An I2C bus signal testing system, method, apparatus, and readable storage medium.

Abstract

This invention proposes an I2C bus signal testing system, method, apparatus, and readable storage medium. The system includes: a BMC chip connected to a CPLD module, an analog-to-digital converter (ADC), an EEPROM memory, a comparator, and a slave module; the CPLD module connected to the ADC, digital-to-analog converter (DAC), and comparator; the BMC chip for reading test commands and performing read / write operations on the slave module; the ADC for acquiring I2C signal voltage values; the DAC for converting a selected reference voltage into an analog signal input to the comparator; the comparator for acquiring the I2C signal from a temperature sensor and obtaining a trigger signal by comparing it with the analog signal of the reference voltage; and the CPLD module for calculating the signal interval time based on the trigger signal, determining whether the timing requirements of the I2C protocol specification are met, and determining the test result. This invention improves testing efficiency by performing multiple measurements on each I2C bus signal, thus improving the reliability of the test results.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to an I2C bus signal testing system, method, apparatus, and readable storage medium. Background Technology

[0002] With the development of IoT technology, the number and scale of servers are increasing daily. Because servers operate 24 / 7, BMC chips are typically used for board-level management to implement out-of-band management functions, including system health monitoring, fan control, fault indication, and alarms. I2C is a bidirectional two-wire synchronous serial bus with low power consumption and strong anti-interference capabilities. It supports multiple host devices and is one of the important buses for BMC chips to perform out-of-band management and communicate with monitored objects on the server host. During product testing, the I2C bus signals of the BMC chip need to be measured to check whether the BMC's management mode is normal.

[0003] During server hardware testing, I2C bus signals need to be tested and verified. The testing standard for I2C signals refers to its bus protocol specification, which defines 11 timing test items for I2C signals, including start signal setup / hold time and data signal setup / hold time. Furthermore, the BMC chip in a server system typically supports 14 I2C buses, each connected to different modules via an I2C switch chip, resulting in a large number of I2C bus signals in the system. Using existing testing methods with an oscilloscope for I2C testing requires engineers to verify the timing test items for each I2C bus signal one by one, which is time-consuming, laborious, and yields unsatisfactory results. Moreover, testing two lines (SCL and SDA) simultaneously requires jumper wire operations on the board, which, if performed improperly, may cause short circuits and damage the board. Summary of the Invention

[0004] To address the above problems, the present invention aims to provide an I2C bus signal testing system, method, apparatus, and readable storage medium, which can improve testing efficiency, perform multiple measurements on each I2C bus signal, improve the reliability of test results, avoid board damage due to improper operation, and reduce hardware costs.

[0005] To achieve the above objectives, the present invention provides the following technical solution: an I2C bus signal testing system, comprising: a BMC chip, a CPLD module, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), an EEPROM memory, a comparator, and a slave module; the BMC chip is data-connected to the CPLD module, the ADC, the EEPROM memory, the comparator, and the slave module, respectively; the CPLD module is data-connected to the ADC, the DAC, and the comparator, respectively.

[0006] The BMC chip is used to establish an I2C bus signal connection with multiple temperature sensors, read test commands, and perform read and write operations on the slave module.

[0007] The analog-to-digital converter is used to acquire the I2C signal voltage value of the I2C bus and input it to the CPLD module;

[0008] The digital-to-analog converter is used to convert the selected reference voltage into an analog signal and input it to the comparator;

[0009] The comparator is used to acquire the I2C signal from the temperature sensor, and obtain a trigger signal by comparing it with the analog signal of the reference voltage, and then input it into the CPLD module;

[0010] The CPLD module is used to calculate the signal interval time based on the trigger signal, and determine the test result by judging whether the timing requirements of the I2C protocol specification are met.

[0011] The EEPROM memory is used to store test instructions.

[0012] Furthermore, the system also includes a Flash memory, which is data-connected to the CPLD module and used to store test data.

[0013] Accordingly, the present invention also discloses an I2C bus signal testing method, comprising the following steps:

[0014] Step 1: After the device is powered on, the I2C signal voltage value is obtained using an analog-to-digital converter;

[0015] Step 2: Read the test instructions from the EEPROM memory using the BMC chip to perform read and write operations on the slave module;

[0016] Step 3: Acquire the I2C signal from one temperature sensor and obtain the trigger signal at the corresponding voltage through a comparator;

[0017] Step 4: Input the trigger signal into the CPLD module and calculate the interval time of the corresponding trigger signal;

[0018] Step 5: Determine whether the interval of the trigger signal meets the timing requirements of the I2C protocol specification. If it does, repeat steps 3-5 to retest the I2C bus signal using the current test command. If it does not meet the requirements, record the current test command.

[0019] Step 6: Record the test data and execute Step 2 to detect the I2C signal of the next temperature sensor until the I2C signal detection of all temperature sensors has been completed.

[0020] Furthermore, step 1 includes:

[0021] After the device is powered on, the I2C bus is in an idle state. At this time, SCL and SDA are both high level. The pull-up voltage Vcc is obtained by the analog-to-digital converter and input to the CPLD module.

[0022] Furthermore, step 3 includes:

[0023] The comparator's reference voltages are selected as 0.7Vcc and 0.3Vcc. These reference voltages are then converted into analog signals by a digital-to-analog converter, denoted as the first voltage V. H With the second voltage V L And input it into the comparator;

[0024] Acquire the I2C signal from one temperature sensor and input the SDA and SCL signals into the comparator;

[0025] The comparator will convert the first voltage V H Second voltage V L The trigger signal is compared with the SDA signal and the SCL signal respectively to obtain the trigger signal at the corresponding voltage and to determine the time corresponding to the trigger signal.

[0026] Furthermore, the comparator will convert the first voltage V H Second voltage V L The signals are compared with the SDA and SCL signals respectively to obtain the trigger signal at the corresponding voltage, and the time corresponding to the trigger signal is determined. Specifically, the first voltage V is... H Two trigger signals are obtained by comparing them with the SDA signal, and their corresponding times are determined to be T4 and T8;

[0027] The first voltage V H Two trigger signals are obtained by comparing them with the SCL signal, and their corresponding times are determined to be T2 and T7;

[0028] The second voltage V L Two trigger signals are obtained by comparing them with the SDA signal, and their corresponding times are determined to be T1 and T5;

[0029] The second voltage V L Two trigger signals are obtained by comparing with SCL, and their corresponding times are determined to be T3 and T6.

[0030] Furthermore, step 4 includes:

[0031] The trigger signal is processed by the CPLD module, and the timing test items of the I2C signal are calculated by a preset formula.

[0032] Timing test items include:

[0033] Initial signal setup time t SU；STA =T8-T7

[0034] Start signal hold time t HD；STA =T2-T1

[0035] Data signal setup time t SU；DAT =T6-T5

[0036] Data signal hold time t HD；DAT =T4-T3.

[0037] Furthermore, the procedure before step 1 includes:

[0038] The I2C bus signal of the BMC chip communicates with the temperature sensor at each different address through the I2C Switch chip;

[0039] Before starting the test, open all channels of the I2C switch chip, scan to obtain the address information corresponding to the connected temperature sensor, and write the test command into the EEPROM memory.

[0040] Accordingly, this invention discloses an I2C bus signal testing device, comprising:

[0041] The memory is used to store I2C bus signal test programs;

[0042] A processor, configured to implement the steps of the I2C bus signal testing method described above when executing the I2C bus signal testing program.

[0043] Accordingly, the present invention discloses a readable storage medium storing an I2C bus signal test program, wherein when the I2C bus signal test program is executed by a processor, it implements the steps of the I2C bus signal test method described in any of the above descriptions.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention discloses an I2C bus signal testing system, method, device and readable storage medium, optimizes the I2C signal testing process, can improve testing efficiency, perform multiple measurements on each I2C bus signal, improve the reliability of test results, avoid the problem of board damage due to improper operation, and reduce hardware costs.

[0045] Therefore, it is evident that the present invention has outstanding substantive features and significant progress compared with the prior art, and the beneficial effects of its implementation are also obvious. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0047] Figure 1 This is a system structure diagram of a specific embodiment of the present invention.

[0048] Figure 2 This is a flowchart illustrating a specific embodiment of the present invention.

[0049] Figure 3 This is a schematic diagram of the trigger signal in a specific embodiment of the present invention. Detailed Implementation

[0050] The core of this invention is to provide an I2C bus signal testing method. In the prior art, according to the existing testing methods, I2C testing is performed using an oscilloscope. Engineers have to verify the timing test items of each I2C bus signal one by one, which is time-consuming, laborious, and the results are not ideal. Furthermore, testing two lines (SCL and SDA) simultaneously requires flying wire operations on the board. Improper operation may cause short circuits on the board, thereby burning out the board.

[0051] The I2C bus signal testing method provided by this invention first involves obtaining the voltage values ​​corresponding to the high and low levels of the I2C signal using an analog-to-digital converter after the testing device is powered on. Then, the test instruction is read from the memory, and the host sends an instruction to initiate master-slave I2C communication. At this time, the signal at the test point is acquired and compared with the output voltage of the digital-to-analog converter to obtain the corresponding trigger signal. This trigger signal is then input to the logic control unit (CPLD), and the interval time of the corresponding trigger signal is calculated. Finally, it is determined whether the interval time of the trigger signal meets the timing requirements of the I2C protocol specification. If the interval time meets the requirements, the I2C bus signal is retested using the current test instruction. After the retest is completed, the test data is recorded. If the interval time does not meet the requirements, the current test instruction and test data are recorded. Therefore, this invention can improve testing efficiency by performing multiple measurements on each I2C bus signal, improving the reliability of test results, avoiding board damage due to improper operation, and reducing hardware costs.

[0052] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] Example 1:

[0054] like Figure 1 As shown, this embodiment provides an I2C bus signal testing system, including: a BMC chip, a CPLD module, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), an EEPROM memory, a comparator, a slave module, and a Flash memory. The BMC chip is data-connected to the CPLD module, the ADC, the EEPROM memory, the comparator, and the slave module, respectively. The CPLD module is data-connected to the ADC, the DAC, the comparator, and the Flash memory, respectively.

[0055] The BMC chip is used to establish I2C bus signal connections with multiple temperature sensors, read test commands, and perform read / write operations on slave modules. Specifically, the BMC chip includes multiple I2C bus signals. Each I2C signal of the BMC chip is identical in hardware design, with each signal having a serial data line SDA and a serial clock line SCL. The BMC chip acts as the master, sending test commands and transmitting and receiving data through SDA and SCL to perform relevant tests.

[0056] An analog-to-digital converter is used to acquire the I2C signal voltage value of the I2C bus and input it into the CPLD module.

[0057] A digital-to-analog converter is used to convert a selected reference voltage into an analog signal input to a comparator.

[0058] The comparator is used to acquire the I2C signal from the temperature sensor and obtain the trigger signal by comparing it with the analog signal of the reference voltage, and then input it into the CPLD module.

[0059] The CPLD module is used to calculate the signal interval time based on the trigger signal and determine the test result by judging whether the timing requirements of the I2C protocol specification are met.

[0060] EEPROM memory is used to store test instructions.

[0061] Flash memory is used to store test data.

[0062] This embodiment provides an I2C bus signal testing system that can improve testing efficiency, perform multiple measurements on each I2C bus signal, improve the reliability of test results, avoid board damage due to improper operation, and reduce hardware costs.

[0063] Example 2:

[0064] Based on Example 1, such as Figure 2 As shown, the present invention also discloses an I2C bus signal testing method, comprising the following steps:

[0065] Step 1: After the device is powered on, the I2C signal voltage value is obtained using an analog-to-digital converter.

[0066] The I2C bus signal is an open-drain output. After the device is powered on, the I2C bus is in an idle state. At this time, both SCL and SDA are high. The pull-up voltage Vcc is obtained using an analog-to-digital converter and input to the CPLD module.

[0067] Step 2: Read the test instructions from the EEPROM memory using the BMC chip to perform read and write operations on the slave module.

[0068] Step 3: Acquire the I2C signal from one temperature sensor and obtain the trigger signal at the corresponding voltage through a comparator.

[0069] Specifically, firstly, the comparator's reference voltages are selected as 0.7Vcc and 0.3Vcc. These reference voltages are converted into analog signals by a digital-to-analog converter, denoted as the first voltage VH and the second voltage VL, and then input into the comparator. Next, an I2C signal from a temperature sensor is acquired, and its SDA and SCL signals are input into the comparator. Finally, the comparator compares the first voltage VH and the second voltage VL with the SDA and SCL signals, respectively, to obtain the trigger signal at the corresponding voltage and determine the corresponding timing of the trigger signal.

[0070] As an example, the comparator's specific execution process is as follows:

[0071] The first voltage V H Two trigger signals are obtained by comparing with the SDA signal, and their corresponding times are determined to be T4 and T8; the first voltage V is... H Two trigger signals are obtained by comparing with the SCL signal, and their corresponding times are determined to be T2 and T7; the second voltage V is... L Two trigger signals are obtained by comparing with the SDA signal, and their corresponding times are determined to be T1 and T5; the second voltage V is... L Two trigger signals are obtained by comparing with SCL, and their corresponding times are determined to be T3 and T6.

[0072] Step 4: Input the trigger signal into the CPLD module and calculate the interval time of the corresponding trigger signal.

[0073] like Figure 3 As shown, the trigger signal is processed by the CPLD module, and the timing test items of the I2C signal are calculated by a preset formula.

[0074] The timing test items include: the setup / hold time t of the initial signal. SU；STA t HD；STA Data signal setup / hold time t SU；DAT t HD；DAT .

[0075] The preset formula is as follows:

[0076] Initial signal setup time t SU；STA =T8-T7

[0077] Start signal hold time t HD；STA =T2-T1

[0078] Data signal setup time t SU；DAT =T6-T5

[0079] Data signal hold time t HD；DAT =T4-T3.

[0080] Step 5: Determine whether the interval of the trigger signal meets the timing requirements of the I2C protocol specification. If it does, repeat steps 3-5 to retest the I2C bus signal using the current test command. If it does not meet the requirements, record the current test command.

[0081] In other words, if the timing requirements are not met, the current test instruction is recorded, and the test data is stored in the Flash memory. If the timing requirements are met, the current test instruction is used for retesting to improve the reliability of the test results. If the retest result also meets the timing requirements, the test data is recorded in the Flash memory.

[0082] Step 6: Record the test data and execute Step 2 to detect the I2C signal of the next temperature sensor until the I2C signal detection of all temperature sensors has been completed.

[0083] At this point, the I2C signal test of one temperature sensor is completed. The BMC chip is notified via UART serial communication to start the I2C signal test of the next temperature sensor. This continues until the I2C signal test data of all temperature sensors is recorded. The CPLD then controls the LED to light up, indicating that the current I2C bus signal test is complete. The tester can understand the test status through the data in the memory.

[0084] In addition, before executing this method, the I2C bus signal of the BMC chip needs to be communicated with each temperature sensor at a different address via an I2C switch chip. Before starting the test, all channels of the I2C switch chip are opened, the address information corresponding to the connected temperature sensors is scanned, and the test instructions are written to the EEPROM memory.

[0085] It should be noted that this embodiment uses the timing test item t of the I2C bus signal sent by the BMC chip to the TEMP Sensor. HD；STA , t HD；DAT , t SU；DAT , t SU；STA Taking this as an example, this method can be extended to 11 timing test items under each I2C bus signal in the server system.

[0086] This embodiment provides an I2C bus signal testing method, which optimizes the I2C signal testing process, improves testing efficiency, performs multiple measurements on each I2C bus signal, improves the reliability of test results, avoids board damage due to improper operation, and reduces hardware costs.

[0087] Example 3:

[0088] This embodiment discloses an I2C bus signal testing device, including a processor and a memory; wherein, when the processor executes the I2C bus signal testing program stored in the memory, it performs the following steps:

[0089] 1. After the device is powered on, the I2C signal voltage value is obtained using an analog-to-digital converter.

[0090] 2. Read test instructions from the EEPROM memory using the BMC chip to perform read and write operations on the slave module.

[0091] 3. Acquire the I2C signal from one temperature sensor and obtain the trigger signal at the corresponding voltage through a comparator.

[0092] 4. Input the trigger signal into the CPLD module and calculate the interval time of the corresponding trigger signal.

[0093] 5. Determine whether the interval of the trigger signal meets the timing requirements of the I2C protocol specification. If it does, repeat steps 3-5 to retest the I2C bus signal using the current test command. If it does not meet the requirements, record the current test command.

[0094] 6. Record the test data and execute step 2 to detect the I2C signal of the next temperature sensor until the I2C signal detection of all temperature sensors has been completed.

[0095] Furthermore, the I2C bus signal testing device in this embodiment may also include:

[0096] The input interface is used to acquire I2C bus signal test programs imported from external sources and save the acquired I2C bus signal test programs to the memory. It can also be used to acquire various instructions and parameters transmitted from external terminal devices and transmit them to the processor so that the processor can perform corresponding processing using these instructions and parameters. In this embodiment, the input interface may specifically include, but is not limited to, a USB interface, a serial interface, a voice input interface, a fingerprint input interface, a hard disk read interface, etc.

[0097] An output interface is used to output various data generated by the processor to connected terminal devices, so that other terminal devices connected to the output interface can obtain the various data generated by the processor. In this embodiment, the output interface may include, but is not limited to, a USB interface, a serial interface, etc.

[0098] A communication unit is used to establish a remote communication connection between the I2C bus signal testing device and an external server, so that the I2C bus signal testing device can mount the image file to the external server. In this embodiment, the communication unit may specifically include, but is not limited to, a remote communication unit based on wireless communication technology or wired communication technology.

[0099] The keyboard is used to acquire various parameter data or commands input by the user through real-time keystrokes.

[0100] The monitor is used to display relevant information in real time regarding the process of locating a short circuit in the server's power supply line.

[0101] A mouse can be used to assist users in inputting data and simplifying user operations.

[0102] Example 4:

[0103] This embodiment also discloses a readable storage medium, which includes random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art. The readable storage medium stores an I2C bus signal test program, which, when executed by a processor, performs the following steps:

[0104] 1. After the device is powered on, the I2C signal voltage value is obtained using an analog-to-digital converter.

[0105] 2. Read test instructions from the EEPROM memory using the BMC chip to perform read and write operations on the slave module.

[0106] 3. Acquire the I2C signal from one temperature sensor and obtain the trigger signal at the corresponding voltage through a comparator.

[0107] 4. Input the trigger signal into the CPLD module and calculate the interval time of the corresponding trigger signal.

[0108] 5. Determine whether the interval of the trigger signal meets the timing requirements of the I2C protocol specification. If it does, repeat steps 3-5 to retest the I2C bus signal using the current test command. If it does not meet the requirements, record the current test command.

[0109] 6. Record the test data and execute step 2 to detect the I2C signal of the next temperature sensor until the I2C signal detection of all temperature sensors has been completed.

[0110] In summary, this invention optimizes the I2C signal testing process, improves testing efficiency, performs multiple measurements on each I2C bus signal, enhances the reliability of test results, avoids board damage due to improper operation, and reduces hardware costs.

[0111] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the systems disclosed in the embodiments; relevant details can be found in the method section.

[0112] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0113] In the embodiments provided by this invention, it should be understood that the disclosed systems, methods, and approaches can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or units may be electrical, mechanical, or other forms.

[0114] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0115] In addition, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit.

[0116] Similarly, in the various embodiments of the present invention, each processing unit can be integrated into a functional module, or each processing unit can exist physically, or two or more processing units can be integrated into a functional module.

[0117] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0118] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0119] The I2C bus signal testing method, system, apparatus, and readable storage medium provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. An I2C bus signal testing system, characterized by, include: The system comprises a BMC chip, a CPLD module, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), an EEPROM memory, a comparator, and a slave module. The BMC chip is connected to the CPLD module, the ADC, the EEPROM memory, the comparator, and the slave module for data transfer. The CPLD module is also connected to the ADC, the DAC, and the comparator for data transfer. The BMC chip is used to establish an I2C bus signal connection with multiple temperature sensors, read test commands, and perform read and write operations on the slave module. The analog-to-digital converter is used to acquire the I2C signal voltage value of the I2C bus and input it to the CPLD module; The digital-to-analog converter is used to convert the selected reference voltage into an analog signal and input it to the comparator; The comparator is used to acquire the I2C signal from the temperature sensor, and obtain a trigger signal by comparing it with the analog signal of the reference voltage, and then input it into the CPLD module; The CPLD module is used to calculate the signal interval time based on the trigger signal, and determine the test result by judging whether the timing requirements of the I2C protocol specification are met. The EEPROM memory is used to store test instructions; If the interval time meets the requirements, the I2C bus signal is retested using the current test command. After the retest is completed, the test data is recorded. If the interval time does not meet the requirements, the current test command and test data are recorded.

2. The I2C bus signal testing system according to claim 1, characterized in that, The system also includes a Flash memory, which is data-connected to the CPLD module and used to store test data.

3. A method for testing I2C bus signals, characterized in that, Includes the following steps: Step 1: After the device is powered on, the I2C signal voltage value is obtained using an analog-to-digital converter; Step 2: Read the test instructions from the EEPROM memory using the BMC chip to perform read and write operations on the slave module; Step 3: Acquire the I2C signal from one temperature sensor and obtain the trigger signal at the corresponding voltage through a comparator; Step 4: Input the trigger signal into the CPLD module and calculate the interval time of the corresponding trigger signal; Step 5: Determine whether the interval of the trigger signal meets the timing requirements of the I2C protocol specification. If it does, repeat steps 3-5 to retest the I2C bus signal using the current test command. If it does not meet the requirements, record the current test command. Step 6: Record the test data and execute Step 2 to detect the I2C signal of the next temperature sensor, until the I2C signal detection of all temperature sensors has been completed; Step 3 includes: The reference voltages of the comparator are selected as 0.7Vcc and 0.3Vcc. The reference voltages are converted into analog signals by a digital-to-analog converter and denoted as the first voltage VH and the second voltage VL, and then input into the comparator. Acquire the I2C signal from one temperature sensor and input the SDA and SCL signals into the comparator; The comparator compares the first voltage VH and the second voltage VL with the SDA signal and the SCL signal, respectively, to obtain the trigger signal at the corresponding voltage and determine the time corresponding to the trigger signal. The comparator compares the first voltage VH and the second voltage VL with the SDA signal and the SCL signal, respectively, to obtain the trigger signal at the corresponding voltage and determine the time corresponding to the trigger signal, specifically: The first voltage VH is compared with the SDA signal to obtain two trigger signals, and their corresponding times are determined to be T4 and T8. The first voltage VH is compared with the SCL signal to obtain two trigger signals, and their corresponding times are determined to be T2 and T7. The second voltage VL is compared with the SDA signal to obtain two trigger signals, and their corresponding times are determined to be T1 and T5. The second voltage VL is compared with SCL to obtain two trigger signals, and their corresponding times are determined to be T3 and T6.

4. The I2C bus signal testing method according to claim 3, characterized in that, Step 1 includes: After the device is powered on, the I2C bus is in an idle state. At this time, SCL and SDA are both high level. The pull-up voltage Vcc is obtained by the analog-to-digital converter and input to the CPLD module.

5. The I2C bus signal testing method according to claim 3, characterized in that, Step 4 includes: The trigger signal is processed by the CPLD module, and the timing test items of the I2C signal are calculated by a preset formula. Timing test items include: Initial signal setup time tSU;STA = T8 - T7 Start signal hold time tHD;STA = T2 - T1 Data signal setup time tSU;DAT = T6 - T5 Data signal hold time tHD;DAT = T4 - T3.

6. The I2C bus signal testing method according to claim 3, characterized in that, Before step 1, the following also applies: The I2C bus signal of the BMC chip communicates with the temperature sensor at each different address through the I2C Switch chip; Before starting the test, open all channels of the I2C switch chip, scan to obtain the address information corresponding to the connected temperature sensor, and write the test command into the EEPROM memory.

7. An I2C bus signal testing device, characterized in that, include: The memory is used to store I2C bus signal test programs; A processor, configured to implement the steps of the I2C bus signal testing method as described in any one of claims 3 to 6 when executing the I2C bus signal testing program.

8. A readable storage medium, characterized in that: The readable storage medium stores an I2C bus signal test program, which, when executed by a processor, implements the steps of the I2C bus signal test method as described in any one of claims 3 to 6.

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