Data processing circuit, method, chip and electronic device

Abstract

The present disclosure relates to a data processing circuit, a method, a chip and an electronic device. The data processing circuit comprises inter-chip communication hardware, a conversion bridge connected with the inter-chip communication hardware, and a plurality of intra-chip communication hardware connected with the conversion bridge. The conversion bridge is configured to continuously receive a plurality of to-be-processed data sent by the inter-chip communication hardware. The conversion bridge and the intra-chip communication hardware corresponding to the plurality of to-be-processed data are configured to process the plurality of to-be-processed data to obtain a processing result corresponding to each to-be-processed data. The conversion bridge is configured to send the processing result corresponding to each to-be-processed data to the inter-chip communication hardware. The data processing circuit provided by the embodiment of the present disclosure can process the chip without interruption in the whole data processing process, which not only improves the data interaction efficiency of the inter-chip communication hardware, but also improves the data interaction efficiency of the processing chip itself.

Description

Technical Field

[0001] This disclosure relates to the field of information processing, and more particularly to a data processing circuit, method, chip, and electronic device. Background Technology

[0002] With the continuous development of electronic devices, more and more hardware is integrated into them. Hardware can communicate with each other through on-chip communication protocols and inter-chip communication protocols. The conversion between different communication methods will directly affect the data processing speed of electronic devices in operation. Therefore, how to better realize communication within electronic devices is a technical problem that developers urgently need to solve. Summary of the Invention

[0003] In view of this, the present disclosure proposes a data processing circuit, which includes inter-chip communication hardware, a conversion bridge connected to the inter-chip communication hardware, and multiple intra-chip communication hardware connected to the conversion bridge. The inter-chip communication hardware represents hardware that interacts with the conversion bridge via an inter-chip communication protocol, and the intra-chip communication hardware represents hardware that interacts with the conversion bridge via an intra-chip communication protocol. The conversion bridge is configured to continuously receive multiple pending data sent by the inter-chip communication hardware. The conversion bridge and the intra-chip communication hardware corresponding to the multiple pending data are configured to process the multiple pending data to obtain a processing result corresponding to each pending data. The conversion bridge is configured to send the processing result corresponding to each pending data to the inter-chip communication hardware.

[0004] In one possible implementation, the data to be processed includes at least one of: an operation instruction, a first access address, a second access address, and data to be written; wherein the operation instruction is used to indicate the operation category for the data to be processed, the first access address is used to access the translation bridge, the second access address is all or part of the address of an on-chip communication hardware to be accessed, and the data to be written is used to indicate the data written by the inter-chip communication hardware to the on-chip communication hardware when the operation instruction is a write instruction.

[0005] In one possible implementation, the conversion bridge is configured to: when the operation instruction is a write instruction and the actual address of the conversion bridge is the same as the first access address, sequentially concatenate at least one second access address and / or at least one data to be written from the plurality of data to be processed to obtain at least one data to be transmitted corresponding to the plurality of data to be processed; wherein the data size of each data to be transmitted is less than or equal to the transmission bandwidth between the conversion bridge and the on-chip communication hardware; the conversion bridge is configured to: sequentially send the at least one data to be transmitted to the first on-chip communication hardware corresponding to the concatenated second access address of the at least one data to be transmitted; the first on-chip communication hardware is configured to: save the data to be written from the at least one data to be transmitted, generate a processing result corresponding to each data to be transmitted from the at least one data to be transmitted, and send it to the conversion bridge as the processing result of the data to be processed corresponding to each data to be transmitted; wherein the processing result includes any one of: data to be written saved successfully, data to be written failed to be saved, address access successful, address access failed.

[0006] In one possible implementation, the conversion bridge is configured to: when the operation instruction is a read instruction and the actual address of the conversion bridge is the same as the first access address, sequentially concatenate at least one second access address among the plurality of data to be processed to obtain a third access address; the conversion bridge is configured to: determine the second on-chip communication hardware corresponding to the third access address; the second on-chip communication hardware is configured to: acquire the data to be read and generate a processing result corresponding to the third access address, send the data to be read and the processing result corresponding to the third access address to the conversion bridge, and use the processing result corresponding to the third access address and / or the data to be read as the processing result corresponding to the plurality of data to be processed; wherein, the processing result includes: address access successful or address access failed.

[0007] In one possible implementation, the conversion bridge is configured to determine, based on preset indication parameters, whether to concatenate the at least one second access address and / or the at least one piece of data to be written.

[0008] In one possible implementation, the conversion bridge is connected to the inter-chip communication hardware via an inter-chip communication bus. The conversion bridge is configured to adjust the level of the clock corresponding to the inter-chip communication bus to a sleep level when the time interval between the conversion bridge receiving the processing result corresponding to each piece of data to be processed is greater than a first preset duration. The sleep level is used to stop sending data to be processed when the inter-chip communication hardware determines that the level corresponding to the clock is a sleep level.

[0009] In one possible implementation, the conversion bridge is configured to: adjust the level of the clock corresponding to the inter-chip communication bus to a working level when the time interval between the conversion bridge receiving the processing result corresponding to each piece of data to be processed is greater than a second preset duration; wherein the working level is used to continue sending the data to be processed when the inter-chip communication hardware determines that the level corresponding to the clock is the working level, and the second preset duration is greater than the first preset duration.

[0010] In one possible implementation, the translation bridge is configured to update the configuration parameters in response to a change in the configuration parameters; wherein the configuration parameters include at least one of a third access address size, a first preset duration, a second preset duration, and an indication parameter.

[0011] In one possible implementation, the inter-chip communication hardware includes a display unit.

[0012] In one possible implementation, the display unit includes a display panel, which includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

[0013] According to another aspect of this disclosure, a data processing method is provided, applied to a data processing circuit. The data processing circuit includes inter-chip communication hardware, a conversion bridge connected to the inter-chip communication hardware, and a plurality of intra-chip communication hardware connected to the conversion bridge. The inter-chip communication hardware represents hardware that interacts with the conversion bridge via an inter-chip communication protocol, and the intra-chip communication hardware represents hardware that interacts with the conversion bridge via an intra-chip communication protocol. The data processing method includes: continuously receiving a plurality of data to be processed sent by the inter-chip communication hardware through the conversion bridge; processing the plurality of data to be processed through the conversion bridge and the intra-chip communication hardware corresponding to the plurality of data to be processed to obtain a processing result corresponding to each data to be processed; and sending the processing result corresponding to each data to be processed to the inter-chip communication hardware through the conversion bridge.

[0014] In one possible implementation, the data processing circuit is the data processing circuit described above.

[0015] According to another aspect of this disclosure, a chip is provided, the chip including a processing unit and the aforementioned data processing circuit.

[0016] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the above-described chip.

[0017] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing instructions stored in the memory.

[0018] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided that stores computer program instructions thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method.

[0019] According to another aspect of this disclosure, a computer program product is provided, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0020] The data processing circuit provided in this embodiment includes inter-chip communication hardware, a conversion bridge connected to the inter-chip communication hardware, and multiple on-chip communication hardware connected to the conversion bridge. The conversion bridge is configured to continuously receive multiple data to be processed sent by the inter-chip communication hardware. The conversion bridge and the on-chip communication hardware corresponding to the multiple data to be processed are configured to process the multiple data to be processed to obtain a processing result corresponding to each data to be processed. The conversion bridge is configured to send the processing result corresponding to each data to be processed to the inter-chip communication hardware. The data processing circuit provided in this embodiment can replace the processing chip in related technologies with a conversion bridge for interaction between the inter-chip communication hardware and the on-chip communication hardware. The processing chip does not need to be interrupted during the entire data processing flow. In addition, since the services of the processing chip and the conversion bridge have a certain degree of independence, this embodiment not only improves the data interaction efficiency of the inter-chip communication hardware, but also improves the data interaction efficiency of the processing chip itself.

[0021] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0023] Figure 1 A reference schematic diagram of a data processing circuit in the related art according to an embodiment of the present disclosure is shown.

[0024] Figure 2A block diagram of a data processing circuit provided according to an embodiment of the present disclosure is shown.

[0025] Figure 3 A reference schematic diagram of a data processing circuit provided according to an embodiment of the present disclosure is shown.

[0026] Figure 4 A reference schematic diagram showing the timing of a write operation according to an embodiment of the present disclosure is shown.

[0027] Figure 5 A reference schematic diagram showing the timing of a read operation provided according to an embodiment of the present disclosure is shown.

[0028] Figure 6 A flowchart of a data processing method provided according to an embodiment of the present disclosure is shown.

[0029] Figure 7 A block diagram of an electronic device provided according to an embodiment of the present disclosure is shown. Detailed Implementation

[0030] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0031] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0033] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0034] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0035] See Figure 1 As shown, Figure 1 A reference schematic diagram of a data processing circuit in the related art according to an embodiment of the present disclosure is shown, in conjunction with... Figure 1As shown, this example uses I2C (Inter-Integrated Circuit, a bidirectional two-wire synchronous serial bus) as the inter-chip communication protocol and AHB (Advanced High Performance Bus, an on-chip system bus) as the intra-chip communication protocol. Here, the initiator of the interaction request is regarded as the master of the inter-chip communication protocol or the intra-chip communication protocol, and the receiver of the interaction request is regarded as the slave of the inter-chip communication protocol or the intra-chip communication protocol. Then, the I2C master can complete the interface communication between the devices on the bus (I2C slave and I2C master are connected through the I2C bus) through two bidirectional input and output lines, SDA (Serial Data, serial data line in the I2C bus) and SCL (Serial Clock, serial clock line in the I2C bus). The hardware connected to I2C can act as both a master and a slave. The I2C master interacts with the I2C slave via SDA / SCL, and the I2C slave then interacts with the MCU (Micro Controller Unit, or processing chip) via the AHB bus, realizing the communication interaction conversion between inter-chip communication hardware and intra-chip communication hardware. For example, the I2C slave may internally include a read data buffer (such as a Read FIFO, or Read First Input First Output), a write data buffer (such as a Write FIFO, or Write First Input First Output), an I2C state machine, and an I2C counter (the definitions of these devices can be found in related technologies, and will not be elaborated upon in this embodiment). When the I2C slave receives a command from the I2C master, it stores the command data in the data buffer and initiates an MCU interrupt. The MCU then parses the command and executes the corresponding operation. When an I2C slave receives data, the SDA_IN data (sent from the I2C master to the I2C slave) is shifted and buffered into the rx_shifter (a type of shift register). Once one byte is full, the data is filled into the write data buffer, and an interrupt is initiated to notify the MCU to retrieve the data. When the I2C slave needs to send data, it initiates an interrupt to notify the MCU to retrieve the data and write it into the read data buffer. The I2C slave then reads the data from the read data buffer and shifts it via the tx_shifter (a type of shift register) to send it to SDA_OUT (sent from the I2C slave to the I2C master). Since the I2C transmission unit is one byte, the I2C slave needs to frequently initiate interrupts to the MCU while executing commands from the master. The MCU responds to the interrupts and parses the instructions before it can read and write to the AHB hardware such as the device's internal memory and registers.This method of responding to the I2C host requires waiting for the MCU to respond to an interrupt and parse the instruction before accessing the AHB hardware can be completed, which is time-consuming and inefficient. At the same time, the MCU also needs to frequently respond to I2C interrupts, further impacting its efficiency.

[0036] In view of this, embodiments of this disclosure provide a data processing circuit, which includes inter-chip communication hardware, a conversion bridge connected to the inter-chip communication hardware, and multiple on-chip communication hardware connected to the conversion bridge. The conversion bridge is configured to continuously receive multiple data to be processed sent by the inter-chip communication hardware. The conversion bridge and the on-chip communication hardware corresponding to the multiple data to be processed are configured to process the multiple data to be processed to obtain a processing result corresponding to each data to be processed. The conversion bridge is configured to send the processing result corresponding to each data to be processed to the inter-chip communication hardware. The data processing circuit provided by embodiments of this disclosure can replace the processing chip in related technologies for interaction between inter-chip communication hardware and on-chip communication hardware through the conversion bridge. The processing chip does not need to be interrupted during the entire data processing flow. In addition, since the services of the processing chip and the conversion bridge have a certain degree of independence, embodiments of this disclosure not only improve the data interaction efficiency of the inter-chip communication hardware, but also improve the data interaction efficiency of the processing chip itself.

[0037] See Figure 2 As shown, Figure 2 A block diagram of a data processing circuit according to an embodiment of the present disclosure is shown, in conjunction with... Figure 2As shown, the data processing circuit 100 may include: inter-chip communication hardware 110, a conversion bridge 120 connected to the inter-chip communication hardware, and multiple on-chip communication hardware 130 (only one is shown in the figure) connected to the conversion bridge. The inter-chip communication hardware refers to hardware that interacts with the conversion bridge via an inter-chip communication protocol, and the on-chip communication hardware refers to hardware that interacts with the conversion bridge via an on-chip communication protocol. Exemplarily, the inter-chip communication hardware may include: an inter-chip communication slave and an inter-chip communication master; the on-chip communication hardware may include: an on-chip communication slave and an on-chip communication master, etc., and this embodiment does not impose limitations. The inter-chip communication protocol may include: I2C, SPI (Serial Peripheral Interface), etc., and the on-chip communication protocol may include: AHB, AXI (Advanced eXtensible Interface), etc. The conversion bridge is configured to continuously receive multiple unprocessed data sent by the inter-chip communication hardware. For example, the data to be processed can be flexibly set according to the data transmission rules of the inter-chip communication protocol, and this embodiment of the present disclosure does not impose any limitations. For example, the conversion bridge and the inter-chip communication hardware can be connected through an inter-chip communication protocol bus. Taking the I2C protocol as an example, the inter-chip communication protocol bus can be an I2C bus. The conversion bridge and the on-chip communication hardware corresponding to the plurality of data to be processed are configured to: process the plurality of data to be processed to obtain a processing result corresponding to each data to be processed. The conversion bridge is configured to: send the processing result corresponding to each data to be processed to the inter-chip communication hardware. The processing result can be simply set as a response to the reception of the data to be processed. It should be understood that the processing result can also be flexibly set by the developers according to the actual situation, and this embodiment of the present disclosure does not impose any limitations.

[0038] In one possible implementation, the data to be processed may include at least one of: an operation instruction, a first access address, a second access address, and data to be written. The operation instruction indicates the type of operation for the data to be processed; the first access address is used to access a translation bridge; the second access address is all or part of the addresses of an on-chip communication hardware to be accessed; and the data to be written represents data written by the inter-chip communication hardware to the on-chip communication hardware when the operation instruction is a write instruction. For example, taking the I2C protocol as the inter-chip communication protocol and the AHB protocol as the intra-chip communication protocol, the data to be processed may include: a transmission start signal to indicate the start of the transmission process, a transmission end signal to indicate the end of the transmission process (for example, if I2C can transmit 1 byte of data at a time, and a total of 3 bytes of data are transmitted, then the transmission end signal can be added to the end of the 3 bytes of data transmitted, and the transmission start signal and the start / end signal do not occupy the space of 1 byte of data), an operation instruction to indicate a read operation or a write operation, a first access address required by the I2C host to access the conversion bridge, a second access address required by the conversion bridge to access the AHB slave, and, when the operation instruction indicates to perform a write operation, the conversion bridge is used to write the data to be written required by the AHB slave, etc. Developers can also flexibly set the composition of the data to be processed according to actual needs, and this embodiment of the disclosure is not limited thereto.

[0039] In one possible implementation, the conversion bridge is configured to: when the operation instruction is a write instruction and the actual address of the conversion bridge is the same as the first access address, sequentially concatenate at least one second access address and / or at least one data to be written from the plurality of data to be processed to obtain at least one data to be transmitted corresponding to the plurality of data to be processed. The data size of each data to be transmitted is less than or equal to the transmission bandwidth between the conversion bridge and the on-chip communication hardware. The conversion bridge is configured to: sequentially send the at least one data to be transmitted to the first on-chip communication hardware corresponding to the concatenated second access address of the at least one data to be transmitted. The first on-chip communication hardware is configured to: save the data to be written from the at least one data to be transmitted, generate a processing result corresponding to each data to be transmitted from the at least one data to be transmitted, and send this processing result to the conversion bridge as the processing result of the data to be processed corresponding to each data to be transmitted. The processing result includes any one of: data to be written saved successfully, data to be written failed to be saved, address access successful, and address access failed. In one possible implementation, the conversion bridge is configured to determine, based on preset indication parameters, whether to concatenate the at least one second access address and / or the at least one piece of data to be written. Exemplarily, the on-chip communication hardware and the conversion bridge can be connected via an on-chip communication bus. It should be understood that the above processing result can also be set according to the actual needs of the developers.

[0040] In one possible implementation, the conversion bridge is configured to: when the operation instruction is a read instruction and the actual address of the conversion bridge is the same as the first access address, sequentially concatenate at least one second access address from the plurality of data to be processed to obtain a third access address. The conversion bridge is configured to: determine the second on-chip communication hardware corresponding to the third access address. The second on-chip communication hardware is configured to: acquire the data to be read and generate a processing result corresponding to the third access address, send the data to be read and the processing result corresponding to the third access address to the conversion bridge, and use the processing result corresponding to the third access address as the processing result corresponding to the plurality of data to be processed. The processing result includes: address access successful or address access failed. It should be understood that the above processing result can also be set according to the actual needs of the developers.

[0041] In one possible implementation, the conversion bridge is connected to the inter-chip communication hardware via an inter-chip communication bus. The conversion bridge is configured to adjust the clock level of the inter-chip communication bus to a sleep level when the time interval between receiving the processing result corresponding to each piece of data to be processed by the conversion bridge is greater than a first preset duration. The sleep level is used to stop sending data to be processed when the inter-chip communication hardware determines that the clock level is a sleep level. Exemplarily, the specific value of the first preset duration is not limited in this embodiment, and developers can set it according to actual conditions. For example, taking the I2C bus as an example, the sleep level can be a low level of SCL. When the inter-chip communication hardware determines that SCL is low on the bus, the transmission of data to be processed to the conversion bridge can be paused.

[0042] In one possible implementation, the conversion bridge is configured to adjust the clock level of the inter-chip communication bus to a working level when the time interval between receiving the processing result corresponding to each piece of data to be processed by the conversion bridge is greater than a second preset duration. The working level is used to continue sending data to be processed when the inter-chip communication hardware determines that the clock level is the working level, and the second preset duration is greater than the first preset duration. Exemplarily, the specific value of the second preset duration is not limited in this embodiment, and developers can set it according to actual conditions. For example, taking the I2C bus as an example, the working level can be a high level of SCL; when the inter-chip communication hardware determines that SCL is high on the bus, the transmission of data to be processed by the conversion bridge can continue.

[0043] In one possible implementation, the conversion bridge is configured to update the configuration parameters in response to changes in the configuration parameters. The configuration parameters include at least one of: a third access address size, a first preset duration, a second preset duration, and an indication parameter. Exemplarily, the configuration parameters can be automatically set by the conversion bridge based on the bandwidth of the inter-chip communication bus, the bandwidth of the intra-chip communication bus, and the operating state of the conversion bridge. For example, if the current intra-chip communication bus bandwidth is 64 bits and the inter-chip communication bus bandwidth is 8 bits, the conversion bridge can concatenate eight 8-bit data packets into a single data packet to be transmitted and send it to the intra-chip communication hardware by setting the indication parameter. The concatenated data packet should not exceed the bandwidth of the intra-chip communication bus. Continuing the example, if the data packet size is 32 bits and the intra-chip communication hardware response is slow, the data packet size can be set to 40 bits (the original data packet size plus several intra-chip communication bus bandwidths), 48 bits, 56 bits, or 64 bits by setting the indication parameter. Developers can also set it manually, and this disclosure does not impose any limitations on the embodiments herein.

[0044] In one possible implementation, the inter-chip communication hardware includes a display unit. Exemplarily, the display unit is used to implement the display function of the data processing circuit. In another possible implementation, the display unit includes a display panel, which includes at least one of the following: a liquid crystal display panel, a micro-LED display panel, an LED display panel, a mini LED display panel, a quantum dot LED display panel, an organic LED display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

[0045] See Figure 3 As shown, Figure 3 A reference schematic diagram of a data processing circuit according to an embodiment of the present disclosure is shown. (In conjunction with...) Figure 3 This disclosure provides a practical application scenario for reference. Here, the inter-chip communication protocol is I2C and the intra-chip communication protocol is AHB, with the basic unit of I2C data transmission being 1 byte (i.e., 8 bits). The conversion bridge may include multiple virtual or hardware modules, including an I2C slave (i.e.,... Figure 3 The I2C slave module), AHB master (i.e. Figure 3 The AHB host module, transmission control module, and clock extension module (i.e., Figure 3 The I2C clock extension module and register configuration module (i.e.) Figure 3Regarding the register module (in the code), it should be understood that the aforementioned virtual or hardware module may not need to be configured in the actual circuit layout. That is, the actual hardware as a whole still functions as a conversion bridge. For example, the I2C slave and AHB master can actually be the same hardware module, or they can be two separate hardware modules. Developers can configure them according to the actual situation. The conversion bridge communicates with multiple AHB slaves (i.e., the multiple on-chip communication hardware mentioned above) via the AHB bus. Figure 3 The AHB slaves 1 to N are connected. The conversion bridge, AHB bus, and AHB slaves can be housed on the same integrated circuit (IC). The conversion bridge is connected to the I2C master via SDA and SCL. After receiving the transmission enable signal from the I2C master, the I2C slave first checks the first byte received. The first byte consists of a 7-bit device address (i.e., the first access address mentioned above) and a 1-bit read / write flag (i.e., the operation instruction mentioned above). If the device address sent by the I2C master does not match the I2C slave, the I2C slave will not respond to the request from the master. If the device address matches, the I2C slave will execute the corresponding operation according to the 8th bit of the first byte's read / write flag. During a write operation, the I2C slave serially collects data from the I2C master and writes the i2c_rx_shift data (data buffered by rx_shifter mentioned above, i.e., ...) byte by byte. Figure 3 The data (shifted from the I2C slave module to the AHB master module) is transferred to the AHB master module. When performing a read operation, the I2C slave transmits the data from the AHB master, i2c_tx_shift (data buffered by tx_shifter mentioned above, i.e., ...). Figure 3The shifted data (from the AHB master module to the I2C slave module) is transmitted back to the I2C master in a serial shift manner. This process continues until the I2C master sends a transmission end signal, indicating the transmission with the I2C master is complete. The I2C slave then returns to an idle state, waiting for the next transmission to begin. Upon receiving the transmission start signal or transmission end signal, and upon completing the transmission of each byte, the I2C slave can send corresponding indication signals to the transmission control module for AHB transmission determination. The AHB master completes the conversion between I2C data and AHB data and, after the transmission control module sends a start signal, sends a transmission request to the AHB bus according to the AHB bus specification. When the I2C slave receives a read / write flag indicating a write operation, the AHB master concatenates the i2c_rx_shift data from the I2C slave (including at least one second access address and at least one piece of data to be written mentioned above) to obtain the AHB bus transmission address haddr (i.e., the concatenated second access address mentioned above) and the write transmission data hwdata (i.e., the data to be written in at least one piece of data to be transmitted mentioned above). After receiving the start signal from the transmission control module, the AHB master sends the bus address and bus data to the AHB bus, issues a write request to the AHB slave, and informs the transmission control module of the transmission completion signal (i.e., the processing result mentioned above) after the corresponding AHB slave completes the transmission. When the I2C slave receives a read / write flag indicating a read operation, the AHB master concatenates the i2c_rx_shift data from the I2C slave to obtain the AHB bus transmission address haddr (i.e., the third access address mentioned above). Subsequently, upon receiving the start signal from the transmission control module, the AHB master sends the bus address to the AHB bus, issuing a read request to the AHB slave. After the corresponding AHB slave completes the transmission, it notifies the transmission control module of the completion signal. Simultaneously, it sends the read transmission data hrdata (i.e., the data to be read mentioned above) returned by the AHB slave back to i2c_tx_shift for the I2C slave's read response to the I2C master. Exemplarily, the bit width of the AHB bus transmission address and read / write data can also be flexibly configured through the register control module according to the actual application situation, thereby ensuring compatibility with AHB bus bit widths in different application scenarios. This disclosure does not impose any limitations on this embodiment.

[0046] For example, the transmission control module receives an indication signal flag from the I2C slave (instructing the AHB master to begin the corresponding operation, which can occur after the I2C slave has received the data to be processed), and controls the AHB master to send the corresponding bus transmission to the AHB slave after preparing the AHB bus address and transmission data. Simultaneously, based on the AHB slave's transmission response, it determines whether the bus transmission bridge needs to initiate a clock extension on the I2C bus, thereby preventing the I2C master from issuing new transmission requests and thus avoiding communication errors if the AHB slave's response is not timely. The transmission control module can determine the frequency of AHB bus transmission (which can also be considered as the size of a single transmission) through register configuration (i.e., the indication parameters mentioned above) according to actual conditions. For example, the default AHB bus width can be 32 bits, meaning the maximum width of AHB bus data transmission is 32 bits.

[0047] In one example, the preset indication parameters indicate that the at least one second access address and / or the at least one piece of data to be written should not be concatenated. After completing the device address matching, for a write operation, the AHB master first collects four i2c_rx_shift data sent by the I2C slave module to form a 32-bit AHB bus address haddr. Subsequently, each time it receives i2c_rx_shift data from the I2C slave, it sends an 8-bit (or 1-byte) AHB bus transmission. Simultaneously, after each round of transmission, the previous bus address haddr is automatically incremented by 1 (depending on the actual situation, the bus address of each on-chip communication hardware can be an address range; after incrementing haddr, it should still be within the bus address range of the on-chip communication hardware to be accessed), waiting for the next 1-byte data to arrive before initiating a new transmission. For a read operation, the transmission control module controls the AHB master to initiate an 8-bit read transmission to the AHB slave, and then assigns the data to i2c_tx_shift for serial transmission by the I2C slave, completing the response to the I2C master. In this example, the transmission mode provided by this disclosure embodiment is relatively simple in logic execution, but it increases the number of interactions between the AHB slave and the AHB master.

[0048] In one example, after matching the device address, the AHB master first collects the 32-bit AHB bus address `haddr`, composed of four `i2c_rx_shift` data packets from the I2C slave. Then, it needs to flexibly adjust the AHB transmission bit width based on the specific address value and the `i2c_stop` signal. In a 32-bit AHB bus, bus transmission can be divided into 8-bit byte transmission, 16-bit half-word transmission, and 32-bit word transmission. Therefore, when conditions are met, during a write operation, the transmission control module will choose to collect more bytes before initiating an AHB bus transmission all at once. When the `haddr` bus address sent by the I2C master is word-aligned, if `i2c_stop` has not arrived, the transmission control module will collect four bytes before initiating a word transmission. If `i2c_stop` arrives early, the transmission control module can also control the AHB master to send single byte, half-word, and combined byte + half-word transmissions under different circumstances to handle situations where the I2C slave sends one, two, or three bytes before the I2C master initiates `i2c_stop`. Depending on the alignment of the bus address (haddr) and the arrival time of I2C_stop, the transmission control module can issue the following four types of transmissions: 8-bit, 16-bit, and 32-bit single byte transmissions, half-word transmissions, word transmissions, and two-transmission combinations of 8-bit followed by 16-bit and 16-bit followed by 8-bit. The same applies to read operations; utilizing the 32-bit AHB bus width also reduces the number of bus accesses, with a single bus transmission satisfying at most four I2C master read accesses. In this example, the transmission mode provided by this embodiment reduces the number of interactions between the AHB slave and the AHB master, thus reducing power consumption. Furthermore, it also reduces the number of clock extensions required due to untimely AHB slave responses, meaning the inter-chip communication bus spends less time in sleep mode.

[0049] The clock extension module receives a delayed clock request from the transmission control module (i.e., Figure 3 In the context of delayed SCL, under normal circumstances, SCL does not require a delay operation, that is... Figure 3The default SCL in the I2C bus has no delay until a delayed clock request is received. When the transmission control module determines that the AHB slave is not responding in time and the bus bridge cannot respond to a new I2C bus transmission request, the clock extension module will initiate clock extension by pulling the level of the I2C bus clock SCL low (the low level is the sleep level mentioned above), preventing the I2C master from initiating a new transmission request. After the I2C master detects that SCL is pulled low, it knows that the I2C slave needs extra time to respond and will wait for the I2C slave to release SCL (the level after releasing SCL is the working level mentioned above) before continuing to attempt communication. In addition, the clock extension module can have a built-in timeout system. When the AHB slave does not respond to the transmission request issued by the conversion bridge for too long, the clock extension module will also release SCL to allow a new transmission. In this case, the previous transmission will be discarded and the corresponding flag bit will be pulled up. The register configuration module itself can act as an AHB slave, used to adjust the configuration of the entire conversion bridge according to the actual situation, such as the address width of the AHB bus (i.e., the size of the third access address mentioned above), the maximum response time of the timeout system (i.e., the second preset duration mentioned above), the control mode of the transmission control module (i.e., the indication parameters mentioned above), etc. It can also be used to characterize the current working status of the transmission bridge, etc.

[0050] See Figure 4 , Figure 4 A reference schematic diagram illustrating the timing of a write operation according to an embodiment of this disclosure is shown. Here, an example is used where the inter-chip communication hardware is an I2C master and the intra-chip communication hardware is an AHB slave. Combined with... Figure 4 , Figure 4The squares with slashes represent actions performed by the master (I2C master or AHB master), while the squares without slashes represent actions performed by the slave (I2C slave or AHB slave). In a write operation, the I2C master sends a start transmission indication, matches the I2C slave address with the I2C slave, and performs the write operation on the successfully matched I2C slave. The I2C slave returns a successful reception response to the I2C master. If the I2C bus bandwidth is 8 bits, the AHB bus bandwidth is 32 bits, and the AHB slave address is 32 bits, then after sending every 8 bits of the second access address 0 (part of the AHB slave address) to the I2C slave, the I2C slave can send a success reception response in sequence. Repeating this four times yields the 32-bit AHB slave access address. After sending 32 bits of data, the I2C master begins to send 8 bits of data to be written (0) to the I2C slave in sequence. After receiving each 8 bits of data to be written (0), the I2C slave can send a success reception response once. Repeating this four times yields 32 bits of data to be transmitted. Then, the writing begins in the AHB slave device. The data to be written, 4n (where n is the bandwidth of the I2C bus), is sent to the AHB slave device. The AHB slave device then sends a response command to the AHB master device. The I2C slave device, which is interacting with the AHB master device, then sends a response command to the I2C master device. Finally, the I2C master device ends the writing operation.

[0051] See Figure 5 As shown, Figure 5 A reference schematic diagram showing the timing of a read operation according to an embodiment of the present disclosure is shown. (In conjunction with...) Figure 5 Continuing the previous example, in the read operation, the I2C master begins by matching the I2C slave address with the I2C slave. For a successfully matched I2C slave, a write operation is performed. The I2C slave returns a successful reception response to the I2C master. After sending 8 bits of data 0 (part of the AHB slave address) to the I2C slave, the I2C slave can send a successive successful reception response. This is repeated four times to obtain the 32-bit AHB slave access address (i.e., the third access address mentioned above). The I2C master ends its operation and waits for the I2C slave to return the data to be read. The AHB master begins its operation, informing the AHB slave to start the read operation. After the AHB slave sends a response, it reads 8 bits of data 0 corresponding to the third access address, repeating this four times to obtain 32 bits of data to be read, i.e., data 4n in the diagram. After receiving the data, the AHB master ends its operation on the AHB slave (manifested as no response) and sends the data to be read back to the I2C master. The I2C master's read operation process ends.

[0052] The data processing circuit provided in this disclosure can replace the processing chip with a conversion bridge for interaction between on-chip communication hardware and inter-chip communication hardware, reducing the number of interrupts generated by the inter-chip communication hardware to the processing chip, thereby reducing the degree of interference with the normal operation of the processing chip. Furthermore, this disclosure embodiment can also concatenate at least one second access address and at least one piece of data to be written. In this case, the number of interactions between the conversion bridge and the on-chip communication hardware can be reduced, thereby reducing the number of clock extensions required due to untimely responses from the on-chip communication hardware, reducing transmission power consumption, and improving the transmission efficiency when communicating between the inter-chip communication hardware and the conversion bridge.

[0053] See Figure 6 As shown, Figure 6 A flowchart of a data processing method according to an embodiment of the present disclosure is shown. Figure 6 This disclosure also provides a data processing method applied to a data processing circuit. The data processing circuit includes inter-chip communication hardware, a conversion bridge connected to the inter-chip communication hardware, and multiple intra-chip communication hardware connected to the conversion bridge. The inter-chip communication hardware represents hardware that interacts with the conversion bridge via an inter-chip communication protocol, and the intra-chip communication hardware represents hardware that interacts with the conversion bridge via an intra-chip communication protocol. The data processing method includes: step S100, continuously receiving multiple data to be processed sent by the inter-chip communication hardware through the conversion bridge.

[0054] Step S200: The multiple data to be processed are processed through the conversion bridge and the on-chip communication hardware corresponding to the multiple data to be processed, and the processing result corresponding to each data to be processed is obtained.

[0055] Step S300: Send the processing result corresponding to each piece of data to be processed to the inter-chip communication hardware through the conversion bridge.

[0056] In one possible implementation, the data to be processed includes at least one of: an operation instruction, a first access address, a second access address, and data to be written; wherein the operation instruction is used to indicate the operation category for the data to be processed, the first access address is used to access the translation bridge, the second access address is all or part of the address of an on-chip communication hardware to be accessed, and the data to be written is used to indicate the data written by the inter-chip communication hardware to the on-chip communication hardware when the operation instruction is a write instruction.

[0057] In one possible implementation, step S200 may include: when the operation instruction is a write instruction and the actual address of the conversion bridge is the same as the first access address, concatenating at least one second access address and / or at least one data to be written among the plurality of data to be processed sequentially through the conversion bridge to obtain at least one data to be transmitted corresponding to the plurality of data to be processed; wherein the data size of each data to be transmitted is less than or equal to the transmission bandwidth between the conversion bridge and the on-chip communication hardware; sequentially sending the at least one data to be transmitted to the first on-chip communication hardware corresponding to the concatenated second access address among the at least one data to be transmitted through the conversion bridge; saving the data to be written among the at least one data to be transmitted through the first on-chip communication hardware, generating a processing result corresponding to each data to be transmitted among the at least one data to be transmitted, and sending it to the conversion bridge as the processing result of the data to be processed corresponding to each data to be transmitted; wherein the processing result includes any one of: data to be written saved successfully, data to be written failed to be saved, address access successful, address access failed.

[0058] In one possible implementation, step S200 may include: when the operation instruction is a read instruction and the actual address of the conversion bridge is the same as the first access address, concatenating at least one second access address from the plurality of data to be processed sequentially through the conversion bridge to obtain a third access address; determining the second on-chip communication hardware corresponding to the third access address through the conversion bridge; acquiring the data to be read and generating a processing result corresponding to the third access address through the second on-chip communication hardware; sending the data to be read and the processing result corresponding to the third access address to the conversion bridge; and using the processing result corresponding to the third access address as the processing result corresponding to the plurality of data to be processed; wherein the processing result includes: address access successful or address access failed.

[0059] In one possible implementation, the data processing method further includes: determining, according to preset indication parameters, whether to concatenate the at least one second access address and / or the at least one piece of data to be written.

[0060] In one possible implementation, the conversion bridge is connected to the inter-chip communication hardware via an inter-chip communication bus, and the data processing method further includes: when the time interval between the conversion bridge receiving the processing result corresponding to each piece of data to be processed is greater than a first preset duration, adjusting the level corresponding to the clock of the inter-chip communication bus to a sleep level via the conversion bridge; wherein, the sleep level is used to stop sending the data to be processed when the inter-chip communication hardware determines that the level corresponding to the clock is a sleep level.

[0061] In one possible implementation, the data processing method further includes: when the time interval between the processing results received by the conversion bridge for each piece of data to be processed is greater than a second preset duration, adjusting the level of the clock corresponding to the inter-chip communication bus to a working level via the conversion bridge; wherein the working level is used to continue sending the data to be processed when the inter-chip communication hardware determines that the level corresponding to the clock is the working level, and the second preset duration is greater than the first preset duration.

[0062] In one possible implementation, the data processing method further includes: updating the configuration parameters in response to a change in the configuration parameters; wherein the configuration parameters include at least one of: a third access address size, a first preset duration, a second preset duration, and an indication parameter.

[0063] In one possible implementation, the inter-chip communication hardware includes a display unit.

[0064] In one possible implementation, the display unit includes a display panel, which includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

[0065] According to another aspect of this disclosure, a chip is provided, the chip including a processing unit and the aforementioned data processing circuit.

[0066] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the above-described chip.

[0067] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described method when executing instructions stored in the memory.

[0068] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided that stores computer program instructions thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method.

[0069] According to another aspect of this disclosure, a computer program product is provided, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0070] For example, the electronic devices in this embodiment include, but are not limited to, desktop computers, televisions, mobile devices with large screens such as mobile phones and tablets, and other common electronic devices that require multiple chips to be cascaded together to achieve driving.

[0071] For example, electronic devices can also be user equipment (UE), mobile devices, user terminals, terminals, handheld devices, computing devices, or in-vehicle devices, etc. Examples of terminals include: displays, smartphones or portable devices, mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, a server can be a local server or a cloud server.

[0072] Figure 7 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. For example, the electronic device 1900 may be provided as a server or a terminal device. (Refer to...) Figure 7 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0073] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output interface 1958. Electronic device 1900 can operate on an operating system stored in memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or similar.

[0074] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0075] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention, which is determined by the appended claims.

[0076] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0077] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0078] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0079] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data processing circuit, characterized in that, The data processing circuit includes inter-chip communication hardware, a conversion bridge connected to the inter-chip communication hardware, and multiple intra-chip communication hardware connected to the conversion bridge. The inter-chip communication hardware represents hardware that interacts with the conversion bridge via an inter-chip communication protocol, and the intra-chip communication hardware represents hardware that interacts with the conversion bridge via an intra-chip communication protocol. The conversion bridge is configured to continuously receive multiple data to be processed sent by the inter-chip communication hardware. The conversion bridge and the on-chip communication hardware corresponding to the plurality of data to be processed are configured to process the plurality of data to be processed and obtain a processing result corresponding to each data to be processed. The conversion bridge is configured to send the processing result corresponding to each piece of data to be processed to the inter-chip communication hardware; The data to be processed includes at least one of the following: operation instructions, a first access address, a second access address, and data to be written. The conversion bridge is configured to perform at least one of the following operations: When the operation instruction is a write instruction and the actual address of the conversion bridge is the same as the first access address, at least one second access address and / or at least one data to be written from the plurality of data to be processed are concatenated in sequence to obtain at least one data to be transmitted corresponding to the plurality of data to be processed. When the operation instruction is a read instruction and the actual address of the conversion bridge is the same as the first access address, at least one second access address among the plurality of data to be processed is concatenated in sequence to obtain a third access address.

2. The data processing circuit as described in claim 1, characterized in that, The operation instruction is used to indicate the operation category for the data to be processed, the first access address is used to access the translation bridge, the second access address is all or part of the address of an on-chip communication hardware to be accessed, and the data to be written is used to indicate the data written by the inter-chip communication hardware to the on-chip communication hardware when the operation instruction is a write instruction.

3. The data processing circuit as described in claim 2, characterized in that, The size of each piece of data to be transmitted is less than or equal to the transmission bandwidth between the conversion bridge and the on-chip communication hardware; The conversion bridge is configured to sequentially send the at least one data to be transmitted to the first on-chip communication hardware corresponding to the concatenated second access address in the at least one data to be transmitted; The first on-chip communication hardware is configured to: save the data to be written in the at least one data to be transmitted, generate a processing result corresponding to each of the at least one data to be transmitted, and send it to the conversion bridge as the processing result of the data to be processed corresponding to each of the at least one data to be transmitted; wherein, the processing result includes any one of: data to be written saved successfully, data to be written failed to be saved, address access successful, address access failed.

4. The data processing circuit as described in claim 2, characterized in that, The conversion bridge is configured to: determine the second on-chip communication hardware corresponding to the third access address; The second on-chip communication hardware is configured to: acquire data to be read and generate a processing result corresponding to the third access address, send the data to be read and the processing result corresponding to the third access address to the conversion bridge, and use the processing result corresponding to the third access address and / or the data to be read as the processing result corresponding to the plurality of data to be processed; wherein, the processing result includes: address access successful or address access failed.

5. The data processing circuit as described in claim 3, characterized in that, The conversion bridge is configured to determine, based on preset indication parameters, whether to concatenate the at least one second access address and / or the at least one piece of data to be written.

6. The data processing circuit as described in claim 1, characterized in that, The conversion bridge is connected to the inter-chip communication hardware via an inter-chip communication bus. The conversion bridge is configured to adjust the level of the clock corresponding to the inter-chip communication bus to a sleep level when the time interval between receiving the processing result corresponding to each piece of data to be processed by the conversion bridge is greater than a first preset duration. The sleep level is used to stop sending data to be processed when the inter-chip communication hardware determines that the level corresponding to the clock is a sleep level.

7. The data processing circuit as described in claim 6, characterized in that, The conversion bridge is configured to: adjust the level of the clock corresponding to the inter-chip communication bus to the working level when the time interval between receiving the processing result corresponding to each piece of data to be processed by the conversion bridge is greater than a second preset duration; wherein, the working level is used to continue sending the data to be processed when the inter-chip communication hardware determines that the level corresponding to the clock is the working level, and the second preset duration is greater than the first preset duration.

8. The data processing circuit as described in claim 1, characterized in that, The conversion bridge is configured to update the configuration parameters in response to a change in the configuration parameters; wherein the configuration parameters include at least one of the following: third access address size, first preset duration, second preset duration, and indication parameters.

9. The data processing circuit as described in any one of claims 1 to 8, characterized in that, The inter-chip communication hardware includes a display unit.

10. The data processing circuit as described in claim 9, characterized in that, The display unit includes a display panel, which includes at least one of the following: liquid crystal display panel, micro light-emitting diode display panel, light-emitting diode display panel, mini light-emitting diode display panel, quantum dot light-emitting diode display panel, organic light-emitting diode display panel, cathode ray tube display panel, digital light processing display panel, field emission display panel, plasma display panel, electrophoretic display panel, electrowetting display panel, and small-pitch display panel.

11. A data processing method, characterized in that, An application is made in a data processing circuit, the data processing circuit including inter-chip communication hardware, a conversion bridge connected to the inter-chip communication hardware, and multiple intra-chip communication hardware connected to the conversion bridge, wherein the inter-chip communication hardware represents hardware that interacts with the conversion bridge via an inter-chip communication protocol, and the intra-chip communication hardware represents hardware that interacts with the conversion bridge via an intra-chip communication protocol. The data processing method includes: The conversion bridge continuously receives multiple data sets to be processed from the inter-chip communication hardware. The multiple data to be processed are processed through the conversion bridge and the on-chip communication hardware corresponding to the multiple data to be processed, and the processing result corresponding to each data to be processed is obtained. The processing result corresponding to each piece of data to be processed is sent to the inter-chip communication hardware through the conversion bridge; The data to be processed includes at least one of the following: operation instructions, a first access address, a second access address, and data to be written. The process involves processing the multiple data to be processed through the conversion bridge and the on-chip communication hardware corresponding to each data to be processed, to obtain a processing result for each data to be processed, including at least one of the following operations: When the operation instruction is a write instruction and the actual address of the conversion bridge is the same as the first access address, the conversion bridge is used to sequentially concatenate at least one second access address and / or at least one data to be written among the plurality of data to be processed to obtain at least one data to be transmitted corresponding to the plurality of data to be processed. When the operation instruction is a read instruction and the actual address of the conversion bridge is the same as the first access address, the conversion bridge is used to concatenate at least one second access address among the plurality of data to be processed to obtain a third access address.

12. The data processing method as described in claim 11, characterized in that, The data processing circuit is the data processing circuit as described in any one of claims 1 to 10.

13. A chip, characterized in that, The chip includes a processing unit and a data processing circuit as described in any one of claims 1 to 10.

14. An electronic device, characterized in that, The electronic device includes the chip as described in claim 13.

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