layered symbiotic network

Abstract

The present disclosure relates to on-chip symbiotic networks. A system on chip (SoC) can include multiple network layers that can facilitate lateral or vertical electrical communication between components from different device layers. In one embodiment, a system on chip (SoC) includes multiple network layers, each network layer including one or more routers, and more than one device layer, each of the multiple network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming multiple network layers in an interconnect, where each network layer is bonded to an active surface of a respective device layer of a plurality of device layers.

Description

[0001] Case Analysis

[0002] This application is a divisional application of Chinese invention patent application No. 202080040869.2, filed on May 26, 2020, entitled "Layered Symbiotic Network".

[0003] Cross-references to related applications

[0004] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 857,578, filed June 5, 2019, the disclosure of which is incorporated herein by reference. Background Technology

[0005] A System-on-a-Chip (SoC) is an integrated circuit that typically includes components of a computer or other such electrical system on a single substrate within a single housing. Components within an SoC can include any combination of processors, memory, controllers, power management, network controllers, and other such computer components. By integrating these components onto a single substrate within a single housing of the SoC, the amount of space occupied by the components can be reduced compared to when the components are implemented discretely.

[0006] A communication subsystem is used to control communication between components of the SoC, as well as communication between SoC components and external components (such as memory not located within the SoC casing). The communication subsystem can route data between SoC components via one or more computer buses and / or crossbar switches. As the number of components within the SoC increases, the number of buses and crossbar switches also increases. In some cases, the length of buses and crossbar switches may also increase. Increased numbers and lengths of buses and crossbar switches can lead to increased SoC power consumption and communication latency.

[0007] In SoCs with three-dimensional (3D) packaging structures, such as multi-layered SoCs, where components of a computer or other such electrical system are located on a substrate in each layer, the 3D footprint of the components can further limit the possible communication paths between and within layers. In this regard, the number of possible paths available to communication subsystems between layers may be limited to locations where components do not overlap on adjacent stacked layers. Therefore, the length of communication paths between components located on different layers can increase, potentially leading to increased power consumption and communication latency in the SoC. Furthermore, a larger component on one layer may block a portion of the substrate of another layer, requiring the communication subsystem of the second layer to route around that component.

[0008] Some SoCs have implemented on-chip network (NoC) communication subsystems. In a NoC communication subsystem, each network interface is associated with a component of the SoC, and the network interface packages data to be passed to other components. The network interface communicates with an interconnected set of routers, which direct the packaged data to its intended destination component. The network interface at the destination component can then unpack the data and pass it to the destination component.

[0009] NoC communication subsystems can reduce communication latency typically encountered in bus and crossbar communication subsystems by routing packaged data to its destination component via a more direct communication path. However, NoC communication subsystems can still suffer latency due to inefficient communication paths caused by the limited space on the substrate resulting from the density of components on the substrate within the SoC. In this regard, NoC communication subsystems may need to route around components, thus increasing the length of the communication path.

[0010] Processors typically use a NoC communication subsystem to retrieve data from cache memories located outside the processor die, such as L2 or L3 cache memories. Given the limited space around the processor chip, the size of the L2 cache memory may be constrained. Thus, the processor may need to rely on L3 cache memories, which are typically slower and located further from the processor die, or off-package cache memories (such as L4 cache memories, which are usually located outside the SoC). The use of a NoC communication subsystem can provide more efficient read and write operations for L3 and L4 caches than previously possible using bus and crossbar switch communication subsystems. However, because data needs to travel a distance between the processor and the L3 and L4 caches, the processor may need to delay processing as it waits for data from the L3 and L4 caches. Summary of the Invention

[0011] This disclosure provides a system-on-a-chip (SoC). The SoC may include multiple network layers and device layers. The multiple network layers may include a first network layer and a second network layer. Each network layer may include one or more routers. The first device layer may include one or more components. The first device layer may have an active surface and an opposing second surface. The active surface may be bonded to the second network layer and the opposing second surface may be bonded to the first network layer.

[0012] In some examples, the first and second network layers are configured to route data to and from one or more components on the first device layer. In some cases, at least one of the one or more components includes a network interface, wherein the network interface connects at least one component to the first and second network layers via a conductive structure. In some cases, the conductive structure includes one or more traces, vias, contacts, or terminals. In some cases, the network interface is configured to pack and unpack data.

[0013] In some examples, the first device layer includes at least one of an application-specific integrated circuit (ASIC) layer or a memory layer.

[0014] In some examples, each of the multiple network layers includes an active surface having one or more contacts; and a second surface opposite the active surface having one or more contacts. In some cases, the second surface of the second network layer is bonded to the active surface of the first device layer, and the active surface of the first network layer is bonded to the second surface of the first device layer.

[0015] In some examples, the SoC includes a memory layer comprising an active surface having one or more contacts, the active surface of the memory layer being bonded to an active surface of a second network layer. In some cases, the memory layer includes one or more memory segments, each of the one or more memory segments being connected via one or more conductive structures to at least one of one or more routers in the second network layer. In some cases, the second network layer is configured to route data between one or more components in the first device layer and the one or more memory segments. In some examples, the bonding between the first device layer and the first and second network layers, and the bonding between the memory layer and the second network layer, are formed via ZiBond direct bonding and / or a hybrid direct bonding interconnect (DBI) bonding.

[0016] In some cases, the SoC includes a second device layer containing one or more components, the second device layer having an active surface and an opposing second surface, the opposing second surface being bonded to the active surface of the second network layer.

[0017] In some cases, the SoC includes a third device layer containing one or more components. The third device layer has an active surface and an opposing second surface, the active surface being bonded to the second surface of a first network layer. In some examples, the first and second network layers are configured to route data between one or more components on the third device layer and one or more components in the second device layer.

[0018] In some cases, the bonding between the first device layer and the first network layer and the second network layer, the bonding between the second device layer and the second network layer, and the bonding between the third device layer and the first network layer are formed via ZiBond direct bonding and / or direct bonding interconnect (DBI) hybrid bonding.

[0019] In some examples, one or more components include one or more of a processor, graphics processing unit (GPU), logic board, digital audio processor (DSP), or network adapter. In some cases, the first and second network layers are configured to ignore faulty memory segments or faulty processors.

[0020] In some examples, one or more routers in the first and second network layers are connected via one or more routing traces in each of the respective network layers.

[0021] In some cases, the first and second network layers are connected to memory located outside the SoC. Attached Figure Description

[0022] Figure 1 This is a side cross-sectional view of a three-layer SoC according to various aspects of this disclosure.

[0023] Figure 2 This is a top view of the application-specific integrated circuit (ASIC) layer according to various aspects of this disclosure.

[0024] Figure 3 This is a side cross-sectional view of the ASIC layer according to various aspects of this disclosure.

[0025] Figure 4 This is a top view of the network layer according to various aspects of this disclosure.

[0026] Figure 5 This is a cross-sectional side view of the interconnection of multiple device layers according to various aspects of this disclosure.

[0027] Figure 6 This is a top view of the memory layer according to various aspects of this disclosure.

[0028] Figure 7 This is a cross-sectional side view of the data communication path through multiple device layers and multiple network layers according to various aspects of this disclosure.

[0029] Figure 8A and Figure 8B A cross-sectional side view depicting the interconnection of device layers and network layers according to various aspects of this disclosure, the interconnection having fillers disposed therein.

[0030] Figure 9A This is a top view of the network layer and device layer components according to various aspects of this disclosure.

[0031] Figure 9B This is a top view of the data communication paths through multiple network layers between different device layers according to various aspects of this disclosure.

[0032] Figure 10A Interconnections of device layers and network layers according to various aspects of this disclosure are shown.

[0033] Figure 10B Interconnections of device layers and network layers according to various aspects of this disclosure are shown.

[0034] Figure 11 This is a perspective view of the memory layer and device layer of a defective memory segment according to various aspects of this disclosure. Detailed Implementation

[0035] This technology involves a System-on-a-Chip (SoC) with one or more network layers. Traditional SoCs utilize communication subsystems (such as NoC) to enable communication between components within the SoC. However, due to the limited availability of space on the SoC substrate, the ability to efficiently route communication subsystems can be hindered, potentially leading to slower data communication between components and, in some cases, processing bottlenecks. As described herein, communication subsystems can be moved to one or more network layers, located above, below, or near device layers, such as application-specific integrated circuit (ASIC) layers and memory layers. By doing so, more efficient routing of the communication subsystems can be achieved, as their routing is not obstructed or otherwise limited by components on the device layer. As a result, the distance data travels during communication can be reduced, and the routing of data to its destination can be more direct.

[0036] In some cases, a memory layer can be located above, below, or near the network layer to provide increased memory availability for the processor or other components on the ASIC layer. Memory on the memory layer can operate as L2 cache memory. Due to the large amount of L2 cache memory on the SoC, the number of data requests from memory located further away from the processor die (such as L3 cache memory or off-package memory such as L4 cache memory) can be significantly reduced, thereby limiting or eliminating the need for off-package data requests and allowing for increased operating frequency.

[0037] Figure 1The diagram illustrates a system-on-chip (SoC) 101 comprising two device layers and one network layer. The SoC 101 includes: a first device layer, such as an application-specific integrated circuit (ASIC) layer 102, and a network layer 104; and a second device layer, such as a memory layer 106. The exemplary structure shown in the SoC 101 depicts only one network layer 104 formed between the ASIC layer 102 and the memory layer 104 for ease of explanation of the operation of the network layer 104. Note that additional network layers may be formed between the various device layers in the SoC 101 as needed, as described in more detail herein.

[0038] Network layer 104 may have an active surface 122 and a second surface 115 opposite to the active surface 122. The active surface 122 of network layer 104 may be bonded to the active surface 116 of memory layer 106. The second surface 115 of network layer 104 may be bonded to the active surface 112 of ASIC layer 102. Although not shown, the second surface 113 of ASIC layer 102 may include or be connected to other electronic components, as described in detail herein.

[0039] As used herein, statements regarding ASIC layer 102, network layer 104, memory layer 106, or another layer having a flat surface, indicating that conductive structures such as contacts, terminals, etc., are "at" or "on" the surface of the layer, indicate that when the respective layer is not assembled with any other element, the conductive structure can be used to contact a theoretical point that moves from outside the layer toward the surface of the layer in a direction perpendicular to the surface of the layer. Therefore, terminals or other conductive structures located at the surface of the layer may protrude from the surface; may be flush with the surface; or may be recessed relative to the surface in a hole or recess in the respective layer. In some embodiments, the conductive structure may be attached to the surface or may be disposed in one or more coatings on said surface.

[0040] exist Figure 1 In this document, the first direction D1 is referred to as the "horizontal" or "lateral" direction (which can be considered as the x-axis), while the direction perpendicular to SoC 101, illustrated by the second direction D2, is referred to as the upward or downward direction and is also referred to as the "vertical" direction or z-axis. Figure 2The diagram illustrates a third direction D3 perpendicular to direction D1. Direction D3 can also be considered a "horizontal" or "lateral" direction, or the y-axis. The directions referred to herein are in the reference frame of the structure in question. Therefore, these directions can be located in any orientation relative to the normal or gravitational reference frame. A statement that one feature is positioned at a higher height "above the surface" than another means that one feature is at a greater distance from the surface compared to the other feature in the same orthogonal direction. Conversely, a statement that one feature is positioned at a lower height "above the surface" than another means that one feature is at a smaller distance from the surface compared to the other feature in the same orthogonal direction.

[0041] Figure 2 A top view of ASIC layer 102 is shown, with active surface 112 removed for clarity. ASIC layer 102 includes substrate 202 and components mounted, manufactured, or otherwise located on substrate 202. Components include processors 220A-220C, graphics processing unit (GPU) 230, logic board 260, digital audio processor (DSP) 270, and network adapter 280. ASIC layer 102 may include any combination of components typically found in ASIC devices or other such computing devices. Components mounted on substrate 202 shown are for illustrative purposes only. More than one ASIC layer or other type of device layer may be included on a SoC.

[0042] As used herein, the term "component" can refer to one or more functional blocks. A functional block can be a single or complex circuit, built into or on a layer to perform certain electrical functions. Components can be interconnected internally or externally to form numerous microcircuits, larger circuits, or any suitable type of integrated circuit. Components and functional blocks as described herein can be applied to any type or number of electrical structures and / or elements as needed.

[0043] Each component in ASIC layer 102 may include a network interface that enables the component to communicate via the network in network layer 104 as described herein. Figure 2 Network interfaces are shown, including network interfaces 221A-221C in processors 220A-220, network interface 231 in GPU 230, network interface 261 in logic board 260, network interface 271 in DSP 270, and network interface 281 in network adapter 280. Although Figure 2 The network interfaces are illustrated as being within their respective components, but network interfaces may be located near their respective components.

[0044] The substrate 202 of the ASIC layer 102 may be made of one or more semiconductor materials, such as materials including at least one of the following: crystalline silicon (e.g., Si). <100> or Si <111> The substrate 202 may be made of materials such as semiconductor materials, ceramics, glass, liquid crystal polymer materials, composite materials such as glass epoxy resin or fiber-reinforced composite materials, laminates, or combinations thereof. In some embodiments, the substrate 202 (or any substrate disclosed herein) may be made of materials such as semiconductor materials, ceramics, glass, liquid crystal polymer materials, composite materials such as glass epoxy resin or fiber-reinforced composite materials, laminates, or combinations thereof.

[0045] When layers are bonded face-to-face (e.g., active surface to active surface, active surface to second surface, or second surface to second surface, as described herein), the longitudinal distance between device layers and / or between device layers and network layers can be as small as micrometers. The longitudinal distance from the bottom of a layer through the layer to the adjacent face-to-face bonded layer, such that this distance includes the layer thickness, can be from 5 μm to 55 μm, although the distance can be smaller or larger depending on the substrate and layer thickness. The lateral distance across layers can be several millimeters. In this case, additional circuitry, such as repeaters, inverters, and / or buffers, may be required to maintain the signal integrity needed to travel across that electrical load over such a long distance. For example, if there is a multiprocessor device, the distance required between a given processor and shared memory or crossbar switch may be several millimeters due to the need to traverse the width of another processor.

[0046] refer to Figure 1 The active surface 112 and the second surface 113 of the ASIC layer 102 can be configured to provide electrical interconnects between the ASIC layer 102 and other layers in the SoC 101 or other components outside the SoC 101. For example, and as... Figure 3 As shown in the enlarged side view of the ASIC layer 102, the second surface 113 may include a conductive structure including terminals 303 on its lower surface 301. Terminals 303 may be configured for electrical connections between components formed in the ASIC layer 102, network layer 104, and / or memory layer 106, and for electrical connections to one or more components external to the SoC 101, such as a printed circuit board (PCB), power supply, etc. For clarity, components such as processors 220A-220C, GPU 230, etc., are not shown on the ASIC layer 102. Figure 3 The ASIC layer 102 is shown. An exemplary embodiment of where components may be located within the ASIC layer 102 is shown. Figure 5The diagram is shown in the figure and will be described further herein. Terminals 303 can be arranged according to the surface mount package type, such as ball grid array (BGA), pin grid array (PGA), or pad grid array (LGA). In some cases, there may be approximately 1000 terminals on the lower surface 301 of the second surface 113.

[0047] like Figure 3 As further illustrated, the active surface 112 of the ASIC layer 102 may include conductive structures, including contacts 313 on its upper surface 311. Contacts 313 may be configured to align with corresponding contacts 314 on the network layer 104 (e.g., ...). Figure 5 (as shown in the diagram) to form an electrical connection between network layer 104 and ASIC layer 102.

[0048] Although not shown, the ASIC layer 102, including the active surface 112 and the second surface 113, may include conductive structures configured to connect components (processors 220A-220C, GPU 230, etc.) in the ASIC layer 102 to network layers 104, other components in the ASIC layer 102, and / or network interfaces (e.g., 221A-221C, 231, etc.) corresponding to the terminal 303. Such conductive structures may include traces extending in the horizontal direction D1 along the lower surface 301 and upper surface 311 of the second surface and the active surface 112, respectively. The traces may also extend along the lower and upper surfaces 301, 311 in a direction perpendicular to D1, such as... Figure 2 The direction D3 is illustrated in the diagram. In some cases, the trace can be contained within the ASIC layer 102. In some examples, components in the ASIC layer 102 can be directly connected to the terminal 303 and / or other components without using a network interface.

[0049] The conductive structure may also include conductive interconnects such as vias 162 (e.g., through-silicon vias (TSVs), through-oxide vias (TOVs), or through-glass vias (TGVs)) extending in the longitudinal direction D2 between the active surface 112 and the second surface 113, as shown below. Figure 3 As further illustrated. In some cases, conductive interconnects may extend in the horizontal direction D1 and / or vertical direction D2 within or above the substrate 202. The conductive interconnects and vias 162 may terminate at contacts or terminals, such as terminals 303 and contacts 313. Although Figure 3 The via 162 is illustrated, stopping at the base of the active surface 112 and the second surface 113. That is, the via does not extend to the upper surface 311 or the lower surface 301, but the via 162 may extend through and / or beyond the active surface 112 and / or the second surface 113 to facilitate connection with the upper network layer 104 or the lower interconnect structure.

[0050] Figure 4 A top view of network layer 104 is shown, with active surface 122 removed for clarity. Network layer 104 includes network components mounted on or otherwise located on network layer 104. Network components may include routers, such as routers 410-416, illustrated as circles, and routing traces, such as routing trace 420, illustrated as lines. As discussed herein, routers 410-416 and routing trace 420 may be connected to memory in memory layer 106 via electrical interconnects formed by contacts, terminals, and other conductive structures. Routers may also be connected to components in ASIC layer 102 via network interfaces 221A-221C, 231, 261, 271, and 281. Although Figure 4 Sixteen routers are shown, but any number of routers can be present in network layer 104. Other components may also be included in network layer 104 as needed, which may include active or passive components, including capacitor layers, clock structures (e.g., a tree or part of a tree clock structure), memory, and / or analog circuitry.

[0051] Network layer 104 may be made of one or more semiconductor materials, conductive materials, or other materials described herein with respect to substrate 202. In some cases, more than one network layer 104 may be included on the SoC. By providing additional network layers 104, greater obstructions, such as those resulting from stacking multiple layers (such as device layers and memory layers) to form higher stacks, can be bypassed, as described herein.

[0052] As mentioned in this paper, the ability to efficiently route communication subsystems at device layers (such as ASIC layers) can be hampered by space constraints and congestion caused by large components (such as dies) on the ASIC layer. Such constraints and congestion can lead to inefficient network routing, thereby reducing the speed of data communication between components and, in some cases, causing processing bottlenecks. In some cases where multiple device layers are vertically stacked in a three-dimensional (3D) package structure, large components in a device layer may constrain routing options between different components in nearby device layers, such as by projecting onto other device layers and / or network layers.

[0053] By utilizing additional network layers located above, below, and / or adjacent to the device layer, routing options can be effectively increased and enhanced. These additional network layers can serve as signal relay paths / buses / checkpoints to redirect or switch signals laterally or vertically from a first component to a destination second component via efficient computational algorithms from the network layers. Each network layer can execute computational algorithms independently or collectively to determine the most efficient data communication path and / or operation between different components. Therefore, more efficient routing of the communication subsystem can be achieved because the routing of the communication subsystem is not hindered or otherwise limited by the location or size of components on the device layer. As a result, the distance data travels during communication can be reduced, and the routing of data to its destination can be more direct.

[0054] Figure 5 A cross-sectional side view depicts a portion of the interconnect structure of a multilayer SoC 501 with a three-dimensional (3D) package structure. SoC 501 includes a first device layer 502a, a second device layer 502b, a first network layer 504a, a second network layer 504b, and a memory layer 506. The second device layer 502b is located between the first network layer 504a and the second network layer 504b. The first device layer 502a and the second device layer 502b may be ASIC layers similar to the ASIC layer 102 described herein. For example, the first device layer 502a and the second device layer 502b may each include vias 565a and 565b. In some examples, the first device layer and / or the second device layer 502b may be any other device layer, such as a memory layer or a network layer. Although in Figure 5 Only two network layers 504a and 504b and three device layers 502a, 502b, and 506 are shown in the diagram; however, it should be noted that any number of network and device layers can exist. For example, a SoC may include three network layers, three ASIC layers, and one memory layer. In another example, a SoC may include a single ASIC layer and numerous network and memory layers. In any configuration, network layers can be configured to connect device layers together.

[0055] Network layers 504a and 504b can be configured to provide electrical interconnects between the network layers and their respective interface layers (e.g., device layers 502a and 502b and memory layer 506 in SoC 501). For example, active surfaces 542a and 542b of network layers 504a and 504b can include contacts 515a and 515b, respectively. Second surfaces 541a and 541b of network layers 504a and 504b can include contacts 544a and 544b, respectively. These contacts (e.g., contacts 515a, 515b, 544a, and 544b) can be aligned with contacts on adjacent device layers. For example, contact 544a on the second surface 541a of network layer 504a can be connected to contact 513a on the active surface 511a of ASIC layer 502a. Contacts 544b on the second surface 541b of network layer 504b can be connected to contacts 513b on the active surface 511b of ASIC layer 502b. Contacts 515a on the active surface 542a of network layer 504a can be connected to contacts 517b on the second surface 545b of ASIC layer 502b. Contacts 517a on the second surface 545a of ASIC layer 502a can be connected to other electrical components. In some cases, hundreds of thousands of electrical connections can be formed between contacts on network layers 504a, 504b and device layers 502a, 502b and 506.

[0056] Network layers 504a and 504b may include network components such as those described with respect to network layer 104. In this regard, network layers 504a and 504b may include routers and other conductive structures configured to connect components within the device layer or otherwise route data between different device layers and network layers. The conductive structures may be the same as those described herein with respect to ASIC layer 102, such as traces, interconnects, and vias, including... Figure 5 The vias 564a and 564b are shown. In operation, network layers 504a and 504b can take packaged data from components on a device layer and route the data to one or more receiving components on the same or different device layers, where the data is unpacked and delivered to the receiving components.

[0057] Memory layer 506 can be similar to memory layer 106 described herein. For example... Figure 5 As shown, memory layer 506 is disposed on second network layer 504b. Contacts 555 on the active surface 556 of memory layer 506 can be arranged such that they are aligned with and connected to contacts 515b on the active surface 542b of network layer 506. The contacts on network layer 504b and memory layer 506 can form millions of electrical connections.

[0058] Memory layers such as memory layers 106 and 506 can include one or more memory segments. For example, and as... Figure 6 As shown, memory layer 506 includes 25 memory segments, including memory segments 601-605, but any number of memory segments is possible. Memory segments can be NAND memory or other such volatile and non-volatile memories, including MRAM, NRAM, FE-RAM, etc.

[0059] Fabricating memory segments can include creating memory wafers and dicing them into memory segments of selected sizes. In this regard, each memory wafer can have the same design to allow for the reusability of memory segments across different SoC designs. For example, memory wafers can be created in defined increments, such as 1x1 mm, 2x2 mm, 4x4 mm, etc. The memory wafers can then be diced or otherwise divided into memory segments sized to fit the SoC in which they are used. For example, the die size of SoC 101, i.e., the size of ASIC layer 102, could be 10x10 mm. To form memory layer 106, four memory wafers with a size of 5x5 mm can be diced into 1x1 mm segments, resulting in 100 1x1 mm memory segments. These 100 memory segments can then be arranged in memory layer 106 such that memory layer 106 has the same size as the die (10x10 mm). Although the memory segment is described as 1x1 mm in the foregoing example, the memory segment can be of any size. For example, a 20x20 mm die can have a corresponding memory layer consisting of a 10x10 array of 2x2 mm memory segments, or a 10x20 mm die can have a corresponding memory layer consisting of a 5x10 array of 2x2 mm memory segments. In some cases, multiple memory segments can be formed on the same wafer. For example, a 10x10 mm memory array can consist of a 10x10 mm memory wafer with two 5x10 mm memory segments. In other words, instead of dicing the wafer, memory segments can be formed directly on the wafer.

[0060] Memory layers, such as memory layers 106 and 506, can be the same size as or different from other device layers, such as ASIC layers and network layers. In some cases, the dimensions of a memory layer, such as its width and length, can be matched to multiples of the memory dimensions so that the interconnects of the memory layer overlap with other device layers. In another embodiment, die-to-wafer assembly can be used. In this embodiment, the memory layer may not match device layers such as ASIC layers or network layers, but the network layer may match either the memory layer or the ASIC layer.

[0061] The layers of the SoCs described in this article, such as SoC 101 and 501, can be bonded in a stacked arrangement using various bonding techniques, including direct dielectric bonding, non-adhesive bonding, and other techniques. Direct bonding technology or Hybrid bonding technologies, both of which are available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), a subsidiary of Xperi (see, for example, U.S. Patent Nos. 6,864,585 and 7,485,968, the entire contents of which are incorporated herein by reference). Figure 5 These bonding techniques enable contacts on the device layer to be bonded to contacts in the network layer. For example, a contact 513a on the active surface 511a of the first device / ASIC layer 502a can be bonded to a contact 544a on the second surface 541a of the first network layer 504a. Similarly, this process enables a contact 515a on the active surface 542a of the first network layer 504a to be bonded to a contact 517b on the active surface 545b of the second device layer 502b. Contacts 555 on the active surface 556 of the memory layer 506 can be bonded to contacts 515b on the active surface 542b of the network layer using the same bonding techniques. The contacts can have extremely fine pitch. For example, the contact pitch can be as low as approximately 1 μm to 10 μm, or in some cases, as low as approximately 100 nm or greater than 10 μm.

[0062] exist Figure 5 In the illustrated embodiment, device layers 502a, 502b, and 506 are each connected to at least one of network layers 504a and 504b to create data communication paths between layers. For example, ASIC layer 502a is connected to memory layer 506 via various connections between network layers 504a and 504b and between ASIC devices 502b.

[0063] As described, components can be formed on the device layer. For example, ASIC layer 502a includes components 512, 514, and 516, while ASIC layer 502b includes components 522, 524, and 526, as... Figure 5 As shown. Note that, Figure 5 The components shown can be used with Figure 2The components 220A-220C, 230, 260, 270, and 280 depicted are identical or similar. The components of memory layer 506, including components 532, 534, and 536, may include components such as NAND memory or other types of volatile and non-volatile memory (including MRAM, NRAM, FE-RAM, etc.). Alternatively, components 512, 514, 516, 522, 524, 526, 532, 534, and 536 may be any suitable electronic component designated to perform certain functions as needed. Although only three components are shown in each active surface of ASIC layers 502a and 502b and in active surface 556 of memory layer 506, it should be noted that each device layer may have any number of components, and these components may be placed anywhere and / or on any surface.

[0064] Figure 7 Another embodiment of a stacked SoC 700 is depicted, comprising six device layers 702a, 702b, 702c, 702d, 702e, and 706, and four network layers 704a, 704b, 704c, and 704d. Device layer 706 may be analogous to memory layers 106 and 506, and device layers 702a-e may be analogous to ASIC layers 102, 502a, and 502b. Network layers 704a-d may be compared to network layers 104, 504a, and 504b and may facilitate data communication between device layers. Each network layer is located between corresponding device layer pairs. For example, and as... Figure 7 As further shown, network layer 704a is located between device layers 702a and 702b, network layer 704b is located between device layers 702b and 702c, network layer 704c is located between device layers 702d and 702e, and network layer 704d is located between device layers 702e and 706. Note that, for clarity, conductive structures such as contacts, terminals, vias, etc., are not shown. Similarly, for clarity and ease of description, the active and second surfaces formed in the network layers and device layers are not shown. Figure 7 As shown in the image.

[0065] In some cases, device layers can be bonded face-to-face, with network layers not situated between them. In this regard, and as... Figure 7 As further shown, a direct bonding process (e.g., face-to-face) is used between device layers 702c and 702d at the bonding interface 728, thereby eliminating the need for a network layer between the device layers. In this respect, communication between device layers 702c and 702d can occur between the connections at the bonding interface 728.

[0066] Device layers 702a-702e and 706 may include components. For example, device layer 702a includes components 732 and 734, device layer 702b includes components 736 and 738, device layer 702c includes components 740, 742, and 744, device layer 702d includes components 746, 748, and 750, and device layer 70e includes component 730. For clarity, not all components are shown. Figure 7 The components shown can be used with Figure 2 The components 220A-220C, 230, 260, 270, 280, and others depicted in the text are... Figure 5 The components 532, 534 and 536 depicted are the same or similar.

[0067] like Figure 7 As further shown, the location of a component within a device layer can constrain communication routing options between the component and / or different layers. For example, as illustrated by dashed line 754, a direct communication path between component 732 in device layer 702a and component 730 in device layer 702e may be blocked by component 736 in device layer 702b.

[0068] By utilizing multiple network layers, efficient communication routing can be used to circumvent congestion caused by components. In this regard, network layers can serve as electrical communication pathways capable of determining and providing efficient communication paths between components that can be positioned vertically and / or laterally. Each network layer can be programmed with computational algorithms or other such logic to determine the most efficient communication path between components located laterally or vertically on different device layers. Each network layer 704a-704d can independently execute computational algorithms or logic to determine the most efficient data communication path and / or operation between different components. For example, when electrical communication is requested between component 732 in device layer 704a and component 730 in device layer 702e, the efficient communication route illustrated by solid line 752 can be determined by network layers 704a, 704b, and 704c. In this regard, network layer 704a can determine that the most efficient path to route data from component 732 in device layer 702a to network layer 704b is between components 736 and 738. Network layer 704b can then determine that the most efficient path to network layer 704c is between components 742 and 744 in device layer 702c and components 748 and 750 in device layer 702d, which is the opposite of traversing around components 744 and 750, as shown by dashed line 753. Network layer 704c can then pass data to component 730 in device layer 702e. In some examples, network layers can collectively perform computational algorithms or logic as needed.

[0069] In one example, a network layer may include at least one lookup table (LUT) or other such storage area capable of providing a lookup mechanism. The lookup mechanism can utilize information from the lookup table to store, retrieve, and route data across multiple additional network layers or device layers. The lookup table may be a circuit that can be programmed to generate output signals in response to input signals to perform logical functions. Note that the functionality, logic, or program within a network layer can be design-dependent so that each network layer can meet different electrical performance and requirements as needed.

[0070] Furthermore, the network layer can be programmed to provide information about the layout (such as physical location) of components formed in each device layer, network layer, and / or memory layer. This information helps the network layer make routing decisions more efficiently and accurately. Therefore, the network layer can know the physical and relative locations of components, such as large functional blocks located in device or memory layers, for efficient routing and electrical communication routing decisions. The layout and relative physical relationships of component blocks can be instantiated into Library Exchange Format (LEF) and / or Design Exchange Format (DEF) according to manufacturing needs.

[0071] In some cases, network layers can have a master / slave relationship. In this regard, one or more network layers can be the master layer that makes and provides routing decisions on behalf of other network layers (called subordinate network layers).

[0072] By utilizing multiple network layers (such as network layers 704a-d), the impact of large congestion caused by components can be reduced by routing data in an efficient manner, bypassing congestion. As a result, more flexible electrical communication subsystems and wiring options are available, providing adjustable or programmable electrical communication paths between components while minimizing the impact of potential congestion from components at the device layer.

[0073] Figure 8A Another example depicting a stacked SoC 800, similar to... Figure 7 The interconnect 700 is depicted, but fillers 802 and 804 are disposed within device layers 706 and 702d. Fillers can be utilized when using die-to-wafer bonding technology. For example, when instead of selecting an entire wafer, substrate, or device layer, a die is selected to be individually bonded to a specific component within the device layer, the total area of ​​the die may be smaller than the area of ​​the device layer to which the die is bonded. Therefore, fillers (such as insulating materials) can be used to fill empty gaps, recesses, or spaces between adjacent bonded dies.

[0074] For example, such as Figure 8AAs shown, filler 802 separates dies 756 and 766 in device layer 706, and filler 804 separates dies 725 and 762 in device layer 702d. In the embodiment depicted in FIG8, fillers 802 and 804 can be disposed between the bonded dies (e.g., 756 and 776, and 752 and 762) without impeding the capability of network layers (such as 704c and 704d).

[0075] In some examples, the filler can be extended into network layers, thereby creating separate networks on a single network layer. For example, such as... Figure 8B As shown in the stacked SoC 801, filler 806 extends from device layer 702d to network layer 704c, thereby splitting network layer 704c into two parts. Similarly, filler 808 extends from device layer 706 through network layer 704d, thereby splitting network layer 704d into two discrete networks.

[0076] Figure 9A The interconnection between components of network layer 904 and components of the ASIC layer is shown. In this regard, routers 910-913 are connected via routing trace 920 on network layer 904. Although Figure 9A The diagram illustrates the components of a network configured in a mesh topology, but networks can be configured in any topology, such as ring topology, startup topology, etc.

[0077] The ASIC layer includes multiple processors, including processors 940 and 942, which respectively include network interfaces 941 and 943. Components of the ASIC layer are connected to the network layer via conductive structures, including conductive structures 930 and 933 that connect network interfaces 941 and 943 to routers 910 and 913, respectively. Although Figure 9A The conductive structure is illustrated as a single line, but the conductive structure can include any combination of terminals, contacts, vias, conductive interconnects, etc., as described herein. Furthermore, although... Figure 9A Only the processor in the ASIC layer is shown, but other components such as GPUs and DSPs may exist in the ASIC layer.

[0078] Figure 9B This diagram illustrates a portion of an interconnect with more than one network layer (including network layer 904 and network layer 906), connecting components from more than one ASIC layer. Similar to... Figure 9AIn the configuration described, routers 910-913 from the first network layer 904 are connected via routing trace 920. Routers 955 and 956 from the second network layer 906 are connected via routing trace 957. Data can be sent from processor 940 in the first ASIC layer to processor 960 in the third ASIC layer via network layers 904 and 906 and the intermediate ASIC layer, as shown in bold. In this regard, data can be sent from processor 940 to network layer 904 via network interface 940 and conductive structure 930. Data can travel through routers 910-913 via routing trace 920. Router 913 can then direct the data to processor 950 via conductive trace 951. Processor 950 can pass the data to network layer 906 via network interface 954. Data can then travel from router 955 to router 956 via routing trace 957. Then router 956 can transmit data to network interface 964 of processor 960 via conductive structure 961.

[0079] Notice, Figure 10B The number of components in the ASIC and network layers depicted is for illustrative purposes only. Any number of components in the ASIC and network layers can be used as needed.

[0080] Figure 10A The ASIC layer 1002 is shown (similar to...) Figure 1 The ASIC layer 102 and memory layer 1006 (similar to those depicted in the text) Figure 1 The memory layer 106 depicted in the diagram passes through the network layer 1004 (similar to...). Figure 1 The interconnection of network layer 1004 (as depicted in the diagram). In this regard, processors or other components on the ASIC layer, including processors 1042 and 1044, are connected to network layer 1004 via conductive structure 1030. Network components on network layer 1004 are connected via conductive structure 1032 to memory segments such as memory segments 1050-1054 in memory layer 1006. For clarity, network components including routers and routing traces are not shown in network layer 1004. It should be understood that each component in ASIC layer 1002 is connected to one or more routers in network layer 1004. For clarity, Figure 10A Only components on the ASIC layer and a subset of memory segments on the memory layer are marked.

[0081] To read and write data to memory segments in memory layer 1006, a processor such as processor 1042 or another component in ASIC layer 1002 can pass data and / or instructions to network layer 1004 via conductive structure 1030. Data can be packaged by the network interface before being transmitted to the network layer. A router can direct data and / or instructions to the appropriate memory segment on memory layer 1006, such as memory segment 1050. Data can be unpacked upon arrival at memory segment 1050. Assuming memory layer 1006 is adjacent to components in ASIC layer 1002, memory segments, such as memory segments 1050-1052 in memory layer 1006, can effectively operate as L2 cache memory.

[0082] In some scenarios, a router can direct data and / or instructions to memory located outside the SoC package. For example, and as... Figure 10A As further shown, the L3 memory 1080 can be connected to the network layer 1004 via one or more conductive structures (such as conductive structure 1034). In operation, the processor or other components of the ASIC layer 1002 can pass instructions and / or data to the network layer 1004. Data and / or instructions can be routed through the network layer to conductive structure 1034 via one or more routers. Data and / or instructions are then passed to the L3 memory 1080 via conductive structure 1034. Routers can also route data and / or instructions to other devices located outside the SoC package, such as other processors, via one or more conductive structures. Additional network layers can be further formed on the memory layer 1006 and similarly constructed to facilitate further vertical communication within the device layers formed in the SoC. In some cases, the network layer can be configured to ignore faulty or otherwise inoperable memory segments as needed.

[0083] Figure 10B The diagram illustrates an interconnect with two network layers 1004 and 1005. In this configuration, data from a first device layer (not shown) can be transferred to a memory layer 1006. Network layer 1005, located between the first device layer and the ASIC layer 1002, can receive data and forward it to the ASIC layer 1002 via conductive structure 1015. The data can then be passed to network layer 1004 via conductive structure 1030, and network layer 1004 can then guide the data to memory layer 1006 via conductive structure 1032.

[0084] In some cases, the network layer can be configured to ignore faulty or otherwise malfunctioning memory segments. For example, such as... Figure 11As illustrated, memory segment 1150 on memory layer 1106 may be faulty. Consequently, network layer 1104 can ignore this memory segment by not routing any data to memory segment 1150 via conductive structure 1133. Faulty memory segments can be identified by performing known memory tests during SoC or memory production, allowing e-fuse to set bad sectors. In some cases, faulty memory segments can be detected during SoC operation (downtime) or startup. In this regard, a basic MBIST (Memory Built-in Self-Test) can evaluate sectors in each memory segment to determine which segments, or sectors within segments, are fully operational and which are not. Conversely, the same approach can be applied to multiprocessor approaches where network layers can ignore and bypass faulty processors or processing elements routed on ASIC layers or other layers.

[0085] Although the aforementioned layers are identified as having different components and features, such as a memory layer with memory, a network layer with network components, and an ASIC layer including computing components, each layer may include components associated with another layer. For example, a memory layer may include network components and / or computing components, a network layer may include memory and / or computing components, and an ASIC layer may include network components and / or memory.

Claims

1. A network configured to route electrical communications laterally and vertically between components of a stacked device layer of a 3D System-on-a-Chip (SoC), the network comprising: A first network layer is disposed between a first device layer and a second device layer, wherein the first device layer includes one or more first components and the second device layer includes one or more second components; A third device layer is directly bonded to the second device layer, the third device layer including one or more third components, the one or more third components being in direct electrical communication with the one or more second components; A second network layer is disposed between the third and fourth device layers, the fourth device layer including one or more fourth components, wherein the first and second network layers are configured to route data between at least one first component of the first components and one or more fourth components of the fourth components via at least two routers of the first network layer, the at least two routers including a first router and a second router, the first router being configured to route the data from the first device layer to the second router and the second router being configured to route the data to the second device layer.

2. The network of claim 1, wherein the second device layer and the third device layer each include one or more vertical structures, the one or more vertical structures together with the first network and the second network providing one or more electrical communication paths between the at least one first component and the at least one fourth component.

3. The network of claim 1, wherein the one or more second components and the one or more third components are directly electrically connected via a hybrid junction formed between the second device layer and the third device layer.

4. The network according to claim 1, wherein: The first network layer is directly bonded to each of the first device layer and the second device layer; as well as The second network layer is directly bonded to each of the third and fourth device layers.

5. The network according to claim 2, wherein: The shortest physical distance between at least one first component and one or more fourth components is blocked by a second or third component; as well as The first network, the second network, or the first network and the second network are configured to determine an electrical communication path between the at least one first component and the at least one fourth component.

6. The network of claim 5, wherein the electrical communication path is determined based on the relative physical location of one or more components of each of the first device layer, the second device layer, the third device layer, and the fourth device layer.

7. The network of claim 6, wherein the relative physical location is stored in a lookup table of the first network layer or the second network layer.

8. The network of claim 5, wherein each of the first network layer and the second network layer is configured to independently determine a corresponding portion of the electrical communication path.

9. The network of claim 8, wherein the first network layer and the second network layer are configured to jointly determine the electrical communication path.

10. The network of claim 1, wherein the first network layer and the second network layer are configured in a master / slave relationship.

11. The network of claim 1, wherein each of the one or more components of the corresponding first device layer and the fourth device layer includes a network interface configured to pack and unpack data for communication via an electrical communication path.

12. The network of claim 1, further comprising a third network layer disposed between the fourth device layer and the fifth device layer, the fifth device layer comprising one or more memory components.

13. The network of claim 1, wherein the first network layer is directly bonded to the active surface of the first device layer.

14. The network of claim 1, wherein one or more routers in the first network layer communicate with the one or more first components via interconnects formed between the first network layer and the first device layer by hybrid bonding.

15. The network of claim 12, wherein one or more routers in the third network layer communicate with the one or more memory components via interconnects formed between the third network layer and the fifth device layer by hybrid bonding.

16. The network of claim 15, wherein the interconnects have a pitch between 1 micrometer and 10 micrometers.

17. The network of claim 1, wherein one of the device layers comprises at least two monolithic dies arranged side by side, and an insulating material disposed in the space between the at least two monolithic dies.

18. The network of claim 17, wherein the at least two monolithic dies are directly bonded to at least one network layer in the network layer, the at least one network layer comprising two separate portions, and the insulating material extends longitudinally from between the at least two monolithic dies into the space between the two separate portions.

19. The network of claim 1, wherein the data routed between the first component and the fourth component is routed between the first network layer and the second network layer via a second component or a third component.

20. The network of claim 19, wherein the electrical communication includes data, and the second component or the third component transmits the data to the first network layer or the second network layer via a routing interface.

21. A network configured to route electrical communications laterally and vertically between components of a stacked device layer of a 3D System-on-a-Chip (SoC), said network comprising: A first network layer is disposed between a first device layer and a second device layer, wherein the first device layer includes a first component and the second device layer includes a second component; as well as A second network layer is disposed between the second device layer and the third device layer, the third device layer including a third component, wherein the first network layer and the second network layer are configured to route data between the first component and the third component via the network interface of the second component and through at least two routers of the first network layer, the at least two routers including a first router and a second router, the first router being configured to direct the data from the first device layer to the second router and the second router being configured to direct the data to the network interface of the second component of the second device layer.

22. A system-on-a-chip (SoC), comprising: Multiple network layers, including a first network layer and a second network layer, each network layer including one or more routers; as well as A first device layer includes one or more components, the first device layer having an active surface and an opposing second surface, the active surface being bonded to a second network layer, and the opposing second surface being bonded to the first network layer. At least the first and second components of the one or more components each include a network interface, wherein the network interfaces of the first and second components are connected to the first and second network layers via conductive structures. The first network layer and the second network layer are configured to route data from the first component to the second component via interconnects formed by hybrid bonding of corresponding device layers and network layers. The first network layer includes at least two routers, including a first router and a second router. The first router is configured to route the data from the network interface of the first component to the second router, and the second router is configured to route the data to the network interface of the second component.

23. A method for forming a 3D system-on-a-chip (SoC), the 3D SoC comprising: A first device layer and a first network layer and a second network layer coupled to opposite sides of the first device layer, the first device layer including one or more components, each of said one or more components including a network interface, and the first network layer and the second network layer each including one or more routers, said one or more routers being configured to route data between the one or more components via said network interface, the method including: The first network layer and the second network layer are bonded to the first device layer. The first network layer includes at least two routers, including a first router and a second router. The first router is configured to route the data from the network interface of a first component of the first device layer to the second router, and the second router is configured to route the data to the network interface of a second component of the first device layer.

24. The method of claim 23, wherein the first network layer and the second network layer are configured to route data to or from the one or more components on the first device layer.

25. The method of claim 23, wherein the first network layer is configured to control the operation of the second network layer.

26. The method of claim 23, wherein the first network layer and the second network layer are configured to operate independently.

27. The method according to claim 23, wherein: At least the first and second components of the one or more components each include a network interface; The network interfaces of the first component and the second component are connected to the first network layer and the second network layer via conductive structures; as well as The first network layer and the second network layer are configured to route data from the first component to the second component.

28. The method of claim 23, wherein bonding the first network layer and the second network layer to the device layer comprises hybrid bonding.

29. The method of claim 23, further comprising bonding the second device layer to the second network layer.

30. The method of claim 29, further comprising bonding a third device layer to the first network layer.

31. A method for forming a 3D system-on-a-chip (SoC), the SoC including a plurality of vertically stacked device layers and a network configured to route data between components of the plurality of device layers, wherein the network includes a first network layer and a second network layer, the method comprising: (a) Bonding the first device layer and the second device layer to opposite sides of the first network layer; (b) Before, after, or simultaneously with (a), the second and third device layers are joined to opposite sides of the second network layer, wherein the first and second network layers are configured to cooperatively route data between the first, second, and / or third device layers. The first network layer and the second network layer are configured to route the data between the first component of the first device layer and the third component of the third device layer via the network interface of the second component of the second device layer and through at least two routers of the first network layer. The at least two routers include a first router and a second router. The first router is configured to route the data from the first device layer to the second router, and the second router is configured to direct the data to the network interface of the second component of the second device layer.

32. The method of claim 31, wherein (a) and (b) each comprise forming a hybrid bonding between the respective device layer and network layer.

33. The method of claim 31, wherein the second device layer includes one or more paths for transmitting the data between the first network layer and the second network layer.

34. The method of claim 31, wherein the first device layer comprises a first group of one or more components, the second device layer comprises a second group of one or more components, and the third device layer comprises a third group of one or more components.

35. The method of claim 34, wherein each component in the first group of one or more components, the second group of one or more components, and the third group of one or more components includes a network interface.

36. A method of forming a network configured to route electrical communications laterally and vertically between components of a stacked device layer of a 3D system-on-a-chip (SOC), wherein the network includes a first network layer disposed between a first device layer and a second device layer, a third device layer bonded to the second device layer, and a second network layer disposed between the third device layer and a fourth device layer, the method comprising: The first device layer and the second device layer are directly bonded to the first network layer; The third device layer is directly bonded to the second device layer; as well as The third device layer and the fourth device layer are directly bonded to the second network layer, wherein: The first device layer includes one or more first components; The fourth device layer includes one or more fourth components; The first network layer and the second network layer are configured to route data between at least one first component in the first component and one or more fourth components in the fourth component via at least two routers of the first network layer, the at least two routers including a first router and a second router, the first router being configured to route the data from the first device layer to the second router and the second router being configured to direct the data to the second device layer.

37. The method of claim 36, wherein: The second device layer includes one or more second components. The third device layer includes one or more third components, and The third component communicates directly with the one or more second components.

38. The method of claim 36, wherein the second device layer and the third device layer each include one or more vertical structures, the one or more vertical structures together with the first network and the second network providing one or more electrical communication paths between the at least one first component and the at least one fourth component.

39. The method of claim 38, wherein: The shortest physical distance between at least one first component and one or more fourth components is blocked by a second or third component; as well as The first network, the second network, or the first network and the second network are configured to determine an electrical communication path between the at least one first component and the at least one fourth component.

40. The method of claim 39, wherein the electrical communication path is determined based on the relative physical location of one or more components of each of the first device layer, the second device layer, the third device layer, and the fourth device layer.

41. The method of claim 40, wherein the relative physical location is stored in a lookup table of the first network layer or the second network layer.

42. The method of claim 39, wherein each of the first network layer and the second network layer is configured to independently determine a corresponding portion of the electrical communication path.

43. The method of claim 39, wherein the first network layer and the second network layer are configured to jointly determine the electrical communication path.

44. The method of claim 36, wherein the first network layer and the second network layer are configured in a master / slave relationship.

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