Electronic assemblies and methods of making the same

Abstract

This disclosure provides an electronic component and a method for manufacturing the same, wherein the electronic component includes: an insulating layer; and a first metal bump disposed on the insulating layer and includes: a first metal layer disposed on the insulating layer; and a second metal layer disposed on the first metal layer, wherein, in a cross-sectional view, the first metal layer has a first width, the second metal layer has a second width, and the first width is smaller than the second width.

Description

Technical Field

[0001] This disclosure relates to an electronic component and a method for manufacturing the same, and more particularly to an electronic component and a method for manufacturing the same that facilitates electrical testing. Background Technology

[0002] With technological advancements and in response to consumer demands, modern electronic products are increasingly moving towards high integration, meaning a single electronic device can possess multiple functions. More functions in an electronic product necessitate a greater number of chips, posing a challenge to circuit I / O design. This can generally be addressed by using composite layers or additive layer structures, such as redistribution layers, to modify the original circuit I / O design or increase the spacing or number of I / O pins to meet these requirements.

[0003] However, electrical testing is required for each layer of the fabric to facilitate subsequent processes. Therefore, there is an urgent need to provide an electronic component and its fabrication method to facilitate electrical testing or mitigate damage to the electronic component caused by electrical testing. Summary of the Invention

[0004] This disclosure provides an electronic component comprising: an insulating layer; and a first metal bump disposed on the insulating layer and comprising: a first metal layer disposed on the insulating layer; and a second metal layer disposed on the first metal layer, wherein, in a cross-sectional view, the first metal layer has a first width, the second metal layer has a second width, and the first width is smaller than the second width.

[0005] According to an embodiment of this disclosure, the ratio of the first width to the second width is less than or equal to 0.95.

[0006] According to an embodiment of the present disclosure, the first metal bump further includes a third metal layer disposed on the second metal layer, the third metal layer having a third width, and the first width being smaller than the third width.

[0007] According to an embodiment of the present disclosure, in the cross-sectional view, the first metal layer has a first edge, and the first edge is located below the second metal layer.

[0008] According to an embodiment of the present disclosure, the first metal layer includes a first sub-metal layer and a second sub-metal layer, the first sub-metal layer being disposed between the second sub-metal layer and the insulating layer, wherein the width of the first sub-metal layer is smaller than the width of the second sub-metal layer.

[0009] According to an embodiment of the present disclosure, the first metal layer has a first projection on the insulating layer, the second metal layer has a second projection on the insulating layer, and the area of ​​the first projection is smaller than the area of ​​the second projection.

[0010] According to an embodiment of this disclosure, a second metal bump is further included, which is disposed on the insulating layer and adjacent to the first metal bump; wherein, in the cross-sectional view, the first metal layer has a first edge and a second edge opposite to the first edge, the first edge and the second edge are located below the second metal layer, and the first edge is closer to the second metal bump than the second edge; the second metal layer has a third edge and a fourth edge opposite to the third edge, the third edge being closer to the second metal bump than the fourth edge; wherein the distance between the first edge and the third edge is greater than the distance between the second edge and the fourth edge. This disclosure also provides a method for fabricating an electronic component, comprising the following steps: providing an insulating layer, wherein the insulating layer includes a first region and a second region, and a first metal layer is sequentially disposed on the insulating layer on the first region and the second region of the insulating layer; disposing a second metal layer on the first metal layer and corresponding to the first region of the insulating layer; forming a mask on the first metal layer and corresponding to the second region of the insulating layer; removing a portion of the first metal layer disposed in the second region; removing the mask; and removing the first metal layer disposed in the second region to form an electronic component, wherein the electronic component includes: the insulating layer; and a first metal bump disposed on the insulating layer and including: the first metal layer disposed on the insulating layer; and the second metal layer disposed on the first metal layer; wherein, in a cross-sectional view of the electronic component, the first metal layer has a first width, the second metal layer has a second width, and the first width is smaller than the second width.

[0011] According to an embodiment of the present disclosure, the first metal bump further includes a third metal layer disposed on the second metal layer, wherein, in a cross-sectional view of the electronic component, the third metal layer has a third width, and the first width is smaller than the third width.

[0012] This disclosure also provides a method for fabricating an electronic component, comprising the following steps: providing an insulating layer, wherein the insulating layer includes a first region and a second region, and sequentially disposed on the insulating layer are: a first metal layer disposed on the first region of the insulating layer; and a second metal layer disposed on the first metal layer; forming a metal wire on the second region of the insulating layer, and the metal wire being electrically connected to the first metal layer; and removing the metal wire to form an electronic component, wherein the electronic component includes: the insulating layer; and a first metal bump disposed on the insulating layer and including: the first metal layer disposed on the insulating layer; and the second metal layer disposed on the first metal layer. Attached Figure Description

[0013] Figure 1A This is a cross-sectional view of an electronic component according to an embodiment of the present disclosure.

[0014] Figure 1B and Figure 1C for Figure 1A A magnified view of a portion of the image.

[0015] Figure 1D for Figure 1B A magnified view of a portion of the image.

[0016] Figure 2 This is a flowchart illustrating a method for fabricating an electronic component according to an embodiment of the present disclosure.

[0017] Figures 3A to 3F This is a cross-sectional view of a method for fabricating an electronic component according to an embodiment of the present disclosure.

[0018] Figure 4 This is a flowchart illustrating a method for fabricating an electronic component according to an embodiment of the present disclosure.

[0019] Figures 5A to 5D This is a cross-sectional view of a method for fabricating an electronic component according to an embodiment of the present disclosure.

[0020] Figure 6A and Figure 6B This is a cross-sectional view of a method for fabricating an electronic component according to an embodiment of the present disclosure.

[0021] Explanation of reference numerals in the attached figures

[0022] Detailed Implementation

[0023] The following are specific embodiments illustrating the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified and changed in various ways for different viewpoints and applications without departing from the spirit of this disclosure.

[0024] It should be noted that, unless otherwise specified herein, the term "a" component is not limited to having a single component, but may include one or more of the components. Furthermore, the use of ordinal numbers such as "first" and "second" in the specification and claims to modify components of a claim does not itself imply or represent any prior ordinal number for that claimed component, nor does it represent the order of one claimed component with another, or the order of manufacturing processes. The use of these ordinal numbers is solely for the purpose of clearly distinguishing one claimed component with a given name from another claimed component with the same name.

[0025] Throughout this disclosure and in the appended claims, certain terms are used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same component. This document is not intended to distinguish between components that have the same function but different names. In the following description and claims, words such as "comprising," "containing," and "having" are open-ended terms and should therefore be interpreted as "containing but not limited to...". Thus, when the terms "comprising," "containing," and / or "having" are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0026] In this text, the terms "about," "approximately," "substantially," and "roughly" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "about," "approximately," "substantially," or "roughly," the meaning of these terms is implied. Furthermore, the phrases "range from the first value to the second value" or "range between the first value and the second value" indicate that the range includes the first value, the second value, and other values ​​in between.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined herein.

[0028] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one component to another in the diagram. It is understood that if the device in the diagram is flipped upside down, the component depicted on the "below" side will become the component on the "above" side. When a corresponding component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Additionally, when a component is referred to as "on another component," there is a vertical relationship between them in the top view, and this component can be above or below the other component, depending on the orientation of the device.

[0029] In this disclosure, the thickness, length, and width can be measured using an optical microscope, and the thickness can be measured from a cross-sectional image in an electron microscope, but is not limited thereto. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of approximately 10% between the first and second values; if the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0030] It should be noted that the technical solutions provided in the different embodiments below can be substituted for, combined or mixed with each other to constitute another embodiment without violating the spirit of this disclosure.

[0031] Figure 1A This is a cross-sectional view of an electronic component according to an embodiment of the present disclosure. Figure 1B and Figure 1C for Figure 1A A magnified view of a portion of the image.

[0032] like Figure 1A and Figure 1B As shown, the electronic component disclosed herein is characterized by comprising: an insulating layer 2; and a first metal bump M1 disposed on the insulating layer 2 and comprising: a first metal layer 31 disposed on the insulating layer 2; and a second metal layer 32 disposed on the first metal layer 31, wherein, in a cross-sectional view, the first metal layer 31 has a first width W1, the second metal layer 32 has a second width W2, and the first width W1 is smaller than the second width W2.

[0033] In this disclosure, the material of the insulating layer 2 is not particularly limited, and may be, for example, an organic material, an inorganic material, or a combination thereof. Examples of suitable organic materials include polyimide (PI), photosensitive polyimide (PSPI), epoxy resin, polybenzoxazole (PBO), benzocyclobutene (ECB), photoresist, polymers, or combinations thereof, but this disclosure is not limited thereto. Examples of suitable inorganic materials include silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or combinations thereof, but this disclosure is not limited thereto.

[0034] In this disclosure, the materials of the first metal layer 31 and the second metal layer 32 are not particularly limited, and may be, for example, gold (Au), silver (Ag), copper (Cu), palladium (Pd), platinum (Pt), ruthenium (Ru), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), manganese (Mn), zinc (Zn), their alloys, or combinations thereof, but this disclosure is not limited thereto. Furthermore, the same or different materials may be used to prepare the first metal layer 31 and the second metal layer 32. In one embodiment of this disclosure, the first metal layer 31 may be a composite layer, more specifically, such as... Figure 1B As shown, the first metal layer 31 may include a first sub-metal layer 311 and a second sub-metal layer 312. The first sub-metal layer 311 is disposed between the second sub-metal layer 312 and the insulating layer 2. The first sub-metal layer 311 and the second sub-metal layer 312 may be made of different materials. In one embodiment of this disclosure, the first sub-metal layer 311 may contain titanium, and the second sub-metal layer 312 may contain copper. In another embodiment of this disclosure, the second metal layer may contain copper 32.

[0035] In this disclosure, the "first width" refers to the width of the bottom of the first metal layer 31 in the direction perpendicular to the normal direction Z of the insulating layer 2 in a cross-sectional view, i.e., the width of the first metal layer 31 in the Y direction. The "first width" can also refer to the width of the surface 31S of the first metal layer 31 in contact with the insulating layer 2 in the direction perpendicular to the normal direction Z of the insulating layer 2 in a cross-sectional view, i.e., the width of the surface 31S of the first metal layer 31 in contact with the insulating layer 2 in the Y direction. Alternatively, the "first width" can also refer to the distance between the two edges of the first metal layer 31. Similarly, in this disclosure, the "second width" refers to the width of the bottom of the second metal layer 32 in the direction perpendicular to the normal direction Z of the insulating layer 2 in a cross-sectional view, i.e., the width of the second metal layer 32 in the Y direction. The "second width" may also refer to the width of the surface 32S in contact with the first metal layer 31 in a cross-sectional view, in the direction perpendicular to the normal direction Z of the insulating layer 2, that is, the width of the surface 32S in contact with the first metal layer 31 in the Y direction. Alternatively, the "second width" may also refer to the distance between the two edges of the second metal layer 32. In one embodiment of this disclosure, the ratio of the first width W1 to the second width W2 is less than or equal to 0.95 (W1 / W2 ≤ 0.95).

[0036] In this disclosure, the first metal bump M1 further includes a third metal layer 33 disposed on the second metal layer 32. The third metal layer 33 has a third width W3, and the first width W1 is smaller than the third width W3. Here, the material of the third metal layer 33 is similar to that of the first metal layer 31 or the second metal layer 32, and will not be described in detail here. In one embodiment of this disclosure, the third metal layer 33 may be a composite layer, more specifically, such as... Figure 1B As shown, the third metal layer 33 may include a third sub-metal layer 331 and a fourth sub-metal layer 332. The third sub-metal layer 331 is disposed between the second metal layer 32 and the fourth sub-metal layer 332. The third sub-metal layer 331 and the fourth sub-metal layer 332 may be made of the same or different materials. In one embodiment of this disclosure, the third sub-metal layer 331 may contain nickel, and the fourth sub-metal layer 332 may contain gold, but this disclosure is not limited thereto. By using the arrangement method proposed in this disclosure, where the second width W2 of the second metal layer 32 is greater than the first width W1 of the first metal layer 31, or the third width W3 of the third metal layer 33 is greater than the first width W1 of the first metal layer 31, it indicates that the second metal layer 32 is effectively stacked on the first metal layer 31, or the third metal layer 33 is effectively stacked on the first metal layer 31, which can improve the electrical characteristics of electronic components, but is not limited thereto.

[0037] In this disclosure, such as Figure 1A As shown, the first metal layer 31 has a first projection T1 on the insulating layer 2, and the second metal layer 32 has a second projection T2 on the insulating layer 2. In the normal direction Z of the insulating layer 2, the first projection T1 and the second projection T2 overlap, and the area of ​​the first projection T1 is smaller than the area of ​​the second projection T2.

[0038] In addition, such as Figure 1B As shown in the cross-sectional view, the first metal layer 31 has a first edge E1 and a second edge E2 opposite to the first edge E1, and the first edge E1 and the second edge E2 are located below the second metal layer 32. More specifically, the first metal layer 31 has a first edge E1 and a second edge E2 opposite to the first edge E1, and the second metal layer 32 has a third edge E3 and a fourth edge E4 opposite to the third edge E3, wherein, in the normal direction Z of the insulating layer 2, the first edge E1 may not overlap with the third edge E3, and the second edge E2 may substantially overlap with the fourth edge E4. In one embodiment of this disclosure, the distance D1 between the first edge E1 and the third edge E3 may be greater than or equal to 0.1 micrometers (µm).

[0039] Figure 1C For another first metal bump M1' of this disclosure, wherein, Figure 1C and Figure 1B Similar, except for the following differences.

[0040] like Figure 1C As shown, the first metal layer 31 of another first metal bump M1' has a first edge E1 and a second edge E2 opposite to the first edge E1, and the second metal layer 32 has a third edge E3 and a fourth edge E4 opposite to the third edge E3. In the normal direction Z of the insulating layer 2, the first edge E1 may not overlap with the third edge E3, and the second edge E2 may not overlap with the fourth edge E4. In one embodiment of this disclosure, the distance D1 between the first edge E1 and the third edge E3 may be greater than or equal to 0.1µm, the distance D2 between the second edge E2 and the fourth edge E4 may be greater than or equal to 0µm, and the distance D1 between the first edge E1 and the third edge E3 and the distance D2 between the second edge E2 and the fourth edge E4 may be the same or different.

[0041] Figure 1D for Figure 1B Enlarged portion of the image, such as Figure 1D As shown, in this disclosure, the first metal layer 31 may include a first sub-metal layer 311 and a second sub-metal layer 312, and the width W11 of the first sub-metal layer 311 may be different from the width W12 of the second sub-metal layer 312. More specifically, in one embodiment of this disclosure, the width W11 of the first sub-metal layer 311 may be smaller than the width W12 of the second sub-metal layer 312. Therefore, the distance between at least one edge e11 of the first sub-metal layer 311 and the edge e12 of the second sub-metal layer 312 may be greater than 0. Furthermore, in one embodiment of this disclosure, the area of ​​the projection T11 of the first sub-metal layer 311 on the insulating layer 2 may be smaller than the area of ​​the projection T12 of the second sub-metal layer 312 on the insulating layer 2.

[0042] In this disclosure, such as Figure 1A As shown, the electronic component may further include a second metal bump M2, which is disposed on the insulating layer 2 and adjacent to the first metal bump M1. In the cross-sectional view, the first edge E1 and the second edge E2 of the first metal layer 31 are located below the second metal layer 32, with the first edge E1 being closer to the second metal bump M2 than the second edge E2, and the third edge E3 of the second metal layer 32 being closer to the second metal bump M2 than the fourth edge E4. The distance D1 between the first edge E1 and the third edge E3 is greater than the distance between the second edge E2 and the fourth edge E4. In this embodiment, as... Figure 1A As shown, the distance between the second edge E2 and the fourth edge E4 is approximately 0, but in other embodiments of this disclosure, such as Figure 1C As shown, the distance D2 between the second edge E2 and the fourth edge E4 may not be 0.

[0043] In this disclosure, the electronic component may further include a third metal bump M3 disposed below the first metal bump M1 and the second metal bump M2, that is, the insulating layer 2 is disposed between the first metal bump M1 or the second metal bump M2 and the third metal bump M3. The third metal bump M3 is electrically connected to both the first metal bump M1 and the second metal bump M2, therefore, the first metal bump M1 can be electrically connected to the second metal bump M2 through the third metal bump M3.

[0044] Furthermore, in this disclosure, the electronic component may also include a plurality of metal bumps, such as Figure 1A The illustration shows a fourth metal bump M4 and a fifth metal bump M5, but this disclosure is not limited thereto. The fourth metal bump M4 and the fifth metal bump M5 are disposed below the third metal bump M3, that is, the third metal bump M3 is disposed between the insulating layer 2 and the fourth metal bump M4 and the fifth metal bump M5, and the fourth metal bump M4 and the fifth metal bump M5 are electrically connected to the third metal bump M3. Furthermore, another insulating layer 21 may be included between the third metal bump M3 and the fourth metal bump M4 and the fifth metal bump M5, but this disclosure is not limited thereto.

[0045] Figure 2 This is a flowchart illustrating a method for fabricating an electronic component according to an embodiment of the present disclosure. Figures 3A to 3F This is a cross-sectional view of a method for fabricating an electronic component according to an embodiment of the present disclosure.

[0046] like Figure 3A As shown, a carrier substrate 10 is provided; and a release layer 11 is disposed on the carrier substrate 10. Next, an insulating layer 2 is provided on the carrier substrate 10, wherein the insulating layer 2 includes a first region R1 and a second region R2, and a first metal layer 31 is sequentially disposed on the insulating layer 2 on the first region R1 and the second region R2 of the insulating layer 2; and a second metal layer 32 is disposed on the first metal layer 31 and corresponds to the first region R1 of the insulating layer 2.

[0047] Here, the "first region" refers to the region where the insulating layer 2 and the second metal layer 32 overlap in the normal direction Z of the insulating layer 2. The "second region" refers to the region where the insulating layer 2 and the second metal layer 32 do not overlap in the normal direction Z of the insulating layer 2.

[0048] In one embodiment of this disclosure, before the step of providing the insulating layer 2 disposed on the carrier substrate 10, a third metal bump M3 may be provided and disposed on the carrier substrate 10, wherein the third metal bump M3 may be electrically connected to the first metal layer 31.

[0049] The material of the carrier substrate 10 is not particularly limited, and can be, for example, a quartz substrate, a glass substrate, a wafer, a sapphire substrate, a rigid-flex board, resin, epoxy resin, or other rigid substrates. Alternatively, the carrier substrate 10 can also be a flexible substrate or film, and its material may include polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), or other plastic materials, but this disclosure is not limited thereto. The release layer 11 can be an adhesive, epoxy resin, die attach film (DAF), or the like, but this disclosure is not limited thereto. The release layer 11 facilitates the subsequent removal of the carrier substrate 10. In one embodiment of this disclosure, the release layer 11 may be absent.

[0050] In this disclosure, there are no particular limitations on the method for forming the insulating layer 2. For example, dip coating, spin coating, roller coating, blade coating, spray coating, deposition, or combinations thereof can be used, but this disclosure is not limited thereto. There are no particular limitations on the method for forming the first metal layer 31 and the second metal layer 32. For example, sputtering, electroplating, chemical plating, chemical vapor deposition, or combinations thereof can be used, but this disclosure is not limited thereto. Furthermore, the first metal layer 31 and the second metal layer 32 can be prepared separately using the same or different methods.

[0051] like Figure 3A As shown, a third metal layer 33 may also be formed on the second metal layer 32, corresponding to the first region R1 of the insulating layer 2. Here, the third metal layer 33 can be prepared using materials or methods similar to those used for the first metal layer 31 or the second metal layer 32, which will not be described in detail here.

[0052] Next, as Figure 3B As shown, a mask 4 is formed on the first metal layer 31, and the mask 4 corresponds to the second region R2 of the insulating layer 2. Here, the patterned mask 4 can be formed on the first metal layer 31 by photolithography, inkjet lithography, or a combination thereof, so that the mask 4 is formed on the second region R2 of the corresponding insulating layer 2.

[0053] Then, as Figure 3C As shown, a portion of the first metal layer 31 disposed in the second region R2 is removed; more specifically, in the second region R2, the first metal layer 31 not covered by the mask 4 is removed. Next, the mask 4 is removed to form a patterned first metal layer 31, as shown. Figure 3D As shown. Here, a portion of the first metal layer 31 can be removed by etching, which includes wet etching, dry etching, or a combination thereof, but this disclosure is not limited thereto.

[0054] To ensure the proper electrical characteristics of electronic components, electrical testing is performed. Previously, testing was often conducted directly on metal bumps, which could damage the bumps and affect the performance or reliability of the electronic components. Therefore, in this disclosure, as... Figure 3E As shown, the first metal layer 31 disposed on the second region R2 of the insulating layer 2 can be used as a reference line. Electrical testing of the electronic component is performed using an electrical tester 5 through the reference line. This reduces damage to metal bumps (e.g., the first metal bump M1 and / or the second metal bump M2) during electrical testing, thereby improving the performance or reliability of the electronic component. Here, the electrical tester 5 includes a voltmeter, an ammeter, or a combination thereof, but this disclosure is not limited thereto.

[0055] Next, as Figure 3F As shown, the first metal layer 31 disposed in the second region R2 of the insulating layer 2 is removed to form the electronic component of this disclosure. The electronic component of this disclosure includes: an insulating layer 2; and a first metal bump M1 disposed on the insulating layer 2 and comprising: a first metal layer 31 disposed on the insulating layer 2; and a second metal layer 32 disposed on the first metal layer 31. Furthermore, in this disclosure, a second metal bump M2 may be disposed above the insulating layer 2, and the second metal bump M2 is disposed adjacent to the first metal bump M1. Here, a third metal bump M3 can be electrically connected to both the first metal bump M1 and the second metal bump M2. Therefore, the first metal bump M1 can be electrically connected to the second metal bump M2 through the third metal bump M3.

[0056] Furthermore, after the step of removing the first metal layer 31 disposed in the second region R2 of the insulating layer 2, the process may further include the step of removing the carrier substrate 10 and the release layer 11 to form as shown in the figure. Figure 1A The electronic component shown can be used in various electronic devices.

[0057] Here, the first metal layer 31 disposed in the second region R2 of the insulating layer 2 can be removed by etching, including wet etching, dry etching, or a combination thereof, but this disclosure is not limited thereto. Since the first metal layer 31 is etched multiple times, therefore, as Figure 1B or Figure 1C As shown in the cross-sectional view of the electronic component, the width of the first metal layer 31 is different from the width of the second metal layer 32. More specifically, the first metal layer 31 has a first width W1, the second metal layer 32 has a second width W2, and the first width W1 is smaller than the second width W2.

[0058] Furthermore, in this disclosure, electronic components may also be as follows: Figure 1DAs shown, the first metal layer 31 may include a first sub-metal layer 311 and a second sub-metal layer 312. The first sub-metal layer 311 is disposed between the second sub-metal layer 312 and the insulating layer 2. The width W11 of the first sub-metal layer 311 may be smaller than the width W12 of the second sub-metal layer 312. Furthermore, as... Figure 1B As shown in 1C, the first metal bump M1 or another first metal bump M1' may also include a third metal layer 33, disposed on the second metal layer 32, and corresponding to the first region R1 of the insulating layer 2, wherein the third metal layer 33 has a third width W3, and the first width W1 is smaller than the third width W3.

[0059] Figure 4 This is a flowchart illustrating a method for fabricating an electronic component according to an embodiment of the present disclosure. Figures 5A to 5D This is a cross-sectional view of a method for fabricating an electronic component according to an embodiment of the present disclosure.

[0060] like Figure 5A As shown, a carrier substrate 10 is provided; and a release layer 11 is disposed on the carrier substrate 10. Next, an insulating layer 2 is provided on the carrier substrate 10, wherein the insulating layer 2 includes a first region R1 and a second region R2, and a first metal layer 31 is disposed on the first region R1 of the insulating layer 2, and a second metal layer 32 is disposed on the first metal layer 31 in sequence above the insulating layer 2.

[0061] In this disclosure, before the step of providing the insulating layer 2 disposed on the carrier substrate 10, it may further include providing a third metal bump M3 disposed on the carrier substrate 10, wherein the third metal bump M3 may be electrically connected to the first metal layer 31.

[0062] Here, the materials of the substrate 10, release layer 11, first metal layer 31, second metal layer 32, and insulating layer 2 are as described above and will not be repeated here. Alternatively, the first metal layer 31, second metal layer 32, and insulating layer 2 can be prepared using methods similar to those described above, and will not be repeated here.

[0063] In this disclosure, a third metal layer 33 may also be formed on the second metal layer 32. Here, the third metal layer 33 may be prepared using materials or methods similar to those used for the first metal layer 31 or the second metal layer 32, which will not be described in detail here.

[0064] Then, as Figure 5BAs shown, a metal wire 6 is formed on the second region R2 of the insulating layer 2, and the metal wire 6 is electrically connected to the first metal layer 31. More specifically, the metal wire 6 may include a first metal segment 61 and a second metal segment 62, wherein the first metal segment 61 is electrically connected to the first metal layer 31 of the first metal bump M1, and the second metal segment 62 is electrically connected to the first metal layer 31 of the second metal bump M2.

[0065] In this disclosure, the material of the metal line 6 is not particularly limited, and may be, for example, gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, zinc, their alloys, or combinations thereof, but this disclosure is not limited thereto. Furthermore, the metal line 6 may be formed using methods such as printing, sputtering, electroplating, electroless plating, chemical vapor deposition, or combinations thereof, but this disclosure is not limited thereto.

[0066] Next, as Figure 5C As shown, the metal wire 6 disposed on the second region R2 of the insulating layer 2 can be used as a reference line. Electrical testing of the electronic component is performed using an electrical tester 5 through the reference line. This reduces damage to metal bumps (e.g., the first metal bump M1 and / or the second metal bump M2) during electrical testing, thereby improving the performance or reliability of the electronic component. Here, the electrical tester 5 includes a voltmeter, an ammeter, or a combination thereof, but this disclosure is not limited thereto.

[0067] Then, as Figure 5D As shown, metal wire 6 is removed to form another electronic component of this disclosure. This other electronic component includes: an insulating layer 2; and a first metal bump M1 disposed on the insulating layer 2, comprising: a first metal layer 31 disposed on the insulating layer 2; and a second metal layer 32 disposed on the first metal layer 31. Furthermore, in this disclosure, a second metal bump M2 may be disposed above the insulating layer 2, and the second metal bump M2 is disposed adjacent to the first metal bump M1. Here, a third metal bump M3 can be electrically connected to both the first metal bump M1 and the second metal bump M2. Therefore, the first metal bump M1 can be electrically connected to the second metal bump M2 through the third metal bump M3.

[0068] In addition, although not shown in the figure, after the step of removing the metal line 6, there may also be a step of removing the carrier substrate 10 and the release layer 11, so as to apply the electronic components to various electronic devices.

[0069] Here, the metal line 6 can be removed by etching, including laser etching, wet etching, dry etching, or a combination thereof, but this disclosure is not limited thereto. When the metal line 6 is removed by laser etching, some material of the metal line 6 may remain on the insulating layer 2. When the metal line 6 is removed by wet etching, the following can be obtained: Figure 1AThe electronic components shown.

[0070] In summary, by using a portion of the first metal layer 31 or the metal line 6 as a reference circuit, this disclosure can be provided for use during electrical testing to improve the impact on the performance or reliability of electronic components during electrical testing, thereby improving the performance or reliability of electronic devices.

[0071] In this disclosure, the electronic components may include redistribution layers and packaging components, such as fan-out package on package (FOPoP) components and 2.5D package components, but this disclosure is not limited thereto. The electronic components of this disclosure can be applied to various electronic devices, such as display devices, antenna devices, sensing devices, or splicing devices, but this disclosure is not limited thereto.

[0072] The electronic component fabrication method disclosed herein can be applied to redistribution-first (RDL first) or chip-first processes. Chip-first processes can be further divided into face-up and face-down processes. The fabrication method of chip-first processes is similar to... Figures 3A to 3F The preparation methods shown are similar, except for the following differences.

[0073] In one embodiment of this disclosure, for example in a chip-first process, such as Figure 6A As shown, after providing the carrier substrate 10 and release layer 11, the method may further include disposing a chip 7 on the carrier substrate 10. Then, an insulating layer 2, a first metal layer 31, and a second metal layer 32 are sequentially provided on the carrier substrate 10. The chip 7 is electrically connected to the first metal layer 31 and the second metal layer 32. Subsequently, as... Figures 3B to 3E As shown, after performing electrical tests using a portion of the first metal layer 31 as a reference circuit, a portion of the first metal layer 31 is removed, forming a circuit as shown. Figure 6A The structure shown is then removed from the carrier substrate 10 and release layer 11 to form the chip-facing electronic component of this embodiment.

[0074] Furthermore, in another embodiment of this disclosure, a chip-facing electronic component can be formed, such as... Figure 6B As shown, where, Figure 6B Electronic components and Figure 6A Similar, except for the following differences.

[0075] In the fabrication method of this embodiment, after providing the carrier substrate 10 and the release layer 11, the chip 7 is disposed on the carrier substrate 10, and then the carrier substrate 10 and the release layer 11 are removed. Next, components such as the insulating layer 2, the first metal layer 31, and the second metal layer 32 are sequentially provided on the chip 7, wherein the chip 7 can be electrically connected to the first metal layer 31 and the second metal layer 32. Then, as... Figures 3B to 3E As shown, after performing electrical tests using a portion of the first metal layer 31 as a reference circuit, a portion of the first metal layer 31 is removed to form the chip-facing electronic component of this embodiment. Figure 6B As shown.

[0076] Furthermore, although not shown in the figures, other embodiments of this disclosure may use, such as Figures 5A to 5D The fabrication method shown is used for chip-first processes, with metal line 6 serving as a reference line for electrical testing, which will not be described in detail here.

[0077] The specific embodiments described above should be interpreted as merely illustrative and not as limiting the remainder of this disclosure in any way. Features of different embodiments may be combined and used in combination as long as they do not conflict with each other.

Claims

1. An electronic component, characterized in that, Include: An insulating layer; A first metal bump is disposed on the insulating layer and includes: A first metal layer is disposed on the insulating layer; and A second metal layer is disposed on the first metal layer; and A second metal bump is disposed on the insulating layer and adjacent to the first metal bump. In one cross-sectional view, the first metal layer has a first width, the second metal layer has a second width, and the first width is smaller than the second width. In the cross-sectional view, the first metal layer has a first edge and a second edge opposite to the first edge, the first edge and the second edge are located below the second metal layer, and the first edge is closer to the second metal bump than the second edge. The second metal layer has a third edge and a fourth edge opposite to the third edge, the third edge is closer to the second metal bump than the fourth edge. The distance between the first edge and the third edge is greater than the distance between the second edge and the fourth edge.

2. The electronic component according to claim 1, characterized in that, The ratio of the first width to the second width is less than or equal to 0.

95.

3. The electronic component according to claim 1, characterized in that, The first metal bump also includes a third metal layer disposed on the second metal layer, the third metal layer having a third width, and the first width being smaller than the third width.

4. The electronic component according to claim 1, characterized in that, The first metal layer includes a first sub-metal layer and a second sub-metal layer. The first sub-metal layer is disposed between the second sub-metal layer and the insulating layer, wherein the width of the first sub-metal layer is smaller than the width of the second sub-metal layer.

5. The electronic component according to claim 1, characterized in that, The first metal layer has a first projection on the insulating layer, the second metal layer has a second projection on the insulating layer, and the area of ​​the first projection is smaller than the area of ​​the second projection.

6. A method for manufacturing electronic components, characterized in that, Includes the following steps: An insulating layer is provided, wherein the insulating layer includes a first region and a second region, and the following are sequentially disposed on the insulating layer: A first metal layer is disposed on the first region and the second region of the insulating layer; and A second metal layer is disposed on the first metal layer and corresponds to the first region of the insulating layer; A shield is formed on the first metal layer, and the shield corresponds to the second region of the insulating layer; Remove a portion of the first metal layer disposed in the second region; Remove the mask; as well as The first metal layer disposed in the second region is removed to form an electronic component, wherein the electronic component includes: the insulating layer; and a first metal bump disposed on the insulating layer and comprising: The first metal layer is disposed on the insulating layer; and The second metal layer is disposed on the first metal layer; In a cross-sectional view of the electronic component, the first metal layer has a first width, the second metal layer has a second width, and the first width is smaller than the second width.

7. The method according to claim 6, characterized in that, The first metal bump also includes a third metal layer disposed on the second metal layer, wherein, in the cross-sectional view of the electronic component, the third metal layer has a third width, and the first width is smaller than the third width.

8. A method for manufacturing electronic components, characterized in that, Includes the following steps: An insulating layer is provided, wherein the insulating layer includes a first region and a second region, and the following are sequentially disposed on the insulating layer: A first metal layer is disposed on the first region of the insulating layer; and A second metal layer is disposed on the first metal layer; A metal wire is formed on the second region of the insulating layer, and the metal wire is electrically connected to the first metal layer; as well as Remove the metal wire to form an electronic component, wherein the electronic component includes: the insulating layer; and a first metal bump disposed on the insulating layer and comprising: The first metal layer is disposed on the insulating layer; and The second metal layer is disposed on the first metal layer.

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