Display substrate, manufacturing method thereof, and display device
By using transparent plates instead of non-transparent storage capacitor plates in the display substrate, the problem of insufficient light-transmitting area in the prior art is solved, achieving a higher aperture ratio and display effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2019-08-23
- Publication Date
- 2026-07-31
AI Technical Summary
The storage capacitors in existing display substrates are made of non-transparent materials, resulting in a small light-transmitting area and low aperture ratio for pixel units.
Transparent plates are used to replace the traditional non-transparent storage capacitor plates, and the transparent plates and other structural layers are formed through specific process steps to ensure the light transmittance of the storage capacitor while maintaining electrical connection and functional integrity.
The increased aperture ratio of the display substrate increases the light-transmitting area of the pixel unit, thereby improving the display effect.
Smart Images
Figure CN115995470B_ABST
Abstract
Description
[0001] This application is a divisional application of Chinese patent application No. 201910785535.7, filed on August 23, 2019, entitled "Display substrate and manufacturing method thereof, display device". Technical Field
[0002] This application relates to the field of display technology, and in particular to a display substrate, its manufacturing method, and a display device. Background Technology
[0003] With the continuous development of the display industry, users have increasingly higher requirements for display substrates, and high-quality display substrates are becoming more and more popular.
[0004] Currently, display substrates include multiple pixel units defined by the intersection of data lines and gate lines. Each pixel unit includes a pixel electrode, a thin-film transistor (TFT), and a storage capacitor electrically connected to the pixel electrode. The TFT is used to apply electrical signals to the pixel electrode during the scanning phase, and the storage capacitor is used to maintain the potential of the pixel electrode during the non-scanning phase. The plates of the storage capacitor are typically made of a non-transparent material.
[0005] However, storage capacitors occupy a certain area within the pixel unit, and storage capacitors cannot transmit light. Therefore, the area of the light-transmitting region of the pixel unit is small, and the aperture ratio of the display substrate is low. Summary of the Invention
[0006] This application provides a display substrate, a manufacturing method thereof, and a display device, which helps to improve the aperture ratio of the display substrate. The technical solution is as follows:
[0007] On one hand, a display substrate is provided, the display substrate comprising:
[0008] A substrate, and a pixel unit located on the substrate, the pixel unit including a storage capacitor, the electrode of the storage capacitor being a transparent electrode.
[0009] Optionally, the storage capacitor includes a first electrode and a second electrode that are relatively distributed, wherein the first electrode is made of a metal oxide and the second electrode is made of a conductive semiconductor material.
[0010] Optionally, the pixel unit further includes: a light-shielding layer, an active layer, and a source-drain pattern, wherein the light-shielding layer is located between the substrate and the active layer, and the orthographic projection of the active layer on the substrate is located within the orthographic projection of the light-shielding layer on the substrate.
[0011] The first electrode plate includes a first sub-electrode plate and a second sub-electrode plate that are electrically connected. The first sub-electrode plate is distributed in the same layer as the light-shielding layer, the second sub-electrode plate is distributed in the same layer as the source-drain pattern, and the second electrode plate is distributed in the same layer as the active layer.
[0012] Optionally, the source-drain pattern is a transparent pattern.
[0013] Optionally, an insulating layer is provided between the light-shielding layer and the source-drain pattern, and the insulating layer has a connection hole, through which the second sub-electrode is electrically connected to the first sub-electrode.
[0014] Optionally, the pixel unit further includes: a buffer layer, a gate insulating layer, a gate, and an interlayer dielectric layer, wherein the buffer layer is located between the light-shielding layer and the active layer, and the active layer, the gate insulating layer, the gate, the interlayer dielectric layer, and the source-drain pattern constitute a thin-film transistor;
[0015] The insulating layer between the light-shielding layer and the source-drain pattern includes the buffer layer and the interlayer dielectric layer.
[0016] Optionally, the active layer, the gate insulating layer, the gate electrode, the interlayer dielectric layer, and the source / drain patterns are distributed along a direction away from the substrate. The source / drain patterns include a source electrode and a drain electrode. The orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate electrode on the substrate. The interlayer dielectric layer has source vias and drain vias. The source electrode contacts the active layer through the source vias, and the drain electrode contacts the active layer through the drain vias.
[0017] The pixel unit further includes: a passivation layer located on the side of the source-drain pattern away from the substrate, the passivation layer having a pixel via; and...
[0018] The pixel electrode is located on the side of the passivation layer away from the substrate, and the pixel electrode is electrically connected to the drain electrode through the pixel via.
[0019] On the other hand, a method for manufacturing a display substrate is provided, the method comprising:
[0020] Provide substrates;
[0021] A pixel unit is formed on the substrate, and the pixel unit includes a storage capacitor, the electrode of which is a transparent electrode.
[0022] Optionally, the storage capacitor includes a first electrode and a second electrode that are relatively distributed, wherein the first electrode is made of a metal oxide and the second electrode is made of a conductive semiconductor material.
[0023] Optionally, forming pixel units on the substrate includes:
[0024] A light-shielding layer and a first sub-electrode are formed on the substrate, wherein the light-shielding layer and the first sub-electrode are distributed in the same layer.
[0025] An active layer and a second electrode are formed on the substrate on which the light-shielding layer and the first sub-electrode are formed. The active layer and the second electrode are distributed in the same layer. The orthographic projection of the active layer on the substrate is located within the orthographic projection of the light-shielding layer on the substrate.
[0026] A source / drain pattern and a second sub-plate are formed on the substrate on which the active layer and the second sub-plate are formed. The source / drain pattern and the second sub-plate are distributed in the same layer. The second sub-plate is electrically connected to the first sub-plate.
[0027] Optionally, forming pixel units on the substrate further includes:
[0028] A buffer layer is formed on the substrate on which the light-shielding layer and the first sub-electrode are formed;
[0029] The step of forming an active layer and a second electrode on the substrate on which the light-shielding layer and the first sub-electrode are formed includes: forming the active layer and the second electrode on the substrate on which the buffer layer is formed;
[0030] The step of forming pixel units on the substrate further includes:
[0031] A gate insulating layer, a gate electrode, and an interlayer dielectric layer are formed on the substrate on which the active layer and the second electrode are formed. The active layer, the gate insulating layer, the gate electrode, and the interlayer dielectric layer are distributed in a direction away from the substrate. The orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate electrode on the substrate. The interlayer dielectric layer has a source via and a drain via.
[0032] Connecting holes are formed on the interlayer dielectric layer and the buffer layer;
[0033] The step of forming source / drain patterns and a second sub-plate on the substrate having the active layer and the second electrode plate includes:
[0034] The source-drain pattern and the second sub-plate are formed on the substrate on which the interlayer dielectric layer is formed. The source-drain pattern includes a source and a drain. The source is in contact with the active layer through the source via and the drain is in contact with the active layer through the drain via. The second sub-plate is electrically connected to the first sub-plate through the connection hole.
[0035] Optionally, forming a light-shielding layer and a first sub-electrode on the substrate includes:
[0036] A first conductive material layer is formed on the substrate, the first conductive material layer comprising a transparent conductive film and a light-shielding conductive film stacked in a direction away from the substrate;
[0037] Using a first grayscale mask, the first conductive material layer is processed through a single patterning process to obtain the light-shielding layer and the first sub-electrode plate. The light-shielding layer includes the superimposed transparent conductive film and the light-shielding conductive film, and the first sub-electrode plate includes the transparent conductive film.
[0038] The step of forming the active layer and the second electrode plate on the substrate on which the buffer layer is formed includes:
[0039] A semiconductor material layer is formed on the substrate on which the buffer layer is formed;
[0040] The active layer and semiconductor electrode are obtained by processing the semiconductor material layer through a single patterning process.
[0041] The semiconductor electrode is subjected to a conductor-enhancing process to obtain the second electrode.
[0042] The step of forming a gate insulating layer, a gate electrode, and an interlayer dielectric layer on the substrate on which the active layer and the second electrode plate are formed includes:
[0043] An initial gate insulating layer is formed on the substrate on which the active layer and the second electrode are formed;
[0044] The gate is formed on the substrate on which the initial gate insulating layer is formed;
[0045] The initial gate insulating layer is etched using the gate as a mask to obtain the gate insulating layer;
[0046] The interlayer dielectric layer is formed on the substrate on which the gate is formed;
[0047] The step of forming the source / drain pattern and the second sub-plate on the substrate on which the interlayer dielectric layer is formed includes:
[0048] The second conductive material layer is formed on the substrate on which the interlayer dielectric layer is formed, the second conductive material layer comprising a transparent conductive film and a light-shielding conductive film stacked in a direction away from the substrate.
[0049] Using a second grayscale mask, the second conductive material layer is processed through a single patterning process to obtain the source / drain pattern and the second sub-plate. The source / drain pattern includes the transparent conductive film, and the second sub-plate includes the transparent conductive film.
[0050] Optionally, forming pixel units on the substrate includes:
[0051] A light-shielding layer and a first sub-electrode are formed on the substrate, wherein the light-shielding layer and the first sub-electrode are distributed in the same layer.
[0052] A buffer layer is formed on the substrate on which the light-shielding layer and the first sub-electrode are formed;
[0053] An active layer and a semiconductor electrode are formed on the substrate on which the buffer layer is formed, the active layer and the semiconductor electrode are distributed in the same layer, and the orthographic projection of the active layer on the substrate is located within the orthographic projection of the light-shielding layer on the substrate.
[0054] An initial gate insulating layer is formed on the substrate on which the active layer and the semiconductor electrode are formed;
[0055] A gate is formed on the substrate on which the initial gate insulating layer is formed;
[0056] The initial gate insulating layer is etched using the gate as a mask to obtain the gate insulating layer, exposing the semiconductor electrode. The orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate on the substrate.
[0057] The semiconductor electrode is subjected to a conductor-enhancing process to obtain the second electrode.
[0058] An interlayer dielectric layer is formed on the substrate on which the gate is formed, the interlayer dielectric layer having a source via and a drain via;
[0059] Connecting holes are formed on the interlayer dielectric layer and the buffer layer;
[0060] The source-drain pattern and the second sub-plate are formed on the substrate on which the interlayer dielectric layer is formed. The source-drain pattern includes a source and a drain. The source is in contact with the active layer through the source via and the drain is in contact with the active layer through the drain via. The second sub-plate is electrically connected to the first sub-plate through the connection hole.
[0061] Optionally, forming pixel units on the substrate further includes:
[0062] A passivation layer is formed on the substrate having the source-drain pattern and the second sub-plate, the passivation layer having pixel vias;
[0063] A pixel electrode is formed on the substrate on which the passivation layer is formed, and the pixel electrode is electrically connected to the drain electrode through the pixel via.
[0064] In another aspect, a display device is provided, comprising the display substrate described in the preceding aspect.
[0065] The beneficial effects of the technical solution provided in this application are:
[0066] The display substrate, manufacturing method, and display device provided in this application embodiment have the following advantages: in the display substrate, the pixel unit includes a storage capacitor, and the electrode plate of the storage capacitor is a transparent electrode plate. Therefore, the storage capacitor can transmit light, the light-transmitting area of the pixel unit is large, and the aperture ratio of the display substrate is high.
[0067] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description
[0068] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0069] Figure 1 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this application;
[0070] Figure 2 This is a schematic diagram of another display substrate structure provided in an embodiment of this application;
[0071] Figure 3 This is a schematic diagram of another display substrate provided in an embodiment of this application;
[0072] Figure 4 This is a flowchart of a method for manufacturing a display substrate according to an embodiment of this application;
[0073] Figure 5 This is a flowchart of another method for manufacturing a display substrate provided in an embodiment of this application;
[0074] Figure 6 This is a flowchart illustrating a method for forming a light-shielding layer and a first sub-electrode plate on a substrate according to an embodiment of this application.
[0075] Figure 7This is a schematic diagram of a first conductive material layer formed on a substrate according to an embodiment of this application;
[0076] Figure 8 This is a schematic diagram of a first conductive material layer after processing, provided in an embodiment of this application;
[0077] Figure 9 This is a schematic diagram provided in an embodiment of the present application showing a buffer layer formed on a substrate having a light-shielding layer and a first sub-electrode.
[0078] Figure 10 This is a flowchart of a method for forming an active layer and a second electrode plate on a substrate with a buffer layer provided in an embodiment of this application;
[0079] Figure 11 This is a schematic diagram of a semiconductor material layer formed on a substrate with a buffer layer, provided in an embodiment of this application.
[0080] Figure 12 This is a schematic diagram of a semiconductor material layer processed by a single patterning process, provided in an embodiment of this application.
[0081] Figure 13 This is a schematic diagram of a semiconductor electrode plate after being conductive, provided in an embodiment of this application;
[0082] Figure 14 This is a flowchart of a method for forming a gate insulating layer, a gate electrode, and an interlayer dielectric layer on a substrate on which an active layer and a second electrode are formed, according to an embodiment of this application.
[0083] Figure 15 This is a schematic diagram provided in an embodiment of the present application, showing the formation of an initial gate insulating layer on a substrate on which an active layer and a second electrode plate are formed.
[0084] Figure 16 This is a schematic diagram of a gate formed on a substrate having an initial gate insulating layer, provided in an embodiment of this application.
[0085] Figure 17 This is a schematic diagram of the initial gate insulating layer after etching, provided in an embodiment of this application;
[0086] Figure 18 This is a schematic diagram of an interlayer dielectric layer formed on a substrate with a gate formed, provided in an embodiment of this application;
[0087] Figure 19 This is a schematic diagram of a connection hole formed on the interlayer dielectric layer and the buffer layer according to an embodiment of this application;
[0088] Figure 20This is a flowchart of a method for forming source and drain patterns and a second sub-plate on a substrate having an interlayer dielectric layer, as provided in an embodiment of this application.
[0089] Figure 21 This is a schematic diagram of a second conductive material layer formed on a substrate having an interlayer dielectric layer, as provided in an embodiment of this application.
[0090] Figure 22 This is a schematic diagram provided in an embodiment of the present application, showing the formation of a passivation layer on a substrate on which an active drain pattern and a second sub-electrode are formed;
[0091] Figure 23 This is a flowchart of another method for manufacturing a display substrate provided in an embodiment of this application;
[0092] Figure 24 This is a schematic diagram provided in an embodiment of the present application, showing the formation of an initial gate insulating layer on a substrate on which an active layer and a semiconductor electrode are formed;
[0093] Figure 25 This is a schematic diagram of a gate formed on a substrate having an initial gate insulating layer, provided in an embodiment of this application.
[0094] Figure 26 This is a schematic diagram of the initial gate insulating layer after etching, provided in an embodiment of this application.
[0095] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Detailed Implementation
[0096] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0097] Please refer to Figure 1 It shows a schematic diagram of the structure of a display substrate 0 provided in an embodiment of this application, see below. Figure 1 The display substrate 0 includes a substrate 01, and pixel units located on the substrate 01. Figure 1 (Not shown in the image), the pixel unit includes a storage capacitor 02, the electrode of which is a transparent electrode.
[0098] In summary, the display substrate provided in this application embodiment has a large light-transmitting area and a high aperture ratio because the pixel unit in the display substrate includes a storage capacitor and the electrode of the storage capacitor is a transparent electrode.
[0099] The substrate 01 can be a rigid substrate made of a light-guiding, non-metallic transparent material such as glass or quartz, or a flexible substrate made of a material such as polyimide (PI). The electrode material of the storage capacitor 02 can be a transparent conductive material, allowing the electrode of the storage capacitor 02 to be a transparent electrode. For example... Figure 1 As shown, the storage capacitor 02 includes a first electrode 021 and a second electrode 022 that are relatively distributed. The first electrode 021 and the second electrode 022 are insulated from each other. The material of the first electrode 021 may include a metal oxide, and the material of the second electrode 022 may include a conductive semiconductor material. For example, the material of the first electrode 021 may be one or a combination of indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum-doped zinc oxide (ZnO:Al), and the material of the second electrode 022 may be a conductive indium gallium zinc oxide (IGZO) or a conductive indium tin zinc oxide (ITZO), etc.
[0100] Alternatively, please refer to Figure 2 It shows a schematic diagram of another display substrate 0 provided in an embodiment of this application. See also Figure 2 The pixel unit also includes a light-shielding layer 03, an active layer 04, and a source-drain pattern 05. The light-shielding layer 03 is located between the substrate 01 and the active layer 04. The orthographic projection of the active layer 04 onto the substrate 01 lies within the orthographic projection of the light-shielding layer 03 onto the substrate 01. The light-shielding layer 03 can block the active layer 04, preventing external light from the display substrate 0 from shining onto the active layer 04. The source-drain pattern 05 can be a transparent pattern, allowing light to pass through the area where the source-drain pattern 05 is located, thus increasing the area of the light-transmitting region of the pixel unit. Figure 2As shown, the storage capacitor 02 includes a first electrode 021 and a second electrode 022 distributed opposite to each other. The first electrode 021 includes a first sub-electrode 0211 and a second sub-electrode 0212 electrically connected. The first sub-electrode 0211 is distributed in the same layer as the light-shielding layer 03, the second sub-electrode 0212 is distributed in the same layer as the source-drain pattern 05, and the second electrode 022 is distributed in the same layer as the active layer 04. An insulating layer is provided between the light-shielding layer 03 and the source-drain pattern 05, and the insulating layer has connection holes. Figure 2 (Not shown in the diagram), the second sub-electrode 0212 is electrically connected to the first sub-electrode 0211 through this connection hole.
[0101] The light-shielding layer 03 can be a single-layer or multi-layer structure. Optionally, the light-shielding layer 03 may include a transparent conductive film and a light-shielding conductive film stacked along a direction away from the substrate 01. The transparent conductive film may be made of ITO, and the light-shielding conductive film may include a first light-shielding film and a second light-shielding film stacked together. The light-shielding film may be made of one or more alloys of metals Al, Mo, or Cu, and the materials of the first and second light-shielding films may be the same or different. For example, the first light-shielding film may be made of Mo, and the second light-shielding film may be made of Al. The active layer 04 may be made of a-Si, p-Si, IGZO, or ITZO. The source-drain pattern 05 may be a single-layer or multi-layer structure. Optionally, the source-drain pattern 05 can be a single-layer structure made of ITO. Alternatively, the source-drain pattern 05 can include a transparent conductive film and a light-shielding conductive film stacked along a direction away from the substrate 01. The transparent conductive film can be made of ITO, and the light-shielding conductive film can include a first light-shielding film and a second light-shielding film stacked together. The light-shielding film can be made of one or more alloys of metal Nb, metal Mo, or metal Cu. The materials of the first light-shielding film and the second light-shielding film can be the same or different. For example, the material of the first light-shielding film can be a MoNb alloy, and the material of the second light-shielding film can be metal Cu.
[0102] Alternatively, please continue to refer to Figure 2The pixel unit also includes: a buffer layer 06, a gate insulating layer 07, a gate 08, and an interlayer dielectric layer 09. The buffer layer 06 is located between the light-shielding layer 03 and the active layer 04. The active layer 04, the gate insulating layer 07, the gate 08, the interlayer dielectric layer 09, and the source-drain pattern 05 constitute a thin film transistor G. The buffer layer 06 and the interlayer dielectric layer 09 are located between the light-shielding layer 03 and the source-drain pattern 05. The buffer layer 06 and the interlayer dielectric layer 09 are respectively provided with through holes. The through holes on the buffer layer 06 and the through holes on the interlayer dielectric layer 09 are connected to form a connection hole. The second sub-electrode plate 0212 is electrically connected to the first sub-electrode plate 0211 through the connection hole. Optionally, the active layer 04, gate insulating layer 07, gate 08, interlayer dielectric layer 09, and source / drain patterns 05 are distributed along a direction away from the substrate 01. The source / drain patterns 05 include a source 051 and a drain 052. The orthographic projection of the gate insulating layer 07 onto the substrate 01 coincides with the orthographic projection of the gate 08 onto the substrate 01. The interlayer dielectric layer 09 has source vias and drain vias. Figure 2 (Not marked in the text), the source electrode 051 contacts the active layer 04 through the source electrode via, and the drain electrode 052 contacts the active layer 04 through the drain electrode via.
[0103] Optionally, the materials of the buffer layer 06, the gate insulating layer 07, and the interlayer dielectric layer 09 can all be one or a combination of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNx). The gate 08 can be a single-layer structure or a multi-layer structure. For example, the gate 08 can include a first film layer and a second film layer stacked in a direction away from the gate insulating layer 07. The material of the first film layer can be metallic Cu, and the material of the second film layer can be a MoNb alloy.
[0104] Alternatively, please refer to Figure 3 It shows a schematic diagram of another display substrate 0 provided in an embodiment of this application, see [link]. Figure 3 ,exist Figure 2 Based on this, the display substrate 0 may further include a passivation layer 010 and a pixel electrode 011. The passivation layer 010 is located on the side of the source / drain pattern 05 away from the substrate 01, and the passivation layer 010 has pixel vias. Figure 3 (Not shown in the image), the pixel electrode 011 is located on the side of the passivation layer 010 away from the substrate 01. The pixel electrode 011 is electrically connected to the drain electrode 052 through a pixel via on the passivation layer 010. The material of the passivation layer 010 can be one or a combination of SiOx, SiNx, or SiOxNx, and the material of the pixel electrode 011 can be one or a combination of ITO, IZO, or ZnO:Al.
[0105] Those skilled in the art will readily understand that the display substrate described in the embodiments of this application is merely exemplary. In actual applications, the display substrate may include more or fewer structures than the display substrate described in this application. For example, the display substrate may also include a common electrode, and when the display substrate is an electroluminescent display substrate, the pixel electrode may be called the anode and the common electrode may be called the cathode. The display substrate may also include structures such as an electroluminescent layer located between the anode and the cathode. These will not be described in detail in the embodiments of this application.
[0106] In summary, the display substrate provided in this application embodiment has a large light-transmitting area and a high aperture ratio because the pixel unit in the display substrate includes a storage capacitor and the electrode of the storage capacitor is a transparent electrode.
[0107] Please refer to Figure 4 It illustrates a method flowchart of a display substrate manufacturing method provided in an embodiment of this application. This method can be used to manufacture... Figures 1 to 3 Any of the display substrates shown. See also Figure 4 The method may include the following steps:
[0108] In step 101, a substrate is provided.
[0109] In step 102, a pixel unit is formed on the substrate. The pixel unit includes a storage capacitor, and the electrode of the storage capacitor is a transparent electrode.
[0110] In summary, in the display substrate manufactured by the method provided in this application embodiment, the pixel unit includes a storage capacitor, and the electrode of the storage capacitor is a transparent electrode. Therefore, the storage capacitor can transmit light, resulting in a larger light-transmitting area of the pixel unit and a higher aperture ratio of the display substrate.
[0111] Please refer to Figure 5 It illustrates a method flowchart of another display substrate manufacturing method provided in an embodiment of this application, which can be used to manufacture... Figures 1 to 3 Any of the display substrates 0 shown in this embodiment are used for manufacturing Figure 3 The following explanation uses the display substrate 0 shown as an example. See also... Figure 5 The method includes the following steps:
[0112] In step 201, a light-shielding layer and a first sub-electrode are formed on the substrate, and the light-shielding layer and the first sub-electrode are distributed in the same layer.
[0113] In this embodiment, the light-shielding layer and the first sub-electrode can be formed in a single process. Optionally, please refer to... Figure 6 This diagram illustrates a method for forming a light-shielding layer and a first sub-electrode plate on a substrate according to an embodiment of this application. See also... Figure 6This method may include the following sub-steps:
[0114] In sub-step 2011, a first conductive material layer is formed on the substrate. The first conductive material layer includes a transparent conductive film and a light-shielding conductive film stacked in a direction away from the substrate.
[0115] Please refer to Figure 7 This illustration shows a schematic diagram of a first conductive material layer W formed on a substrate 01 according to an embodiment of this application. The first conductive material layer W may include a transparent conductive film and a light-shielding conductive film stacked in a direction away from the substrate 01. Both the transparent conductive film and the light-shielding conductive film can be single-layer or multi-layer structures. Optionally, the transparent conductive film is a single-layer structure, and the material of the transparent conductive film can be ITO. The light-shielding conductive film includes a first light-shielding film and a second light-shielding film stacked in a direction away from the substrate 01. The material of the first light-shielding film can be metal Al, and the material of the second light-shielding film can be metal Mo. For example, ITO, metal Al, and metal Mo can be sequentially deposited on the substrate 01 to obtain the first conductive material layer W.
[0116] In sub-step 2012, a first grayscale mask is used to process the first conductive material layer through a single patterning process to obtain a light-shielding layer and a first sub-electrode. The light-shielding layer includes a superimposed transparent conductive film and a light-shielding conductive film, and the first sub-electrode includes a transparent conductive film.
[0117] Please refer to Figure 8 The illustration shows a schematic diagram of a first conductive material layer W after processing according to an embodiment of this application. The light-shielding layer 03 and the first sub-electrode 0211 are distributed in the same layer. The light-shielding layer 03 may include a superimposed transparent conductive film and a light-shielding conductive film. The first sub-electrode 0211 may include a transparent conductive film.
[0118] In this embodiment, a first grayscale mask can be used to process the first conductive material layer W through a single patterning process to obtain the light-shielding layer 03 and the first sub-electrode 0211. Optionally, firstly, a photoresist layer can be formed on the first conductive material layer W. Then, the photoresist layer is exposed and developed using the first grayscale mask to obtain a photoresist pattern. This photoresist pattern includes a first photoresist region, a second photoresist region, and a photoresist completely removed region. The thickness of the first photoresist region is greater than the thickness of the second photoresist region. Then, the region on the first conductive material layer W corresponding to the photoresist completely removed region is etched to remove the first conductive material layer W corresponding to the photoresist completely removed region. After that, the photoresist in the second photoresist region is removed, and the region on the first conductive material layer W corresponding to the second photoresist region is etched to remove the light-shielding conductive film in the region on the first conductive material layer W corresponding to the second photoresist region to obtain the first sub-electrode 0211. Finally, the photoresist in the first photoresist region is removed to obtain the light-shielding layer 03.
[0119] In step 202, a buffer layer is formed on the substrate on which the light-shielding layer and the first sub-electrode are formed.
[0120] Please refer to Figure 9 This illustration shows a schematic diagram of a buffer layer 06 formed on a substrate 01 having a light-shielding layer 03 and a first sub-electrode 0211, according to an embodiment of this application. The buffer layer 06 covers the light-shielding layer 03 and the first sub-electrode 0211. The material of the buffer layer 06 can be one or a combination of SiOx, SiNx, or SiOxNx. For example, using SiOx as the material, the buffer layer 06 is formed on the substrate 01 having the light-shielding layer 03 and the first sub-electrode 0211 by any of the processes such as deposition, coating, or sputtering.
[0121] In step 203, an active layer and a second electrode are formed on a substrate on which a buffer layer is formed. The active layer and the second electrode are distributed in the same layer, and the orthogonal projection of the active layer on the substrate is located within the orthogonal projection of the light-shielding layer on the substrate.
[0122] In this embodiment, the active layer and the second electrode can be formed in a single process. Please refer to... Figure 10 This diagram illustrates a method for forming an active layer and a second electrode on a substrate with a buffer layer, according to an embodiment of this application. See also... Figure 10 This method may include the following sub-steps:
[0123] In sub-step 2031, a semiconductor material layer is formed on the substrate on which the buffer layer is formed.
[0124] Please refer to Figure 11This illustration shows a schematic diagram of a semiconductor material layer X formed on a substrate 01 with a buffer layer 06, according to an embodiment of this application. The material of the semiconductor material layer X can be IGZO or ITZO. For example, using IGZO as the material, the semiconductor material layer X is formed on the substrate 01 with the buffer layer 06 by any of the processes such as deposition, magnetron sputtering, or thermal evaporation.
[0125] In sub-step 2032, the semiconductor material layer is processed through a patterning process to obtain the active layer and the semiconductor electrode.
[0126] Please refer to Figure 12 This illustration shows a schematic diagram of a semiconductor material layer X processed by a single patterning process according to an embodiment of this application. The active layer 04 and the semiconductor electrode T are distributed in the same layer, and the orthographic projection of the active layer 04 on the substrate 01 is located within the orthographic projection of the light-shielding layer 03 on the substrate 01.
[0127] In sub-step 2033, the semiconductor electrode is subjected to a conductor-forming process to obtain a second electrode.
[0128] Please refer to Figure 13 The illustration shows a schematic diagram of a semiconductor electrode T after being conductiveized according to an embodiment of this application. Conducting the semiconductor electrode T with conductors yields a second electrode 022, which is distributed co-layered with the active layer 04. Optionally, the second electrode 022 can be obtained by conducting the semiconductor electrode T with conductors through processes such as doping.
[0129] In step 204, a gate insulating layer, a gate electrode, and an interlayer dielectric layer are formed on the substrate on which the active layer and the second electrode are formed. The active layer, the gate insulating layer, the gate electrode, and the interlayer dielectric layer are distributed in a direction away from the substrate. The orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate electrode on the substrate. The interlayer dielectric layer has a source via and a drain via.
[0130] Alternatively, please refer to Figure 14 This diagram illustrates a method for forming a gate insulating layer, a gate electrode, and an interlayer dielectric layer on a substrate forming an active layer and a second electrode, according to an embodiment of this application. See also... Figure 14 This method may include the following sub-steps:
[0131] In sub-step 2041, an initial gate insulating layer is formed on the substrate on which the active layer and the second electrode plate are formed.
[0132] Please refer to Figure 15This illustration shows a schematic diagram of an initial gate insulating layer Y formed on a substrate 01 on which an active layer 04 and a second electrode 022 are formed, according to an embodiment of this application. The initial gate insulating layer Y covers the active layer 04 and the second electrode 022. The material of the initial gate insulating layer Y can be one or a combination of SiOx, SiNx, or SiOxNx. For example, using SiOx as the material, the initial gate insulating layer Y is formed on the substrate 01 on which the active layer 04 and the second electrode 022 are formed by any of the processes such as deposition, coating, or sputtering.
[0133] In sub-step 2042, a gate is formed on a substrate on which an initial gate insulating layer is formed.
[0134] Please refer to Figure 16 This illustration shows a schematic diagram of a gate 08 formed on a substrate 01 with an initial gate insulating layer Y, according to an embodiment of this application. The orthogonal projection of the gate 08 onto the substrate 01 lies within the orthogonal projection of the active layer 04 onto the substrate 01. Optionally, the gate 08 can be a single-layer structure or a multi-layer structure. For example, the gate 08 may include a first film layer and a second film layer stacked along a direction away from the initial gate insulating layer Y. The material of the first film layer can be metallic Cu, and the material of the second film layer can be a MoNb alloy. For example, a gate material layer can be obtained by sequentially depositing metallic Cu and a MoNb alloy on the initial gate insulating layer Y, and the gate 08 can be obtained by processing the gate material layer through a single patterning process.
[0135] In sub-step 2043, the initial gate insulating layer is etched using the gate as a mask to obtain the gate insulating layer.
[0136] Please refer to Figure 17 The illustration shows a schematic diagram of an initial gate insulating layer Y after etching according to an embodiment of this application. After etching the initial gate insulating layer Y with the gate 08 as a mask, a gate insulating layer 07 can be obtained. The orthogonal projection of the gate insulating layer 07 on the substrate 01 coincides with the orthogonal projection of the gate 08 on the substrate 01.
[0137] In sub-step 2044, an interlayer dielectric layer is formed on the substrate on which the gate is formed.
[0138] Please refer to Figure 18This illustration shows a schematic diagram of an interlayer dielectric layer 09 formed on a substrate 01 with a gate 08, according to an embodiment of this application. The interlayer dielectric layer 09 has source vias b and drain vias c. The material of the interlayer dielectric layer 09 can be one or a combination of SiOx, SiNx, or SiOxNx. For example, a SiOx material layer can be formed on the substrate 01 with the gate 08 formed by any of the processes such as deposition, coating, or sputtering. The SiOx material layer is then processed by a single patterning process to form the source vias b and drain vias c, resulting in the interlayer dielectric layer 09.
[0139] In step 205, connection holes are formed on the interlayer dielectric layer and the buffer layer.
[0140] Please refer to Figure 19 The illustration shows a schematic diagram of a connection hole a formed on the interlayer dielectric layer 09 and the buffer layer 06 according to an embodiment of this application. The connection hole a penetrates through the interlayer dielectric layer 09 and the buffer layer 06. Optionally, the connection hole a can be formed on the interlayer dielectric layer 09 and the buffer layer 06 in a single patterning process.
[0141] In step 206, a source-drain pattern and a second sub-plate are formed on a substrate on which an interlayer dielectric layer is formed. The source-drain pattern includes a source and a drain. The source is in contact with the active layer through a source via and the drain is in contact with the active layer through a drain via. The second sub-plate is electrically connected to the first sub-plate through a connection hole.
[0142] In the embodiments of this application, the source-drain pattern and the second sub-plate can be formed in a single process. Optionally, please refer to... Figure 20 This diagram illustrates a method flowchart for forming source / drain patterns and a second sub-plate on a substrate with an interlayer dielectric layer, according to an embodiment of this application. See also... Figure 20 This method may include the following sub-steps:
[0143] In sub-step 2061, a second conductive material layer is formed on a substrate on which an interlayer dielectric layer is formed. The second conductive material layer includes a transparent conductive film and a light-shielding conductive film stacked in a direction away from the substrate.
[0144] Please refer to Figure 21This illustration shows a schematic diagram of a second conductive material layer Z formed on a substrate 01 with an interlayer dielectric layer 09, according to an embodiment of this application. The second conductive material layer Z may include a transparent conductive film and a light-shielding conductive film stacked in a direction away from the substrate 01. Both the transparent conductive film and the light-shielding conductive film can be single-layer or multi-layer structures. Optionally, the transparent conductive film is a single-layer structure, and its material can be one or more combinations of ITO, IZO, or ZnO:Al. The light-shielding conductive film includes a first light-shielding film and a second light-shielding film stacked in a direction away from the substrate 01. The first light-shielding film can be made of MoNb alloy, and the second light-shielding film can be made of metallic Cu. For example, ITO, MoNb alloy, and metallic Mo can be sequentially deposited on the substrate 01 with the interlayer dielectric layer 09 to obtain the second conductive material layer Z.
[0145] In sub-step 2062, a second grayscale mask is used to process the second conductive material layer through a patterning process to obtain the source-drain pattern and the second sub-plate. The source-drain pattern includes a superimposed transparent conductive film and a light-shielding conductive film, and the second sub-plate includes a transparent conductive film.
[0146] A schematic diagram of the second conductive material layer Z after a single patterning process can be seen as follows: Figure 2 As shown. After processing the second conductive material layer Z through a single patterning process, the source / drain pattern 05 and the second sub-plate 0212 can be obtained. The source / drain pattern 05 and the second sub-plate 0212 are distributed in the same layer. The source / drain pattern 05 includes a source 051 and a drain 052. The source 051 is connected through a source via (…). Figure 2 (Not shown in the image) is in contact with the active layer 04, and the drain 052 is connected through a drain via ( Figure 2 (Not shown in the diagram) contacts the active layer 04, and the second sub-electrode 0212 is connected through the connection hole ( Figure 2 (Not shown in the image) is electrically connected to the first sub-electrode 0211. The source-drain pattern 05 includes a superimposed transparent conductive film and a light-shielding conductive film. The second sub-electrode 0212 includes a transparent conductive film.
[0147] In this embodiment, a second grayscale mask can be used to process the second conductive material layer Z through a single patterning process to obtain the source / drain pattern 05 and the second sub-plate 0212. Optionally, firstly, a photoresist layer can be formed on the second conductive material layer Z. Then, the photoresist layer is exposed and developed using the second grayscale mask to obtain a photoresist pattern. This photoresist pattern includes a first photoresist region, a second photoresist region, and a photoresist completely removed region. The thickness of the first photoresist region is greater than the thickness of the second photoresist region. Then, the region on the second conductive material layer Z corresponding to the photoresist completely removed region is etched to remove the second conductive material layer Z corresponding to the photoresist completely removed region. After that, the photoresist in the second photoresist region is removed, and the region on the second conductive material layer Z corresponding to the second photoresist region is etched to remove the light-shielding conductive film in the region on the second conductive material layer Z corresponding to the second photoresist region to obtain the second sub-plate 0212. Finally, the photoresist in the first photoresist region is removed to obtain the source / drain pattern 05.
[0148] It should be noted that the embodiments of this application are illustrated using the example of the source-drain pattern 05 including a superimposed transparent conductive film and a light-shielding conductive film. The source-drain pattern 05 may also include only a transparent conductive film, allowing light to pass through the area where the source-drain pattern 05 is located, thereby increasing the area of the light-transmitting region of the pixel unit. In addition, it is easy to understand that the display substrate may also include data lines. The data lines are usually distributed in the same layer as the source-drain pattern 05. The data lines may include superimposed transparent conductive films and light-shielding conductive films. When the source-drain pattern 05 and the second sub-electrode 0212 only include transparent conductive films, and the data lines include superimposed transparent conductive films and light-shielding conductive films, a second grayscale mask can be used to process the second conductive material layer through a single patterning process to obtain the source-drain pattern 05, the second sub-electrode 0212, and the data lines. The embodiments of this application will not be described in detail here.
[0149] In step 207, a passivation layer is formed on the substrate on which the active drain pattern and the second sub-plate are formed. The passivation layer has pixel vias.
[0150] Please refer to Figure 22 This illustration shows a schematic diagram of a passivation layer 010 formed on a substrate 01 on which an active drain pattern 05 and a second sub-plate 0212 are formed, according to an embodiment of this application. The passivation layer 010 may have pixel vias d. Optionally, the material of the passivation layer 010 may be one or a combination of SiOx, SiNx, or SiOxNx. For example, a SiOx material layer is formed on the substrate 01 on which the active drain pattern 05 and the second sub-plate 0212 are formed by any of the processes such as deposition, coating, or sputtering. The SiOx material layer is then processed by a single patterning process to form pixel vias d, thereby obtaining the passivation layer 010.
[0151] In step 208, a pixel electrode is formed on a substrate on which a passivation layer is formed, and the pixel electrode is electrically connected to the drain electrode through a pixel via.
[0152] A schematic diagram showing the formation of pixel electrodes 011 on a substrate 01 with a passivation layer 010 is shown below. Figure 3 As shown, pixel electrode 011 passes through a pixel via ( Figure 3 (Not shown in the image) is connected to the drain 052. For example, an ITO material layer is formed on a substrate 01 on which a passivation layer 010 is formed by any of the processes such as deposition, coating or sputtering, and the pixel electrode 011 is obtained by processing the ITO material layer by a single patterning process.
[0153] In summary, in the display substrate manufactured by the method provided in this application embodiment, the pixel unit includes a storage capacitor, and the electrode of the storage capacitor is a transparent electrode. Therefore, the storage capacitor can transmit light, the light-transmitting area of the pixel unit is large, and the aperture ratio of the display substrate is high.
[0154] Please refer to Figure 23 It illustrates a method flowchart of another display substrate manufacturing method provided in an embodiment of this application, which can be used to manufacture... Figures 1 to 3 Any of the display substrates shown, Figure 23 To manufacture embodiments of this application Figure 3 The following explanation uses the display substrate 0 shown as an example. See also... Figure 23 The method includes the following steps:
[0155] In step 301, a light-shielding layer and a first sub-electrode are formed on the substrate, and the light-shielding layer and the first sub-electrode are distributed in the same layer.
[0156] In step 302, a buffer layer is formed on the substrate on which the light-shielding layer and the first sub-electrode are formed.
[0157] The implementation process of steps 301 to 302 can be referred to Figure 5 The implementation process of steps 201 to 202 in the illustrated embodiment and Figures 6 to 9 The embodiments of this application will not be described in detail here.
[0158] In step 303, an active layer and a semiconductor electrode are formed on a substrate on which a buffer layer is formed. The active layer and the semiconductor electrode are distributed in the same layer, and the orthogonal projection of the active layer on the substrate is located within the orthogonal projection of the light-shielding layer on the substrate.
[0159] The implementation process of step 303 can be referred to Figure 5 The implementation process of sub-steps 2031 to 2032 in the illustrated embodiment and Figure 11 and Figure 12The embodiments of this application will not be described in detail here.
[0160] In step 304, an initial gate insulating layer is formed on the substrate on which the active layer and the semiconductor electrode are formed.
[0161] Please refer to Figure 24 This illustration shows a schematic diagram of an initial gate insulating layer Y formed on a substrate 01 on which an active layer 04 and a semiconductor electrode T are formed, according to an embodiment of this application. The initial gate insulating layer Y covers the active layer 04 and the semiconductor electrode T. The implementation process of this step 304 can be referred to... Figure 5 The implementation process of sub-step 2041 in the illustrated embodiment will not be described again in this application embodiment.
[0162] In step 305, a gate is formed on a substrate on which an initial gate insulating layer is formed.
[0163] Please refer to Figure 25 This illustration shows a schematic diagram of a process following the formation of a gate 08 on a substrate 01 with an initial gate insulating layer Y, as provided in an embodiment of this application. The implementation process of step 305 can be found in [reference needed]. Figure 5 The implementation process of sub-step 2042 in the illustrated embodiment will not be repeated here.
[0164] In step 306, the initial gate insulating layer is etched using the gate as a mask to obtain the gate insulating layer, exposing the semiconductor electrode. The orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate on the substrate.
[0165] Please refer to Figure 26 The illustration shows a schematic diagram of an initial gate insulating layer Y after etching according to an embodiment of this application. After etching the initial gate insulating layer Y with the gate 08 as a mask, the gate insulating layer 07 can be obtained, exposing the semiconductor electrode T. The orthographic projection of the gate insulating layer 07 on the substrate 01 coincides with the orthographic projection of the gate 08 on the substrate 01.
[0166] In step 307, the semiconductor electrode is subjected to a conductor-forming process to obtain a second electrode.
[0167] A schematic diagram of the semiconductor electrode T after conductor-forming treatment can be shown as follows: Figure 17 As shown, a second electrode 022 can be obtained by performing a conductor-enhancing treatment on the semiconductor electrode T. The second electrode 022 is distributed in the same layer as the active layer 04. Optionally, the second electrode 022 can be obtained by performing a conductor-enhancing treatment on the semiconductor electrode T using processes such as doping.
[0168] In step 308, an interlayer dielectric layer is formed on the substrate on which the gate is formed, the interlayer dielectric layer having source vias and drain vias.
[0169] The implementation process of step 308 can be referred to this application. Figure 5 The implementation process of sub-step 2044 in the illustrated embodiment and Figure 18 The embodiments of this application will not be described in detail here.
[0170] In step 309, connection holes are formed on the interlayer dielectric layer and the buffer layer.
[0171] In step 310, a source-drain pattern and a second sub-plate are formed on a substrate on which an interlayer dielectric layer is formed. The source-drain pattern includes a source and a drain. The source is in contact with the active layer through a source via and the drain is in contact with the active layer through a drain via. The second sub-plate is electrically connected to the first sub-plate through a connection hole.
[0172] In step 311, a passivation layer is formed on the substrate on which the active drain pattern and the second sub-plate are formed. The passivation layer has pixel vias.
[0173] In step 312, a pixel electrode is formed on a substrate on which a passivation layer is formed, and the pixel electrode is electrically connected to the drain electrode through a pixel via.
[0174] The implementation process of steps 309 to 312 above can be referred to Figure 5 The implementation process of steps 205 to 208 in the illustrated embodiment and Figures 19 to 22 , Figure 3 The embodiments of this application will not be described in detail here.
[0175] In summary, in the display substrate manufactured by the method provided in this application embodiment, the pixel unit includes a storage capacitor, and the electrode of the storage capacitor is a transparent electrode. Therefore, the storage capacitor can transmit light, the light-transmitting area of the pixel unit is large, and the aperture ratio of the display substrate is high.
[0176] In this embodiment, a single patterning process may include: photoresist coating, exposure, development, etching, and photoresist stripping. Therefore, processing a material layer (e.g., semiconductor material layer X) to obtain a corresponding structure through a single patterning process may include: first, coating a layer of photoresist on the material layer (e.g., semiconductor material layer X) to form a photoresist layer; then, exposing the photoresist layer using a mask to form fully exposed and unexposed areas; next, processing the exposed photoresist layer through a development process to completely remove the photoresist in the fully exposed areas while retaining all the photoresist in the unexposed areas; then, etching the area corresponding to the fully exposed area on the material layer (e.g., semiconductor material layer X) through an etching process; and finally, stripping the photoresist in the unexposed areas, resulting in a corresponding structure (e.g., active layer O4 and semiconductor electrode T) formed in the area corresponding to the unexposed area on the material layer (e.g., semiconductor material layer X). As is easily understood, the embodiments of this application use positive photoresist as an example to illustrate the primary patterning process. The photoresist used in the primary patterning process can be negative photoresist, which will not be elaborated further in the embodiments of this application.
[0177] The order of steps in the manufacturing method of the display substrate provided in this application can be adjusted appropriately, and the steps can also be added or removed as appropriate. Any variations that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application, and therefore will not be elaborated further.
[0178] Based on the same inventive concept, this application also provides a display device, which includes the display substrate provided in the above embodiments. The display device can be an electroluminescent display device and can be a flexible display device, such as an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QLED) display device. This display device can be any product or component with display functionality, such as electronic paper, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, or wearable devices.
[0179] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A display substrate, characterized by, The display substrate includes: A substrate and a pixel unit located on the substrate, the pixel unit including a storage capacitor, the storage capacitor having a first electrode and a second electrode distributed opposite to each other, the electrode of the storage capacitor being a transparent electrode; The pixel unit further includes: a light-shielding layer, an active layer, a source-drain pattern, and a passivation layer. The light-shielding layer is located between the substrate and the active layer. The orthographic projection of the active layer on the substrate is located within the orthographic projection of the light-shielding layer on the substrate. The passivation layer is located on the side of the source-drain pattern away from the substrate. Both the light-shielding layer and the source / drain pattern include superimposed transparent conductive films and light-shielding conductive films; the transparent conductive film in the light-shielding layer is close to the substrate and in direct contact with the substrate; an insulating layer is provided between the light-shielding layer and the source / drain pattern; the transparent conductive film in the source / drain pattern is close to the substrate and in direct contact with the insulating layer away from the substrate. The first electrode plate includes a first sub-electrode plate and a second sub-electrode plate, both of which include a transparent conductive film. The transparent conductive film of the first sub-electrode plate is in direct contact with the insulating layer and is distributed in the same layer as the transparent conductive film in the light-shielding layer. In the direction perpendicular to the substrate, the thickness of the light-shielding layer is greater than the thickness of the first sub-electrode plate. The transparent conductive film of the second sub-electrode plate is distributed in the same layer as the transparent conductive film in the source-drain pattern and is in direct contact with the passivation layer. The first sub-electrode and the light-shielding layer are formed using a first grayscale mask through a single patterning process; the second sub-electrode and the source / drain patterns are formed using a second grayscale mask through a single patterning process.
2. The display substrate according to claim 1, characterized in that, In a direction perpendicular to the substrate, the thickness of the source-drain pattern is greater than the thickness of the second sub-plate.
3. The display substrate according to claim 1, characterized in that, The orthogonal projection of the transparent conductive film in the light-shielding layer onto the substrate covers the orthogonal projection of the light-shielding conductive film in the light-shielding layer onto the substrate.
4. The display substrate of claim 1, wherein, The second electrode plate is disposed on the same layer as the active layer. 5.The display substrate of claim 2, wherein, The pixel unit further includes: a pixel electrode located on the side of the passivation layer away from the substrate; the passivation layer has a pixel via, the pixel electrode is electrically connected to the source-drain pattern through the pixel via, and the orthographic projection of the pixel via on the substrate overlaps with the orthographic projection of the source-drain pattern on the substrate. 6.The display substrate of claim 2, wherein, The insulating layer has a connection hole, the second sub-electrode is electrically connected to the first sub-electrode through the connection hole, and there is a gap between the second sub-electrode and the source-drain pattern.
7. The display substrate according to claim 2, characterized in that, The pixel unit further includes: a buffer layer, a gate insulating layer, a gate, and an interlayer dielectric layer. The buffer layer is located between the light-shielding layer and the active layer. The active layer, the gate insulating layer, the gate, the interlayer dielectric layer, and the source-drain pattern constitute a thin-film transistor. The insulating layer between the light-shielding layer and the source-drain pattern includes the buffer layer and the interlayer dielectric layer. 8.The display substrate of claim 7, wherein, The first sub-electrode is in direct contact with the buffer layer; the second sub-electrode is in direct contact with the side of the interlayer dielectric layer away from the substrate.
9. The display substrate according to claim 7, characterized in that, The active layer, the gate insulating layer, the gate electrode, the interlayer dielectric layer, and the source / drain patterns are distributed along a direction away from the substrate. The source / drain patterns include a source electrode and a drain electrode. The orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate electrode on the substrate. The interlayer dielectric layer has source vias and drain vias. The source electrode contacts the active layer through the source vias, and the drain electrode contacts the active layer through the drain vias. The pixel unit further includes: a pixel electrode located on the side of the passivation layer away from the substrate; The passivation layer has pixel vias, and the pixel electrode is electrically connected to the drain electrode through the pixel vias.
10. A display device, characterized by comprising: The display device includes: the display substrate according to any one of claims 1 to 9.