Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate, a channel is formed in the substrate; forming a gate conductive layer, the gate conductive layer covers part of the channel; forming a semiconductor doped layer, the semiconductor doped layer fills the channel and covers the gate conductive layer, and the doping concentration of one side of the semiconductor doped layer close to the top surface of the gate conductive layer is different from the doping concentration of one side of the semiconductor doped layer away from the top surface of the gate conductive layer. In the present disclosure, the work function difference between the gate conductive layer and the channel of the semiconductor structure is large, the work function difference between the semiconductor doped material in the semiconductor doped layer and the channel is small, the threshold voltage of the semiconductor structure close to the bottom of the channel is large, and the threshold voltage close to the top surface of the substrate is small, which can avoid the occurrence of gate-induced drain leakage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the development of Dynamic Random Access Memory (DRAM), in order to improve the performance of semiconductor devices, Recess Channel Access Transistor (RCAT) is usually applied to DRAM to reduce the gate channel length of the transistor and improve the integration density of DRAM.

[0003] However, recessed channel array transistors are prone to generating gate-induced drain leakage current (GIDL), which affects the reliability of dynamic random access memory. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0006] The first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0007] A substrate is provided, wherein channels are formed within the substrate;

[0008] A gate conductive layer is formed, the gate conductive layer covering a portion of the channel;

[0009] A semiconductor doped layer is formed, which fills the channel and covers the gate conductive layer. The doping concentration of the semiconductor doped layer on the side near the top surface of the gate conductive layer is different from the doping concentration on the side of the semiconductor doped layer away from the top surface of the gate conductive layer.

[0010] According to some embodiments of this disclosure, forming the semiconductor doped layer includes:

[0011] A first semiconductor doped layer is formed, which covers the top surface of the gate conductive layer and the top surface of the first semiconductor doped layer is lower than the top surface of the substrate;

[0012] A second semiconductor doped layer is formed, which covers the top surface of the first semiconductor doped layer;

[0013] The doping concentration of the second semiconductor doped layer is different from that of the first semiconductor doped layer.

[0014] According to some embodiments of this disclosure, the second semiconductor doped layer and the first semiconductor doped layer have the same conductivity type.

[0015] According to some embodiments of this disclosure, forming the first semiconductor doped layer includes:

[0016] A first semiconductor material is deposited, and the first semiconductor material is doped for the first time to form a first doped region, the first doped region covering the top surface of the gate conductive layer;

[0017] The first semiconductor material is doped a second time to form a second doped region, and the second doped region covers the top surface of the first doped region.

[0018] The doping concentrations of the second doped region and the first doped region are different.

[0019] According to some embodiments of this disclosure, forming the second semiconductor doped layer includes:

[0020] A second semiconductor material is deposited, and the second semiconductor material is first doped to form a third doped region, which covers the top surface of the first semiconductor doped layer.

[0021] The second semiconductor material is doped a second time to form a fourth doped region, which covers the top surface of the third doped region.

[0022] The fourth doping region and the third doping region have different doping concentrations.

[0023] According to some embodiments of this disclosure, the doping concentration of the second semiconductor doped layer is greater than the doping concentration of the first semiconductor doped layer.

[0024] According to some embodiments of this disclosure, forming the gate conductive layer includes:

[0025] An initial gate conductive layer is filled within the channel;

[0026] The initial gate conductive layer is etched back, leaving a portion of the initial gate conductive layer with a height not less than one-third of the channel depth to form the gate conductive layer.

[0027] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0028] The substrate includes channels;

[0029] A gate conductive layer that covers a portion of the channel;

[0030] A semiconductor doped layer fills the channel and covers the gate conductive layer, wherein the doping concentration of the semiconductor doped layer on the side near the top surface of the gate conductive layer is different from the doping concentration on the side of the semiconductor doped layer away from the top surface of the gate conductive layer.

[0031] According to some embodiments of this disclosure, in a direction perpendicular to the substrate, the gate conductive layer has a first height between the bottom of the gate conductive layer and the top of the semiconductor doped layer, and the gate conductive layer has a second height, the second height being not less than one-third of the first height.

[0032] According to some embodiments of this disclosure, the semiconductor doped layer includes:

[0033] A first semiconductor doped layer covers the top surface of the gate conductive layer, and the top surface of the first semiconductor doped layer is lower than the top surface of the substrate;

[0034] A second semiconductor doped layer, wherein the second semiconductor doped layer covers the top surface of the first semiconductor doped layer;

[0035] The doping concentration of the second semiconductor doped layer is different from that of the first semiconductor doped layer.

[0036] According to some embodiments of this disclosure, the first semiconductor doped layer includes a first dopant, and the second semiconductor doped layer includes a second dopant, wherein the first dopant and the second dopant have the same conductivity type.

[0037] According to some embodiments of this disclosure, the doping concentration of the first dopant in the first semiconductor doped layer gradually changes in a direction perpendicular to the substrate.

[0038] According to some embodiments of this disclosure, the doping concentration of the second dopant in the second semiconductor doped layer gradually changes in a direction perpendicular to the substrate.

[0039] According to some embodiments of this disclosure, in a direction perpendicular to the substrate, the first semiconductor doped layer has a third height, the third height being no greater than one-third of the first height, and the second semiconductor doped layer has a fourth height, the fourth height being no greater than one-third of the first height.

[0040] According to some embodiments of this disclosure, the doping concentration of the first semiconductor doped layer is lower than that of the second semiconductor doped layer.

[0041] In the semiconductor structure fabrication method and semiconductor structure provided in this disclosure, the work function of the gate conductive layer and the channel of the semiconductor structure differs greatly, while the work function of the semiconductor doping material in the semiconductor doping layer differs little from that of the channel. The threshold voltage near the bottom of the channel is large, while the threshold voltage near the top surface of the substrate is small, which can avoid gate-induced drain leakage.

[0042] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects will become clear. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art from these drawings without inventive effort.

[0044] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0045] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure, according to an exemplary embodiment, of forming a semiconductor doped layer.

[0046] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0047] Figure 4 This is a schematic diagram of a substrate provided in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0048] Figure 5 This is a schematic diagram illustrating the formation of an initial gate conductive layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0049] Figure 6 This is a schematic diagram illustrating the formation of a gate conductive layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0050] Figure 7 This is a schematic diagram illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0051] Figure 8 This is a schematic diagram illustrating the formation of a first semiconductor doped layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0052] Figure 9 This is a schematic diagram illustrating the formation of a second semiconductor doped layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0053] Figure 10 This is a schematic diagram illustrating the formation of a first semiconductor doped layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0054] Figure 11 This is a schematic diagram of a semiconductor structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0055] Figure 12 This is a top view of a substrate provided in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0056] Figure 13 yes Figure 12 A cross-sectional view along plane AA.

[0057] Figure 14 yes Figure 12 A cross-sectional view along plane BB.

[0058] Figure 15 This is a schematic cross-sectional view of plane AA in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0059] Figure 16 This is a schematic cross-sectional view of the BB plane in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0060] Figure 17 This is a schematic cross-sectional view of the AA plane of a semiconductor structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0061] Figure 18 This is a schematic cross-sectional view of the BB plane of a semiconductor structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0062] Figure 19 This is a schematic cross-sectional view of the AA plane of a semiconductor structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0063] Figure 20 This is a schematic cross-sectional view of the BB plane of a semiconductor structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0064] Figure label:

[0065] 100, Substrate; 110, Active region; 131, Channel; 200, Gate oxide layer; 301, Initial gate conductive layer; 310, Gate conductive layer; 320, Semiconductor doped layer; 321, First semiconductor doped layer; 3211, First doped region; 3212, Second doped region; 322, Second semiconductor doped layer; 3221, Third doped region; 3222, Fourth doped region;

[0066] 500, Substrate; 510, Active region; 520, Shallow trench isolation region; 530, Word line channel; 531, Gate channel; 532, Conductive channel; 600, Gate oxide layer; 700, Word line structure; 700a, First gate; 700b, Second gate; 710, Gate conductive layer; 710a, Conductive layer of the first gate; 710b, Conductive layer of the second gate; 720, Semiconductor doped layer; 720a, Semiconductor doped layer of the first gate; 720b, Semiconductor doped layer of the second gate; 721, First semiconductor doped layer; 7211, First doped region; 7212, Second doped region; 722, Second semiconductor doped layer; 7221, Third doped region; 7222, Fourth doped region. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0068] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 1 As shown, Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 4-11 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 4-11 The methods for fabricating semiconductor structures are introduced.

[0069] This embodiment does not limit the semiconductor structure. The following description uses a recessed channel transistor (hereinafter referred to as a transistor) as an example, but this embodiment is not limited to this; the semiconductor structure in this embodiment can also be other structures. It should be understood that the semiconductor structure formed in this embodiment does not constitute a complete transistor; this embodiment only describes the formation process of the gate electrode of the transistor.

[0070] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0071] S10: Provides a substrate with channels formed within it.

[0072] like Figure 4 As shown, the substrate 100 includes an active region 110, which can be a P-type active region or an N-type active region. The material of the active region 110 includes semiconductor materials; for example, the material of the active region 110 may include one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. A channel 131 is formed in the active region 110; in this embodiment, the formed channel 131 is a gate channel.

[0073] like Figure 4 As shown, the substrate 100 also includes a gate oxide layer 200, and the channel 131 is surrounded by the gate oxide layer 200. The gate oxide layer 200 is made of silicon oxide, for example, silicon dioxide.

[0074] In some embodiments, providing a substrate 100 includes: providing an initial substrate, etching the initial substrate to form a gate trench, forming a gate oxide layer 200 in the gate trench, the gate oxide layer 200 covering the inner surface of the gate trench, and the gate oxide layer 200 forming a channel 131 in the gate trench.

[0075] S20: Form a gate conductive layer, which covers part of the channel.

[0076] like Figure 6 As shown, refer to Figure 4 The gate conductive layer 310 is located at the bottom of the channel 131, filling a portion of the channel 131 and covering a portion of the gate oxide layer 200. The material of the gate conductive layer 310 may include a metal nitride, such as titanium nitride or indium nitride. In this embodiment, the material of the gate conductive layer 310 includes titanium nitride.

[0077] In this embodiment, forming the gate conductive layer 310 includes:

[0078] S21: Fill the channel with the initial gate conductive layer.

[0079] like Figure 5 As shown, refer to Figure 4 Atomic layer deposition (ALD) or chemical vapor deposition (CVD) can be used to deposit gate conductive material. The gate conductive material fills the channel 131 and covers the top surface of the substrate 100 to form the initial gate conductive layer 301.

[0080] S22: Etch back the initial gate conductive layer, retaining an initial gate conductive layer with a height not less than one-third of the channel depth to form the gate conductive layer.

[0081] like Figure 6 As shown, refer to Figure 5 A gate conductive layer 310 is formed by etching back a portion of the initial gate conductive layer 301. In this embodiment, the height of the formed gate conductive layer 310 is greater than one-third of the depth of the channel 131.

[0082] S30: Form a semiconductor doped layer. The semiconductor doped layer fills the channel and covers the gate conductive layer. The doping concentration of the semiconductor doped layer on the side near the top surface of the gate conductive layer is different from the doping concentration on the side of the semiconductor doped layer away from the top surface of the gate conductive layer.

[0083] like Figure 7 As shown, a semiconductor doped layer 320 can be formed by in-situ doping of semiconductor materials using a low-pressure chemical vapor deposition (LPCVD) process, or by depositing undoped semiconductor materials to fill the channel 131 to form a semiconductor material layer. Then, doped impurities are injected into the semiconductor material layer through a thermal diffusion process or an ion implantation process to form the semiconductor doped layer 320.

[0084] The threshold voltage (TV) of a transistor is determined by the difference between the work function (WF) of the gate electrode and the gate channel. In the semiconductor structure formed in this embodiment, the gate electrode includes a gate conductive layer disposed at the bottom of the gate channel and a semiconductor doped layer covering the top surface of the gate conductive layer. The work function of the metal nitride in the gate conductive layer differs significantly from that of the gate channel, while the work function of the semiconductor doped layer and the material forming the active region of the gate channel differs less. That is, the threshold voltage of the gate electrode is higher near the bottom of the gate channel and lower near the top surface of the substrate. A higher threshold voltage near the bottom of the gate channel reduces charge leakage from the transistor to adjacent transistors, while a lower threshold voltage near the top surface of the substrate results in a lower voltage at the gate-drain overlap interface, preventing gate-induced drain leakage at the gate-drain overlap interface.

[0085] According to an exemplary embodiment of this disclosure, this embodiment is a further explanation of step S40 in the above embodiment.

[0086] like Figure 2 As shown, forming a semiconductor doped layer includes:

[0087] S31: Form a first semiconductor doped layer, the first semiconductor doped layer covers the top surface of the gate conductive layer, and the top surface of the first semiconductor doped layer is lower than the top surface of the substrate.

[0088] like Figure 8 As mentioned above, refer to Figure 6 The process of forming the first semiconductor doped layer 321 includes depositing a first semiconductor material to fill the channel 131, etching back the first semiconductor material located in the channel 131 to a depth below the top surface of the substrate 100 by etching back, and implanting dopants into the retained first semiconductor material by ion implantation process to form the first semiconductor doped layer 321.

[0089] In some embodiments, forming the first semiconductor doped layer includes:

[0090] S31a: Deposit a first semiconductor material, perform a first doping on the first semiconductor material to form a first doped region, and the first doped region covers the top surface of the gate conductive layer.

[0091] The first doping can be performed on an undoped first semiconductor material by ion implantation.

[0092] S31b: The first semiconductor material is doped a second time to form a second doped region, which covers the top surface of the first doped region.

[0093] The doping concentrations of the second doped region 3212 and the first doped region 3211 are different.

[0094] A second doping can be performed on a first-doped semiconductor material using ion implantation, with the implantation depth of the second doping being less than that of the first doping. For example... Figure 10 As shown, the region below the second doping depth in the first semiconductor doped layer 321 is the first doped region 3211, and the region within the second doping depth is the second doped region 3212. The doping concentration of the second doped region 3212 is greater than that of the first doped region 3211.

[0095] In some embodiments, when depositing the first semiconductor material, the first semiconductor material may be doped only once. The first semiconductor material is doped simultaneously with deposition, and the doping concentration gradually changes, forming a first semiconductor doped layer 321. Along a direction perpendicular to the substrate 100, the concentration of the first semiconductor doped layer 321 gradually changes.

[0096] S32: Form a second semiconductor doped layer, which covers the top surface of the first semiconductor doped layer.

[0097] The doping concentration of the second semiconductor doped layer is different from that of the first semiconductor doped layer. For example, the doping concentration of the second semiconductor doped layer 322 can be greater than or less than the doping concentration of the first semiconductor doped layer 321. In this embodiment, the doping concentration of the second semiconductor doped layer 322 is greater than that of the first semiconductor doped layer 321.

[0098] like Figure 9 As shown, refer to Figure 8 The operation of forming the second semiconductor doped layer 322 includes: placing the semiconductor structure in the reaction chamber, providing the reaction source gas, doping gas and carrier gas into the reaction chamber, using low-pressure chemical vapor deposition of semiconductor doping material, and filling the channel 131 with semiconductor doping material to form the second semiconductor doped layer 322.

[0099] For example, the second semiconductor doped layer 322 may include a silicon- or germanium-containing semiconductor material. In this example, one or more of silicon source gas or germanium source gas may be used as the reaction source gas, one or more of phosphine (PH3) or hydrogen arsenide (AsH3) may be used as the doping gas, and hydrogen (H2) may be used as the carrier gas. An N-type doped semiconductor material is deposited using a low-pressure chemical vapor deposition process, and the N-type doped semiconductor material fills the channel 131 to form the second semiconductor doped layer 322.

[0100] In some embodiments, forming the second semiconductor doped layer includes:

[0101] S32a: Deposit a second semiconductor material, perform a first doping on the second semiconductor material to form a third doped region, and the third doped region covers the top surface of the first semiconductor doped layer.

[0102] S32b: The second semiconductor material is doped a second time to form a fourth doped region, which covers the top surface of the third doped region.

[0103] The fourth doping region has a different doping concentration than the third doping region.

[0104] like Figure 11 As shown, refer to Figure 10 The third doped region 3331 and the fourth doped region 3222 form the second doped layer 322.

[0105] In this embodiment, the second semiconductor doped layer 322 and the first semiconductor doped layer 321 have the same conductivity type. If the first semiconductor doped layer 321 has N-type doping, then the second semiconductor doped layer 322 also has N-type doping. If the first semiconductor doped layer 321 has P-type doping, then the second semiconductor doped layer 322 also has P-type doping.

[0106] The conductivity type of the first semiconductor doped layer 321 and the second semiconductor doped layer 322 is set according to the active region 110. If the active region is a P-type active region, the conductivity type of the first semiconductor doped layer 321 and the second semiconductor doped layer 322 is set to N-type doping. If the active region 110 is an N-type active region, the conductivity type of the first semiconductor doped layer 321 and the second semiconductor doped layer 322 is set to P-type doping.

[0107] The work function of a semiconductor material can be altered by doping with ions. The work function is equal to the difference between the vacuum level and the Fermi level of the semiconductor material. The Fermi level is related to the carrier density in the semiconductor material, which is affected by doping impurities and doping concentration. Therefore, in this embodiment, the first and second semiconductor doped layers have different doping concentrations, resulting in different work functions. By modulating the work function of the semiconductor material, a segmented varying electric field is formed in the gate channel, effectively preventing breakdown and device failure caused by excessive electric field strength in certain parts of the gate channel.

[0108] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 3 As shown, Figure 3 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 12-20 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 12-20 The methods for fabricating semiconductor structures are introduced.

[0109] This embodiment does not limit the semiconductor structure. The following description will take a dynamic random access memory as an example of the semiconductor structure. However, this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures.

[0110] like Figure 3 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0111] Step S100: Provide a substrate, in which word lines are formed.

[0112] Figure 12A top view of base 500 is shown. Figure 13 yes Figure 12 A schematic cross-sectional view of the base along the AA direction. Figure 14 yes Figure 12 A schematic cross-sectional view of the substrate along the BB direction. In this embodiment, the AA direction is the extension direction of the word channel, and the BB direction is the extension direction of the active region.

[0113] like Figure 12 , Figure 13 , Figure 14 As shown, the substrate 500 includes an active region 510 and a shallow trench isolation region 520. Multiple active regions 510 in the substrate 500 are independently disposed, and the shallow trench isolation region 520 separates the multiple active regions 510. The active regions 510 can be P-type active regions or N-type active regions, and the material of the active regions 510 includes semiconductor materials. In this embodiment, the material of the active regions 510 includes a P-type doped semiconductor material. The material of the shallow trench isolation region 520 may include silicon oxide.

[0114] like Figure 12 As shown, a plurality of parallel word line channels 530 are formed within the substrate 500. The word line channels 530 pass through the substrate 500, exposing a portion of the active region 510 and a portion of the shallow trench isolation region 520. Each active region 510 intersects with one word line channel 530 at both ends. The word line channel 530 includes a gate channel 531 passing through the active region 510 and a conductive channel 532 passing through the shallow trench isolation region 520.

[0115] Step S200: Form a gate conductive layer, which covers part of the word line channel.

[0116] In this embodiment, the method for forming the gate conductive layer 710 in step S200 is the same as the implementation method of step S20 in the above embodiment.

[0117] like Figure 15 , Figure 16 , refer to Figure 13 , Figure 14 The gate conductive material can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The gate conductive material fills a portion of the word line channel 530 to form a gate conductive layer 710, which is located at the bottom of the word line channel 530. The material of the gate conductive layer 710 can include metal nitrides; for example, the material of the gate conductive layer 710 can include one or more of titanium nitride and indium nitride. In this embodiment, the material of the gate conductive layer 710 includes titanium nitride.

[0118] Step S300: Form a semiconductor doped layer. The semiconductor doped layer fills the word line channel and covers the gate conductive layer. The doping concentration of the semiconductor doped layer on the side near the top surface of the gate conductive layer is different from the doping concentration on the side of the semiconductor doped layer away from the top surface of the gate conductive layer.

[0119] The method for forming the semiconductor doped layer 720 in step S300 is the same as the implementation method of step S30 in the above embodiment.

[0120] like Figure 17 , Figure 18 , refer to Figure 15 , Figure 16 A semiconductor doped layer 720 can be formed by depositing doped semiconductor material, or by depositing undoped semiconductor material to fill word line channels 530 to form a semiconductor material layer. Then, doped impurities are injected into the semiconductor material layer through thermal diffusion or ion implantation processes to form the semiconductor doped layer 720.

[0121] The semiconductor doped layer 720 formed in step S300 has the same structure as the semiconductor doped layer 320 formed in step S60 of the above embodiment. For example... Figure 17 , Figure 18 As shown, the semiconductor doped layer 720 may include a first semiconductor doped layer 721 and a second semiconductor doped layer 722. The first semiconductor doped layer 721 covers the top surface of the gate conductive layer 710, and the doping concentration of the second semiconductor doped layer 722 is greater than that of the first semiconductor doped layer 721. The conductivity type of the first semiconductor doped layer 721 and the conductivity type of the second semiconductor doped layer 722 are the same.

[0122] In some embodiments, such as Figure 19 , Figure 20 As shown, along the direction from the gate conductive layer 710 to the second semiconductor doped layer 722, the first semiconductor doped layer 721 includes a first doped region 7211 and a second doped region 7212 disposed sequentially, and the doping concentrations of the first doped region 7211 and the second doped region 7212 are different.

[0123] In some embodiments, such as Figure 19 , Figure 20 As shown, along the direction from the first semiconductor doped layer 721 to the top surface of the substrate 500, the second semiconductor doped layer 722 includes a third doped region 7221 and a fourth doped region 7222 arranged sequentially, with the third doped region 7221 and the fourth doped region 7222 having different doping concentrations.

[0124] The semiconductor structure formed in this embodiment, such as Figure 17 , Figure 18As shown, the semiconductor doped layer 720 and the gate conductive layer 710 together form the word line structure 700. The word line structure 700 formed in this embodiment includes a first gate 700a passing through the active region 510 and a second gate 700b passing through the shallow trench isolation region 520. Along the extending direction of the word line structure 700, the first gate 700a and the second gate 700b are connected. Figure 17 As shown, refer to Figure 13 The first gate 700a is disposed in the gate channel 531, and the second gate 700b is disposed in the conductive channel 532.

[0125] like Figure 17 As shown, from the bottom of the word line trench 530 to the top surface of the substrate 100, the first gate 700a includes a gate conductive layer 710a and a semiconductor doped layer 720a disposed sequentially, and the second gate 700b includes a gate conductive layer 710b and a semiconductor doped layer 720b disposed sequentially.

[0126] The first gate 700a can serve as the gate electrode of a transistor (also referred to as a gate or control gate) to control the transistor's on and off states. In this embodiment, the first gate 700a serves as the gate electrode of a recessed channel transistor. The second gate 700b is disposed within the shallow trench isolation region 520 and adjacent to the active region 510, serving to connect the first gates 700a in different active regions 510 to form a recessed channel array transistor.

[0127] The semiconductor structure formed in this embodiment can form a recessed channel array transistor. The first gate, serving as the gate electrode of the transistor, includes a gate conductive layer and a semiconductor doped layer. The work function of the metal nitride in the gate conductive layer differs significantly from that of the gate channel, while the work function of the doped semiconductor material in the semiconductor doped layer differs less significantly from that of the gate channel. This results in a higher threshold voltage near the bottom of the gate channel and a lower threshold voltage near the top surface of the substrate, leading to a lower voltage at the gate-drain overlap interface and preventing gate-induced drain leakage at the gate-drain overlap interface.

[0128] Simultaneously, the conductive layer of the transistor's gate electrode generates a high threshold voltage in the bottom region of the gate channel, while the semiconductor doped layer generates a low threshold voltage above the gate electrode. This creates an electric field that varies from the bottom of the gate channel towards the gate-drain overlap interface of the transistor. As the transistor is repeatedly refreshed and read from, its gate electrode is continuously turned on and off, potentially leading to capacitive coupling interference between adjacent transistors. However, the semiconductor structure formed in this embodiment, with its recessed channel array transistor, utilizes the varying electric field created in the gate channel to alter the electron trajectory, causing leaked electrons to flow into the conductive layer of the first gate, reducing the impact of the hammer effect and improving device reliability.

[0129] According to an exemplary embodiment of this disclosure, this embodiment is a further explanation of step S100 in the above embodiment.

[0130] In this embodiment, a substrate is provided, with reference to Figure 13 , Figure 14 The method includes: providing a semiconductor substrate, which is a P-type substrate, and the semiconductor substrate is made of a semiconductor material. Exemplarily, the semiconductor substrate material may include one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. A mask pattern is formed on the top surface of the semiconductor substrate. A portion of the semiconductor substrate is removed according to the mask pattern to form shallow trenches. The shallow trenches separate the retained portion of the semiconductor substrate into independently configured active regions 510. A low-k dielectric material is deposited to fill the shallow trenches, forming a shallow trench isolation structure 520. In this embodiment, the low-k dielectric material is silicon oxide.

[0131] A hard mask is formed, which covers the top surface of the active area 510 and the shallow trench isolation structure 520. The hard mask is patterned using self-aligned double patterning (SADP) to form a word line pattern. Based on the word line pattern, a dry etching process or a wet etching process is used to remove part of the active area 510 and part of the shallow trench isolation area 520 to form word line trenches.

[0132] Reference Figure 13 , Figure 14 When removing part of the active region 510 and part of the shallow trench isolation region 520, the etching selectivity ratio of the active region 510 and the shallow trench isolation region 520 is controlled by the etching process to ensure that the etching rate of the shallow trench isolation region 520 is greater than the etching rate of the active region 510. As a result, the depth of the word line trench in the shallow trench isolation region 520 is greater than the depth in the active region 510. Along the extension direction of the word line trench, the cross-section of the word line trench is an undulating, concave-convex shape.

[0133] A gate oxide layer is formed, which covers the word line trenches.

[0134] Reference Figure 13 , Figure 14 The gate oxide layer 600 can be formed by depositing a gate oxide material using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The gate oxide layer 600 covers the word line trenches and forms word line trenches 530 within the word line trenches. The material of the gate oxide layer 600 is silicon oxide; in this embodiment, the material of the gate oxide layer 600 is silicon dioxide.

[0135] In the word line structure formed in the word line channel of this embodiment, the height of the second gate is greater than the height of the first gate, and the second gate is disposed between two adjacent first gates to isolate adjacent first gates. By increasing the isolation height of the second gate, the isolation effect of the second gate is increased, the adjacent interference of transistors is reduced, current leakage from transistors to adjacent transistors is avoided, and the row hammer effect is further reduced.

[0136] According to an exemplary embodiment of this disclosure, this embodiment provides a semiconductor structure, such as... Figure 7 As shown, refer to Figure 4 The structure includes: a substrate 100, a channel 131 disposed in the substrate 100, a gate conductive layer 310, and a semiconductor doped layer 320. The gate conductive layer 310 is disposed in the channel 131 and covers a portion of the channel 131. The semiconductor doped layer 320 covers the top surface of the gate conductive layer 310 and fills the remaining portion of the channel 131 not filled by the gate conductive layer 310. The height of the gate conductive layer 310 is greater than one-third of the channel depth. The semiconductor structure also includes a gate oxide layer 200, which is disposed between the gate conductive layer 310 and the channel 131, and between the semiconductor doped layer 320 and the channel 131.

[0137] In this embodiment, the doping concentration of the semiconductor doped layer 320 on the side near the top surface of the gate conductive layer 310 is different from the doping concentration of the semiconductor doped layer 320 on the side away from the top surface of the gate conductive layer 310.

[0138] In this embodiment of the semiconductor structure, the gate conductive layer 310 forms a high threshold voltage at the bottom of the channel 131, and the semiconductor doped layer 320 forms a low threshold voltage in the channel 131 above the gate conductive layer 310. The portion of the channel 131 covered by the gate conductive layer 310 serves as the main channel, and the threshold voltage between the main channel and the top surface of the substrate 100 is calculated. This results in a low voltage at the gate-drain overlap interface of the transistor formed by the semiconductor structure of this embodiment, thus preventing gate-induced drain leakage at the gate-drain overlap interface of the transistor.

[0139] According to an exemplary embodiment, most of the semiconductor structure in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that, in the direction perpendicular to the substrate 100, there is a first height between the bottom of the gate conductive layer 310 and the top of the semiconductor doped layer 320, and the gate conductive layer 310 has a second height, the second height being not less than one-third of the first height.

[0140] According to an exemplary embodiment, most of the semiconductor structure in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that, Figure 9As shown, the semiconductor doped layer 320 includes a first semiconductor doped layer 321 covering the top surface of the gate conductive layer 310, the top surface of the first semiconductor doped layer 321 being lower than the top surface of the substrate 100. The semiconductor doped layer 320 also includes a second semiconductor doped layer 322 covering the top surface of the first semiconductor doped layer 321, the doping concentration of the second semiconductor doped layer 322 being different from the doping concentration of the first semiconductor doped layer 321.

[0141] In some embodiments, the doping concentration of the first semiconductor doped layer 321 is lower than the doping concentration of the second semiconductor doped layer 322.

[0142] like Figure 9 As shown, in a direction perpendicular to the substrate 100, the first semiconductor doped layer 321 has a third height, which is no greater than one-third of the first height, and the second semiconductor doped layer 322 has a fourth height, which is no greater than one-third of the first height.

[0143] In this embodiment, the threshold voltages formed in the channel by the gate conductive layer 310, the first semiconductor doped layer 321, and the second semiconductor doped layer 322 are different. An electric field that varies from the bottom of the channel 131 to the top surface of the substrate 100 is formed in the semiconductor structure. The changing electric field can change the trajectory of electrons, causing leaked electrons to flow into the gate conductive layer, reducing the impact of the hammer effect and improving the reliability of the device.

[0144] According to an exemplary embodiment, most of the semiconductor structure in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that the doping concentration of the first dopant in the first semiconductor doped layer 321 gradually changes in the direction perpendicular to the substrate 100.

[0145] In the direction perpendicular to the substrate 100, the doping concentration of the second dopant in the second semiconductor doped layer 322 gradually changes.

[0146] For example, the doping concentration of the first semiconductor doped layer 321 on the side near the top surface of the gate conductive layer 310 is 10. 13 atoms / cm 2 The doping concentration of the side of the first semiconductor doped layer 321 away from the top surface of the gate conductive layer 310 is 1. 14 atoms / cm 2 .

[0147] In this embodiment, the doping concentration of the second semiconductor doped layer 322 on the side near the top surface of the first semiconductor doped layer 321 is 1. 14 atoms / cm 2 The doping concentration of the side of the second semiconductor doped layer 322 away from the top surface of the first semiconductor doped layer 321 is 1.15 atoms / cm 2 .

[0148] In this embodiment, the semiconductor structure forms an electric field in the channel 131 from the bottom of the channel 131 to the top surface of the substrate 100 where the threshold voltage gradually decreases. The threshold voltage of the semiconductor structure at the top surface of the substrate 100 is the smallest, so the voltage at the gate-drain overlap interface of the transistor formed by the semiconductor structure in this embodiment is the smallest, which can avoid gate-induced drain leakage at the gate-drain overlap interface of the transistor.

[0149] According to an exemplary embodiment, most of the semiconductor structure in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that, Figure 11 As shown, in the direction perpendicular to the substrate 100, the first semiconductor doped layer 321 includes a first doped region 3211 and a second doped region 3212, and the second semiconductor doped layer 322 includes a third doped region 3212 and a fourth doped region 3213.

[0150] In this embodiment, the doping concentration of the first doped region 3212 is less than the doping concentration of the second doped region 332. For example, the doping concentration of the first doped region 3211 is 1. 13 atoms / cm 2 The doping concentration of the second doped region 3212 is 1. 14 atoms / cm 2 .

[0151] In this embodiment, the doping concentration of the second semiconductor doped layer 322 is 1. 15 atoms / cm 2 .

[0152] In this embodiment, the semiconductor structure forms a gradually decreasing threshold voltage in the channel 131 from the bottom of the channel 131 to the top surface of the substrate 100, which reduces the electric field around the semiconductor structure, reduces gate-induced drain leakage at the gate-drain overlap interface, and also reduces adjacent interference.

[0153] According to an exemplary embodiment of this disclosure, this embodiment provides a semiconductor structure, such as... Figure 17 , Figure 18 As shown, or as Figure 19 , Figure 20 As shown, refer to Figure 12The semiconductor structure includes: a substrate 500, a word line channel 530 disposed in the substrate 500, a gate oxide layer 600, a gate conductive layer 710, and a semiconductor doped layer 720. The gate oxide layer 600 covers the word line channel 530, the gate conductive layer 710 fills a portion of the word line channel 530, and the gate conductive layer 710 and the substrate 100 are separated by the gate oxide layer 600. The semiconductor doped layer 720 covers the top surface of the gate conductive layer 710 and fills the remaining portion of the word line channel 530 not filled by the gate conductive layer 710. The semiconductor doped layer 730 and the substrate 100 are separated by the gate oxide layer 600. The gate conductive layer 710 and the semiconductor doped layer 720 together form the word line structure 700. The doping concentration of the semiconductor doped layer 720 on the side closer to the top surface of the gate conductive layer 710 is different from the doping concentration on the side of the semiconductor doped layer 720 farther from the top surface of the gate conductive layer 710.

[0154] Reference Figure 13 , Figure 14 The substrate 500 includes an active region 510 and a shallow trench isolation region 520. A word line channel 530 passes through the substrate 100, exposing a portion of the active region 510 and a portion of the shallow trench isolation region 520. Each active region 510 intersects with a word line channel 530 at both ends. The word line channel 530 includes a gate channel 531 passing through the active region 510 and a conductive channel 532 passing through the shallow trench isolation region 520.

[0155] For example, 17. Figure 18 As shown, or as Figure 19 , Figure 20 As shown, the word line structure 700 includes a first gate 700a passing through the active region 510 and a second gate 700b passing through the shallow trench isolation region 520. Along the extension direction of the word line structure 700, the first gate 700a and the second gate 700b are arranged alternately in sequence. Specifically, from the bottom of the word line trench 530 to the top surface of the substrate 100, the first gate 700a includes a first gate conductive layer 710a and a first gate semiconductor doped layer 720a sequentially disposed, and the second gate 700b includes a second gate conductive layer 710b and a second gate semiconductor doped layer 720b sequentially disposed.

[0156] According to an exemplary embodiment, most of the semiconductor structure in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that, referring to... Figure 13 , Figure 14 The depth of the conductive channel 532 is greater than the depth of the gate channel 531. Along the extension direction of the word line channel 530, the cross-section of the word line channel 530 is a concave-convex shape with varying heights.

[0157] For example, 17. Figure 18 As shown, or as Figure 19, Figure 20 As shown, the bottom surface of the second gate 700b of the word line structure 700 is lower than the bottom surface of the first gate 700a. The second gate 700b has a better effect of isolating two adjacent first gates 700a, and has a better effect of reducing the interference between two adjacent first gates 700a, further reducing the row hammer effect.

[0158] The semiconductor structure fabrication method and semiconductor structure disclosed herein utilize the property that the work function of semiconductor materials can be changed, thereby reducing the voltage at the gate-drain overlap interface of the semiconductor structure and avoiding gate-induced drain leakage at the gate-drain overlap interface of the semiconductor structure.

[0159] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0160] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0161] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0162] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0163] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0164] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: A substrate is provided, wherein channels are formed within the substrate; A gate conductive layer is formed, the gate conductive layer covering a portion of the channel; A semiconductor doped layer is formed, which fills the channel and covers the gate conductive layer. The doping concentration of the semiconductor doped layer on the side near the top surface of the gate conductive layer is different from the doping concentration on the side of the semiconductor doped layer away from the top surface of the gate conductive layer. Forming the semiconductor doped layer includes: A first semiconductor doped layer is formed, which covers the top surface of the gate conductive layer and the top surface of the first semiconductor doped layer is lower than the top surface of the substrate; A second semiconductor doped layer is formed, which covers the top surface of the first semiconductor doped layer; The formation of the first semiconductor doped layer includes: A first semiconductor material is deposited, and the first semiconductor material is doped for the first time to form a first doped region, the first doped region covering the top surface of the gate conductive layer; The first semiconductor material is doped a second time to form a second doped region, and the second doped region covers the top surface of the first doped region. The doping concentrations of the second doped region and the first doped region are different. And / or, the formation of the second semiconductor doped layer includes: A second semiconductor material is deposited, and the second semiconductor material is first doped to form a third doped region, which covers the top surface of the first semiconductor doped layer. The second semiconductor material is doped a second time to form a fourth doped region, which covers the top surface of the third doped region. The fourth doping region and the third doping region have different doping concentrations.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The doping concentration of the second semiconductor doped layer is different from that of the first semiconductor doped layer.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The second semiconductor doped layer and the first semiconductor doped layer have the same conductivity type.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The doping concentration of the second semiconductor doped layer is greater than that of the first semiconductor doped layer.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of the gate conductive layer includes: An initial gate conductive layer is filled within the channel; The initial gate conductive layer is etched back, leaving a portion of the initial gate conductive layer with a height not less than one-third of the channel depth to form the gate conductive layer.

6. A semiconductor structure, characterized in that, The semiconductor structure includes: The substrate includes channels; A gate conductive layer that covers a portion of the channel; A semiconductor doped layer fills the channel and covers the gate conductive layer, wherein the doping concentration of the semiconductor doped layer on the side near the top surface of the gate conductive layer is different from the doping concentration on the side of the semiconductor doped layer away from the top surface of the gate conductive layer; The semiconductor doped layer includes: A first semiconductor doped layer covers the top surface of the gate conductive layer, the top surface of the first semiconductor doped layer is lower than the top surface of the substrate, and the first semiconductor doped layer includes a first dopant. A second semiconductor doped layer covers the top surface of the first semiconductor doped layer, and the second semiconductor doped layer includes a second dopant. In a direction perpendicular to the substrate, the doping concentration of the first dopant in the first semiconductor doped layer gradually changes, and / or, in a direction perpendicular to the substrate, the doping concentration of the second dopant in the second semiconductor doped layer gradually changes.

7. The semiconductor structure according to claim 6, characterized in that, In a direction perpendicular to the substrate, the gate conductive layer has a first height between the bottom of the gate conductive layer and the top of the semiconductor doped layer, and the gate conductive layer has a second height, the second height being not less than one-third of the first height.

8. The semiconductor structure according to claim 6, characterized in that, The doping concentration of the second semiconductor doped layer is different from that of the first semiconductor doped layer.

9. The semiconductor structure according to claim 6, characterized in that, The first dopant and the second dopant have the same conductivity type.

10. The semiconductor structure according to claim 7, characterized in that, In a direction perpendicular to the substrate, the first semiconductor doped layer has a third height, the third height being no greater than one-third of the first height, and the second semiconductor doped layer has a fourth height, the fourth height being no greater than one-third of the first height.

11. The semiconductor structure according to claim 6, characterized in that, The doping concentration of the first semiconductor doped layer is lower than that of the second semiconductor doped layer.

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