A PWM wave adaptive delay circuit with strong anti-interference capability

Abstract

The application discloses a PWM wave adaptive delay circuit with strong anti-interference capability, and belongs to the field of semiconductor integrated circuits, comprising a sampling circuit, a filter circuit, a comparator circuit and a logic control circuit. The sampling circuit samples a current signal and converts the current signal into a voltage signal; the filter circuit filters interference signals; the comparator circuit is used for comparing the filtered voltage signal with a set reference voltage; and the logic control circuit is used for logic operation of a delay voltage signal, a 3.5V voltage signal, a 2.5V voltage signal and a CLK voltage signal. The application realizes setting of upper and lower power tube conduction dead time on a driving module by using a simple and practical structure; the circuit is simple, has strong anti-interference capability, strong adaptability, makes the upper and lower power tube conduction dead time setting flexible and has a wide application range, and can be used for setting of upper and lower power tube conduction dead time on all driving modules of a half-bridge, an H-bridge and a three-phase full-bridge.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a PWM wave adaptive delay circuit with strong anti-interference capability. Background Technology

[0002] With the rapid development of power electronics technology and the advancement of semiconductor integration technology, various types of electronic products have become widely used in people's daily lives. In many power electronic equipment applications, a drive module, i.e., a PWM wave, is required to drive the upper and lower power transistors. This PWM wave needs strong anti-interference capability and strong adaptability, allowing for flexible setting of the dead time of the upper and lower power transistors. In particular, the detection circuit at the input terminal controlling the dead time of the upper and lower power transistors needs to have a wide detection range and high sensitivity. However, traditional dead time setting circuits are complex in structure, have weak anti-interference capability, and poor adaptability, thus reducing the speed and efficiency of the feedback loop. Summary of the Invention

[0003] The purpose of this invention is to provide a PWM wave adaptive delay circuit with strong anti-interference capability, so as to solve the problems of complex structure, high power consumption, weak anti-interference capability and low sensitivity of existing dead time setting circuits.

[0004] To address the aforementioned technical problems, this invention provides a PWM wave adaptive delay circuit with strong anti-interference capability, comprising:

[0005] The sampling circuit samples the current signal and converts it into a voltage signal.

[0006] The filtering circuit filters out interference signals;

[0007] A comparator circuit is used to compare the filtered voltage signal with the set reference voltage.

[0008] The logic control circuit performs logic operations on the delayed voltage signal, the 3.5V voltage signal, the 2.5V voltage signal, and the CLK voltage signal.

[0009] In one embodiment, the sampling circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an error amplifier;

[0010] The differential input A terminal is connected to the first terminal of the seventh resistor. The second terminal of the seventh resistor is connected to both the positive input terminal of the error amplifier and the first terminal of the fifth resistor. The second terminal of the fifth resistor is connected to a bias voltage of 0.5V.

[0011] The differential input B terminal is connected to the first terminal of the sixth resistor. The second terminal of the sixth resistor is connected to both the inverting input terminal of the error amplifier and the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the output terminal of the error amplifier.

[0012] In one embodiment, the filter circuit includes a third resistor and a first capacitor;

[0013] The output terminal of the error amplifier is connected to the first terminal of the third resistor; the second terminal of the third resistor is connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is grounded.

[0014] In one embodiment, the comparator circuit includes a first comparator, a second comparator, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first resistor, and a second resistor.

[0015] The second terminal of the third resistor is connected to the positive input terminal of the first comparator, the inverting input terminal of the first comparator is connected to the first terminal of the second resistor, the output terminal of the first comparator is connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is connected to the first terminal of the second resistor, the drain is connected to the drain of the first PMOS transistor, the drain of the first PMOS transistor is connected to its own gate, and the source is connected to the power supply VDD; the source of the second PMOS transistor is connected to the power supply VDD, and the gate is connected to the drain of the first NMOS transistor.

[0016] The second end of the third resistor is connected to the positive input of the second comparator, the negative input of the second comparator is connected to the first end of the first resistor, the output of the second comparator is connected to the gate of the second NMOS transistor, the source of the second NMOS transistor is connected to the first end of the first resistor, the drain is connected to the drain of the third PMOS transistor, the drain of the third PMOS transistor is connected to its own gate, and the source is connected to the power supply VDD; the source of the fourth PMOS transistor is connected to VDD, and the gate is connected to the drain of the second NMOS transistor.

[0017] The second terminals of both the first resistor and the second resistor are grounded.

[0018] In one embodiment, the logic control circuit includes a third comparator, a fourth comparator, a fifth comparator, a sixth comparator, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a second capacitor, a third capacitor, a first AND gate, and a second AND gate;

[0019] The drain of the second PMOS transistor is connected to the first terminal of the first inverter. The second terminal of the first inverter is connected to the inverting input of the third comparator. The non-inverting input of the third comparator is connected to a bias voltage of 3.5V. The output of the third comparator is connected to the gate of the third NMOS transistor. The drain of the third NMOS transistor is connected to a bias voltage VBIAS1. The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the third NMOS transistor is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded. The source of the fifth PMOS transistor is connected to the power supply VDD, the gate is connected to the gate of the third NMOS transistor, and the drain is connected to both the first terminal of the second capacitor and the fifth NMOS transistor. The positive input terminal of the comparator is connected to the first terminal of the fifth inverter, which is biased by 2.5V. The second terminal of the fifth inverter is connected to the inverting input terminal of the fifth comparator. The output terminal of the fifth comparator is connected to the first terminal of the first AND gate. The gate of the fourth NMOS transistor is connected to the second terminal of the first AND gate. The output terminal of the first AND gate is connected to the gate of the seventh NMOS transistor. The drain of the seventh NMOS transistor is connected to the power supply VCC, and the source is connected to the drain of the eighth NMOS transistor. The clock1 signal is connected to the first terminal of the second inverter. The second terminal of the second inverter is connected to the gate of the fourth NMOS transistor. The drain of the fourth NMOS transistor is connected to the source of the third NMOS transistor. The source of the fourth NMOS transistor is grounded.

[0020] The drain of the fourth PMOS transistor is connected to the first terminal of the third inverter. The positive input terminal of the fourth comparator is connected to a bias voltage of 3.5V. The output terminal of the fourth comparator is connected to the gate of the fifth NMOS transistor. The drain of the fifth NMOS transistor is connected to a bias voltage VBIAS2, and its source is connected to the drain of the sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to the first terminal of the third capacitor, and the second terminal of the third capacitor is grounded. The source of the sixth PMOS transistor is connected to the power supply VDD, its gate is connected to the gate of the fifth NMOS transistor, and its drain is connected to both the first terminal of the third capacitor and the positive input terminal of the sixth comparator. The first terminal of the sixth inverter... The first terminal is connected to a bias voltage of 2.5V. The second terminal is connected to the inverting input of the sixth comparator. The output of the sixth comparator is connected to the first terminal of the second AND gate. The gate of the sixth NMOS transistor is connected to the second terminal of the second AND gate. The output of the second AND gate is connected to the gate of the eighth NMOS transistor. The drain of the eighth NMOS transistor is connected to the source of the seventh NMOS transistor. The source of the eighth NMOS transistor is grounded. The clock2 signal is connected to the first terminal of the fourth inverter. The second terminal of the fourth inverter is connected to the gate of the sixth NMOS transistor. The drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor. The source of the sixth NMOS transistor is grounded.

[0021] This invention provides a PWM wave adaptive delay circuit with strong anti-interference capability, which has the following characteristics:

[0022] Beneficial effects:

[0023] (1) The circuit structure is simple and has strong self-adaptation capability. The dead time of the upper and lower power transistors can be flexibly set by adjusting the value of the external resistor.

[0024] (2) It has a wide range of applications and can be used to set the dead time of the upper and lower power transistors in all drive modules of half-bridge, H-bridge and three-phase full-bridge.

[0025] (3) The circuit as a whole has strong resistance to external interference and high sensitivity, and can detect voltages with very small errors. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a PWM wave adaptive delay circuit structure with strong anti-interference capability provided by the present invention. Detailed Implementation

[0027] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of the PWM wave adaptive delay circuit with strong anti-interference capability proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0028] This invention provides a PWM wave adaptive delay circuit with strong anti-interference capability, comprising a sampling circuit, a filtering circuit, a comparator circuit, and a logic control circuit. The sampling circuit samples the current signal and converts it into a voltage signal; the filtering circuit filters interference signals; the comparator circuit compares the filtered voltage signal with a set reference voltage; and the logic control circuit performs logical operations on the delayed voltage signal, the 3.5V voltage signal, the 2.5V voltage signal, and the CLK voltage signal.

[0029] The structure of the PWM wave adaptive delay circuit with strong anti-interference capability is as follows: Figure 1 As shown, it includes an error amplifier AMP, resistors R1 to R7, capacitors C1 to C3, comparators EA1 to EA6, inverters INV1 to INV6, PMOS transistors MP1 to MP6, NMOS transistors MN1 to MN8, and AND gates AND1 to AND2.

[0030] Please continue reading. Figure 1 Differential input A is connected to the first end of resistor R7. The second end of resistor R7 is connected to both the positive input of error amplifier AMP and the first end of resistor R5. The second end of resistor R5 is connected to a bias voltage of 0.5V. Differential input B is connected to the first end of resistor R6. The second end of resistor R6 is connected to both the inverting input of error amplifier AMP and the first end of resistor R4. The second end of resistor R4 is connected to the output of error amplifier AMP.

[0031] The output of the error amplifier AMP is connected to the first terminal of resistor R3; the second terminal of resistor R3 is connected to the first terminal of capacitor C1, and the second terminal of capacitor C1 is grounded.

[0032] The second terminal of resistor R3 is connected to the positive input terminal of comparator EA1, and the inverting input terminal of comparator EA1 is connected to the first terminal of resistor R2. The output terminal of comparator EA1 is connected to the gate of NMOS transistor MN1. The source of NMOS transistor MN1 is connected to the first terminal of resistor R2, and its drain is connected to the drain of PMOS transistor MP1. The drain of PMOS transistor MP1 is connected to its own gate, and its source is connected to the power supply VDD. The source of PMOS transistor MP2 is connected to the power supply VDD, and its gate is connected to the drain of NMOS transistor MN1. The drain is connected to the first terminal of inverter INV1. The second terminal of inverter INV1 is connected to the inverting input terminal of comparator EA3. The positive input terminal of comparator EA3 is connected to a bias voltage of 3.5V. The output terminal of comparator EA3 is connected to the gate of NMOS transistor MN3, and the drain of NMOS transistor MN3 is connected to a bias voltage VBIAS1. The source of NMOS transistor MN3 is connected to the drain of NMOS transistor MN4. The first terminal of capacitor C2 is connected to the ground; the second terminal of capacitor C2 is grounded; the source of PMOS transistor MP5 is connected to power supply VDD, the gate is connected to the gate of NMOS transistor MN3, and the drain is connected to both the first terminal of capacitor C2 and the positive input terminal of comparator EA5; the first terminal of inverter INV5 is connected to the bias voltage 2.5V, the second terminal is connected to the inverting input terminal of comparator EA5, and the output terminal of comparator EA5 is connected to the first terminal of AND gate AND1; the gate of NMOS transistor MN4 is connected to the second terminal of AND gate AND1, the output terminal of AND gate AND1 is connected to the gate of NMOS transistor MN7, the drain of NMOS transistor MN7 is connected to power supply VCC, and the source is connected to the drain of NMOS transistor MN8; the clock1 signal is connected to the first terminal of inverter INV2, the second terminal of inverter INV2 is connected to the gate of NMOS transistor MN4, the drain of NMOS transistor MN4 is connected to the source of NMOS transistor MN3, and the source of NMOS transistor MN4 is grounded.

[0033] The second terminal of resistor R3 is connected to the positive input of comparator EA2. The inverting input of comparator EA2 is connected to the first terminal of resistor R1. The output of comparator EA2 is connected to the gate of NMOS transistor MN2. The source of NMOS transistor MN2 is connected to the first terminal of resistor R1, and its drain is connected to the drain of PMOS transistor MP3. The drain of PMOS transistor MP3 is connected to its own gate, and its source is connected to the power supply VDD. The source of PMOS transistor MP4 is connected to VDD, its gate is connected to the drain of NMOS transistor MN2, and its drain is connected to the first terminal of inverter INV3. The positive input of comparator EA4 is connected to a bias voltage of 3.5V. The output of comparator EA4 is connected to the gate of NMOS transistor MN5. The drain of NMOS transistor MN5 is connected to a bias voltage VBIAS2, and its source is connected to the drain of NMOS transistor MN6. The drain of NMOS transistor MN5 is connected to the first terminal of capacitor C3, and the second terminal of capacitor C3... Grounded; the source of PMOS transistor MP6 is connected to power supply VDD, the gate is connected to the gate of NMOS transistor MN5, and the drain is connected to both the first terminal of capacitor C3 and the positive input terminal of comparator EA6; the first terminal of inverter INV6 is connected to bias voltage 2.5V, the second terminal is connected to the inverting input terminal of comparator EA6, the output terminal of comparator EA6 is connected to the first terminal of AND gate AND2, the gate of NMOS transistor MN6 is connected to the second terminal of AND gate AND2, the output terminal of AND gate AND2 is connected to the gate of NMOS transistor MN8, the drain of NMOS transistor MN8 is connected to the source of NMOS transistor MN7, and the source of NMOS transistor MN8 is grounded; the clock2 signal is connected to the first terminal of inverter INV4, the second terminal of inverter INV4 is connected to the gate of NMOS transistor MN6, the drain of NMOS transistor MN6 is connected to the source of NMOS transistor MN5, and the source of NMOS transistor MN6 is grounded.

[0034] The specific working principle of the PWM wave adaptive delay circuit with strong anti-interference capability of the present invention is as follows:

[0035] Resistors R4, R5, R6, R7, the error amplifier AMP, and a 0.5V bias voltage form a sampling circuit. This sampling circuit is a differential circuit, which can suppress common-mode amplification and differential-mode amplification, improving the circuit's anti-interference capability. The filter circuit consists of resistor R3 and capacitor C1. The desired frequency band signal is obtained through this filter circuit and serves as the positive input of comparators EA1 and EA2. In the comparator circuit, external resistors R2 and R1 set threshold voltages, which serve as the inverting inputs of comparators EA1 and EA2, respectively. When the positive input of the comparators (i.e., comparators EA1 and EA2) is greater than the inverting input, NMOS transistors MN1 and MN2 will be turned on respectively, making NMOS transistors MN1 and MN2... OS transistor MN2 is linearly turned on. When NMOS transistors MN1 and MN2 are turned on to ground, forming a path, PMOS transistors MP1 and MP3 are connected in a diode configuration and are turned on respectively. PMOS transistors MP2 and MP4, whose gate voltages are lower than their drain voltages, are also turned on simultaneously, forming a delay voltage. In the logic control circuit, this delay voltage is first compared with 3.5V. When the delay voltages DELAYA and DELAYB are less than 3.5V and clock1 / clock2 is 1, capacitors C2 / C3 are charged. Comparators EA5 / EA6 extract the portion of the capacitor voltage greater than 2.5V and AND it with clock1 / clock2 to obtain the delayed signal. The low level of this delayed signal is ANDed to ultimately output a low level, generating a delayed PWM wave that simultaneously turns off the external upper and lower power transistors (NMOS transistors MN7 and MN8). The dead time can be set.

[0036] Through example analysis, it can be found that the simple, efficient, and highly anti-interference PWM wave adaptive delay circuit of the present invention realizes the setting of the conduction dead time of the upper and lower power transistors of the drive module in a simple and practical structure; moreover, the circuit design is simple, with strong anti-interference ability and strong adaptive ability, making the setting of the conduction dead time of the upper and lower power transistors flexible and with a wide range of applications. It can be used to set the conduction dead time of the upper and lower power transistors of all drive modules of half-bridge, H-bridge, and three-phase full-bridge.

[0037] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A PWM wave adaptive delay circuit with strong anti-interference capability, characterized in that, include: The sampling circuit samples the current signal and converts it into a voltage signal. The filtering circuit filters the interference signal to obtain the filtered signal; A comparator circuit is used to compare the filtered voltage signal with the set reference voltage. The logic control circuit performs logical operations on the delayed voltage DELAYA, 3.5V voltage signal, 2.5V voltage signal and CLK voltage signal generated by the comparator circuit; The comparator circuit includes comparators EA1~EA2, PMOS transistors MP1~MP4, NMOS transistors MN1~MN2, and resistors R1~R2; The filtered signal is connected to the positive input terminal of EA1, the negative input terminal of EA1 is connected to the first terminal of R2, the output terminal of EA1 is connected to the gate of MN1, the source of MN1 is connected to the first terminal of R2, the drain of MN1 is connected to the drain of MP1, the drain of MP1 is connected to its own gate, and the source is connected to the power supply VDD; the source of MP2 is connected to the power supply VDD, and the gate is connected to the drain of MN1. The filtered signal is connected to the positive input terminal of EA2, the inverting input terminal of EA2 is connected to the first terminal of R1, the output terminal of EA2 is connected to the gate of MN2, the source of MN2 is connected to the first terminal of R1, the drain of MN2 is connected to the drain of MP3, the drain of MP3 is connected to its own gate, and the source is connected to the power supply VDD; the source of MP4 is connected to VDD, and the gate is connected to the drain of MN2; the second terminals of R1 and R2 are both grounded. The logic control circuit includes comparators EA3~EA6, inverters INV1~INV6, NMOS transistors MN3~MN8, PMOS transistors MP5~MP6, capacitors C2~C3, and AND gates AND1~AND2; The drain of MP2 is connected to the first terminal of INV1. The second terminal of INV1 is connected to the inverting input of EA3. The non-inverting input of EA3 is connected to the bias voltage of 3.5V. The output of EA3 is connected to the gate of MN3. The drain of MN3 is connected to the bias voltage VBIAS1. The source of MN3 is connected to the drain of MN4. The drain of MN3 is connected to the first terminal of C2. The second terminal of C2 is grounded. The source of MP5 is connected to the power supply VDD. The gate is connected to the gate of MN3. The drain is connected to both the first terminal of C2 and the non-inverting input of EA5. The first terminal of INV5 is connected to the bias voltage of 2.5V. The second terminal is connected to the inverting input of EA5. The output of EA5 is connected to the first terminal of AND1. The gate of MN4 is connected to the second terminal of AND1. The output of AND1 is connected to the gate of MN7. The drain of MN7 is connected to the power supply VCC. The source is connected to the drain of MN8. The clock1 signal is connected to the first terminal of INV2. The second terminal of INV2 is connected to the gate of MN4. The drain of MN4 is connected to the source of MN3. The source of MN4 is grounded. The drain of MP4 is connected to the first terminal of INV3. The positive input terminal of EA4 is connected to a bias voltage of 3.5V. The output terminal of EA4 is connected to the gate of MN5. The drain of MN5 is connected to a bias voltage VBIAS2, and its source is connected to the drain of MN6. The drain of MN5 is connected to the first terminal of C3, and the second terminal of C3 is grounded. The source of MP6 is connected to the power supply VDD, its gate is connected to the gate of MN5, and its drain is connected to both the first terminal of C3 and the positive input terminal of EA6. The first terminal of INV6 is connected to a bias voltage of 2.5V, and its second terminal is connected to the inverting input terminal of EA6. The output terminal of EA6 is connected to the first terminal of AND2. The gate of MN6 is connected to the second terminal of AND2. The output terminal of AND2 is connected to the gate of MN8. The drain of MN8 is connected to the source of MN7, and the source of MN8 is grounded. The clock2 signal is connected to the first terminal of INV4. The second terminal of INV4 is connected to the gate of MN6. The drain of MN6 is connected to the source of MN5, and the source of MN6 is grounded.

2. The PWM wave adaptive delay circuit with strong anti-interference capability as described in claim 1, characterized in that, The sampling circuit includes resistors R4~R7 and an error amplifier AMP; The differential input A terminal is connected to the first terminal of R7, the second terminal of R7 is connected to both the positive input terminal of AMP and the first terminal of R5, and the second terminal of R5 is connected to a bias voltage of 0.5V. The differential input B terminal is connected to the first terminal of R6, the second terminal of R6 is connected to both the inverting input terminal of AMP and the first terminal of R4, and the second terminal of R4 is connected to the output terminal of AMP.

3. The PWM wave adaptive delay circuit with strong anti-interference capability as described in claim 2, characterized in that, The filter circuit includes a resistor R3 and a capacitor C1; The output of the AMP is connected to the first terminal of R3; the second terminal of R3 is connected to the first terminal of C1, and the second terminal of C1 is grounded.

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