A method of manufacturing a NOR flash memory device

Abstract

The application provides a NOR flash device manufacturing method, which comprises the following steps: providing a substrate, wherein a gate structure is formed on the substrate; depositing an ONO layer and etching to form a first side wall, wherein the ONO layer comprises a thinned first oxide layer, a nitride layer and a thickened second oxide layer; performing source-drain ion implantation on a cell region; depositing a SiN layer and etching to form a second side wall; performing source-drain ion implantation on a peripheral region; depositing SAB and performing a photolithography etching process; performing a pre-cleaning treatment on the surface of the substrate; wet etching the nitride layer of the first side wall by using phosphoric acid to reduce the height and thickness of the first side wall; and depositing NiPt and TiN. The thinned first oxide layer, the nitride layer and the thickened second oxide layer are used as the first side wall, and the high-selectivity phosphoric acid wet etching is used to etch the side wall SiN before forming the metal silicide, so that the thickness and height of the side wall are thinned, the ILD deposition aspect ratio is reduced, the electrical properties of the storage cell region and the peripheral region are not affected, and the Nor Flash ILD filling performance is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically to a method for manufacturing a NOR flash memory device. Background Technology

[0002] NOR Flash (or non-flash memory) uses a two-spacer process. The first spacer is composed of an ONO (oxide-nitride-oxide) structure, which serves as the sidewall for ion implantation in the Cell region (memory cell region). The second spacer structure is SiN (silicon nitride), which serves as the sidewall for ion implantation in the Periphery region (peripheral region).

[0003] As the size of NOR flash decreases, the gate-to-gate (CG) space also decreases, making ILD (internal drainage layer) filling a major challenge. Currently, 55nm NOR flash already exhibits void issues in ILD filling, such as... Figure 1 As shown, the ILD filling is void. Therefore, it is proposed to adjust the thickness of the sidewall ONO structure to improve the ILD filling window in the Cell region. However, the reduction of the sidewall thickness changes the channel length and LDD region of the device, affecting the device reliability. Summary of the Invention

[0004] In view of this, the present invention provides a method for manufacturing a NOR flash memory device, which reduces the aspect ratio of the ILD deposition and improves the ILD fill window of the NOR flash memory device without changing the channel length of the Cell region and the peripheral region.

[0005] This invention provides a method for manufacturing a NOR flash memory device, the NOR flash memory device comprising a memory cell area and a peripheral area, comprising the following steps:

[0006] Step 1: Provide a substrate on which a gate structure is formed;

[0007] Step 2: Deposit an ONO layer and etch it to form a first sidewall, wherein the ONO layer comprises a thinned first oxide layer, a nitride layer and a thickened second oxide layer;

[0008] Step 3: Perform source and drain ion implantation on the memory cell region;

[0009] Step 4: Deposit a SiN layer and etch it to form the second sidewall;

[0010] Step 5: Perform source and drain ion implantation on the peripheral region;

[0011] Step 6: Deposit SAB oxide and perform photolithography etching process;

[0012] Step 7: Perform pre-cleaning treatment on the substrate surface;

[0013] Step 8: Use a wet phosphoric acid etching process to etch the nitride layer of the sidewall to reduce the height and thickness of the sidewall;

[0014] Step 9: Deposit NiPt and TiN using physical vapor deposition sputtering process.

[0015] Preferably, the substrate in step one is a silicon substrate.

[0016] Preferably, the gate structure described in step one is a control gate.

[0017] Preferably, in step two, the first oxide layer is an HTO layer, the second oxide layer is a TEOS layer, and the nitride layer is a SiN layer.

[0018] Preferably, the thickness of the thinned first oxide layer in step two is the same as the thickness of the thickened second oxide layer.

[0019] Preferably, the thickness of the thinned first oxide layer is 50 angstroms.

[0020] Preferably, the etching in step two uses the HTO layer as the etching stop layer.

[0021] Preferably, the etching process in step six includes dry etching and wet etching processes.

[0022] Preferably, the pre-cleaning treatment in step seven is a wet cleaning treatment using hydrofluoric acid.

[0023] Preferably, the phosphoric acid described in step eight has a high selectivity.

[0024] In this invention, a thinned first oxide layer (TEOS), a nitride layer (SiN), and a thickened second oxide layer (HTO) are deposited as the first sidewall. Before forming the metal silicide, the sidewall SiN is etched using a high-selectivity phosphoric acid wet etching process, which reduces the height of the cell region sidewall and laterally expands the drain space. This thins the sidewall thickness and height, reduces the aspect ratio of the ILD DEP (deposition), improves the ILD filling performance of the NOR flash memory device, and has no impact on the electrical properties of the memory cell region and the peripheral region. The operation is simple and highly feasible. Attached Figure Description

[0025] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0026] Figure 1 This diagram illustrates the voids present in the ILD filling of current NOR flash memory devices.

[0027] Figure 2 The flowchart shown is a method for manufacturing a NOR flash memory device according to an embodiment of the present invention;

[0028] Figure 3 The diagram shows the structure of SAB oxide after etching, according to an embodiment of the present invention.

[0029] Figure 4 The diagram shown is a schematic representation of the structure of the SiN sidewalls after being etched using a wet phosphoric acid etching process according to an embodiment of the present invention. Detailed Implementation

[0030] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0031] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0032] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0033] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0034] NOR Flash is a type of non-volatile computer storage medium that uses NOR logic gates and can be electronically erased and rewritten. Flash memory cells are three-terminal devices: source, drain, and gate. Because of the silicon dioxide insulating layer between the gate and the silicon substrate, the charge in the floating gate does not leak, giving flash memory its memory capacity. NOR Flash belongs to the category of non-volatile memory; NOR has a fast read speed and supports erasable writing, making it a primary device for code storage.

[0035] Figure 1 The flowchart shown is a method for manufacturing a NOR flash memory device according to an embodiment of the present invention. Figure 1 As shown, the manufacturing method of the NOR flash memory device according to an embodiment of the present invention includes the following steps:

[0036] Step 1: Provide a substrate on which a gate structure is formed.

[0037] The substrate material can be silicon, germanium, silicon-germanium, or silicon carbide, or it can be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or other materials such as gallium arsenide or other group III or V compounds. In other embodiments, the substrate may include various doped regions depending on the design requirements of the memory. The substrate may include isolation structures (e.g., shallow trench isolation, STI) to isolate the regions and / or semiconductor devices formed on the substrate. The substrate in this embodiment is a silicon substrate, and further, it may be an undoped or lightly doped silicon substrate.

[0038] In this embodiment of the invention, a control gate is formed on the substrate. The NOR flash memory device includes a memory cell region and a peripheral region. A gate oxide layer, a floating gate, a dielectric layer, and a control gate are formed on the memory cell region, and a gate oxide layer and a control gate are formed on the peripheral region.

[0039] Step 2: Deposit an ONO layer and etch it to form a first sidewall. The ONO layer includes a thinned first oxide layer, a nitride layer, and a thickened second oxide layer.

[0040] In this embodiment of the invention, the first oxide layer is an HTO layer, the second oxide layer is a TEOS layer, and the nitride layer is a SiN layer. In the existing manufacturing process of the ONO layer, the bottom silicon dioxide is generally deposited using thermal growth (consuming the silicon substrate) or LPCVD (low-pressure chemical vapor deposition) deposition process (not consuming the silicon substrate), which generally includes furnace tube thermal oxidation, nitrogen doping, and thermal annealing. The silicon dioxide surface is ion implanted and thermally annealed, or the surface silicon dioxide is nitrided at high temperature using furnace tube N2O and thermally annealed to introduce Si-N bonds, thereby improving the reliability of silicon dioxide and the bonding strength with silicon nitride. The manufacturing process of the sandwich silicon nitride is generally carried out using furnace tube LPCVD deposition. In order to obtain sandwich silicon nitride with better uniformity and controllability, a low-temperature silicon nitride process is often used, followed by a high-temperature silicon nitride densification process. The top silicon dioxide is generally deposited using furnace tube HTO (high-temperature oxidation) process, followed by an HTO densification process.

[0041] In this embodiment of the invention, the thickness of the thinned first oxide layer is the same as the thickness of the thickened second oxide layer. That is, the overall thickness of the first sidewall remains unchanged. Specifically, the thickness of the thinned first oxide layer is 50 angstroms, and the thickness of the thickened second oxide layer is also 50 angstroms. Of course, in other embodiments, other thicknesses may be used, depending on the specific circumstances. After depositing the ONO layer, a dry etching process is performed on the ONO layer, with the HTO layer of the ONO layer serving as the etching stop layer, thereby forming the first sidewall.

[0042] Step 3: Perform source and drain ion implantation on the memory cell area.

[0043] Specifically, it is achieved using photolithography and imp (ion implantation) processes, which will not be described in detail here.

[0044] Step 4: Deposit a SiN layer and etch it to form a second sidewall.

[0045] In this embodiment of the invention, the thickness of the second sidewall remains unchanged and is the same as the thickness formed by the existing process.

[0046] Step 5: Perform source and drain ion implantation on the peripheral region.

[0047] Specifically, it is achieved using photo and imp processes, which will not be described in detail here.

[0048] Step 6: Deposit SAB oxide and perform photolithography etching.

[0049] Here, etching processes include dry etching and wet etching processes. For example... Figure 3 The diagram shown is a schematic representation of the structure after SAB oxide has been etched.

[0050] Step 7: Pre-clean the substrate surface.

[0051] In this embodiment of the invention, the pre-cleaning process is a wet cleaning process using hydrofluoric acid. Hydrofluoric acid removes oxides from the substrate surface, resulting in a clean substrate. If the surface oxides are not completely removed, an additional step can be added using a SPM (Surface Purification Process) cleaning technology.

[0052] Step 8: Use a wet phosphoric acid etching process to etch the nitride layer on the sidewalls to reduce the height and thickness of the sidewalls.

[0053] Phosphoric acid (HPO4) has a selectivity, allowing for the etching of nitride layers on the sidewalls. For example... Figure 4 The diagram shows a schematic of the structure after sidewall SiN etching using a phosphoric acid wet etching process. Laterally, etching the SiN increases the cell drain space; vertically, as shown... Figure 4 As shown in the middle circle, the L-shaped SIN shoulder is eaten downwards.

[0054] In this embodiment of the invention, after completing SAB WET (wet etching), an additional HPO wash is performed to remove a portion of the SiN in the first sidewall. By utilizing the high selectivity of HPO, the height of the cell sidewall is reduced, and the drain space is laterally expanded. This reduces the sidewall thickness and height, decreases the ILD DEP (deposition) aspect ratio, and improves the ILD filling performance of the NOR flash memory device.

[0055] Step 9: Deposit NiPt and TiN using physical vapor deposition sputtering process.

[0056] After depositing NiPt and TiN, two annealing processes are required to form metal silicides. Specifically, the first annealing process generates high-resistivity metal silicide Ni2PtSi; wet etching is used to remove TiN and unreacted NiPt; and the second annealing process converts the high-resistivity Ni2PtSi into the low-resistivity NiPtSi2. Of course, subsequent NOR flash memory device manufacturing requires other process steps, which will not be elaborated here.

[0057] The method for manufacturing NOR flash memory devices of the present invention deposits a thinned first oxide layer TEOS, a nitride layer SiN, and a thickened second oxide layer HTO as the first sidewall. Before forming the metal silicide, the sidewall SiN is etched using a high-selectivity phosphoric acid wet etching process, which reduces the height of the cell region sidewall and laterally expands the drain space. This reduces the sidewall thickness and height, decreases the ILD DEP (deposition) aspect ratio, improves the ILD filling performance of the NOR flash memory device, and has no impact on the electrical properties of the memory cell region and the peripheral region. The method is simple to operate and highly feasible.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a NOR flash memory device, the NOR flash memory device comprising a memory cell region and a peripheral region, characterized in that, Includes the following steps: Step 1: Provide a substrate on which a gate structure is formed; Step 2: Deposit an ONO layer and etch it to form a first sidewall. The ONO layer includes a thinned first oxide layer, a nitride layer, and a thickened second oxide layer. The thickness of the thinned first oxide layer is the same as the thickness of the thickened second oxide layer. Step 3: Perform source and drain ion implantation on the memory cell region; Step 4: Deposit a SiN layer and etch it to form the second sidewall; Step 5: Perform source and drain ion implantation on the peripheral region; Step 6: Deposit SAB oxide and perform photolithography etching process; Step 7: Perform pre-cleaning treatment on the substrate surface; Step 8: Use a wet phosphoric acid etching process to etch the nitride layer of the first sidewall to reduce the height and thickness of the first sidewall; Step 9: Deposit NiPt and TiN using physical vapor deposition sputtering process.

2. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The substrate mentioned in step one is a silicon substrate.

3. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The gate structure described in step one is a control gate.

4. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, In step two, the first oxide layer is an HTO layer, the second oxide layer is a TEOS layer, and the nitride layer is a SiN layer.

5. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The thickness of the thinned first oxide layer is 50 angstroms.

6. The method for manufacturing a NOR flash memory device according to claim 4, characterized in that, The etching described in step two uses the HTO layer as the etching stop layer.

7. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The etching process described in step six includes dry etching and wet etching processes.

8. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The pre-cleaning process described in step seven involves wet cleaning using hydrofluoric acid.

9. The method for manufacturing a NOR flash memory device according to claim 1, characterized in that, The phosphoric acid described in step eight has a high selectivity.

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