Multi-stage erase operation for memory devices

By employing voltage offset technology in multi-stage erase operations, the durability and read interference issues caused by the increased threshold voltage of the GIDL generator during the erase operation of non-volatile memory devices are resolved, thereby improving the performance and reliability of the memory.

CN115997253BActive Publication Date: 2026-07-17MICRON TECHNOLOGY INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
MICRON TECHNOLOGY INC
Filing Date
2021-08-10
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

Existing non-volatile memory devices suffer from durability limitations and read interference effects during erase operations due to the increased threshold voltage of the GIDL generator, which affects the performance and reliability of the memory devices.

Method used

A multi-stage erase operation is employed, which reduces the electrostatic trapping effect by applying different offset voltages to the GIDL generator and the select gate device at different stages of the erase operation, thereby improving the reliability of the GIDL generator and increasing the threshold voltage of the select gate device.

Benefits of technology

It improves the durability of memory devices and the effectiveness of erase operations, reduces the impact of programming/erasing cycles on device performance, and extends the lifespan of memory.

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Abstract

Control logic in the memory device initiates an erase operation on the memory array, and during the erase operation, applies an erase voltage signal to the source terminals of a string of memory cells in a data block of the memory array. During a first phase of the erase operation, the control logic further applies a first voltage signal to a first word line of the data block and applies a second voltage signal to a second word line of the data block, wherein the first word line is coupled to a gate-induced drain leakage (GIDL) generator device in the source terminal of the memory cell string and the second word line is coupled to a adjacent selected gate (SGS) device in the source terminal of the memory cell string, and wherein both the first and second voltage signals have a common first voltage offset relative to the erase voltage signal. During a second phase of the erase operation, the control logic further determines the end of the first phase of the erase operation and reduces the first voltage signal relative to the erase voltage signal to a second voltage offset and reduces the second voltage signal relative to the erase voltage signal to a third voltage offset, wherein the second offset is greater than the third offset.
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