Semiconductor structure and method of forming the same, and mask layout

Abstract

A semiconductor structure, a method for forming the semiconductor structure, and a mask layout, the semiconductor structure comprising: a substrate comprising a substrate and a plurality of parallel arranged fins on the substrate, the substrate comprising a transistor cell region, in the transistor cell region, in a direction perpendicular to an extending direction of the fins, a fin closest to a boundary of the transistor cell region is an edge fin, and the edge fin has an outer sidewall facing the boundary of the transistor cell region; and a gate structure across the fins and covering a part of top and a part of sidewall of the fins, the gate structure exposing at least a part of the outer sidewall of any edge fin. The present application exposes at least a part of the outer sidewall of any edge fin by the gate structure, reduces the sidewall area of the edge fin covered by the gate structure, and thus can reduce the effective channel width by adjusting the etching amount of the gate structure on the outer sidewall while ensuring the normal operation of the transistor, thereby improving the flexibility of adjusting the effective channel width of the transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same, as well as a photomask layout. Background Technology

[0002] As semiconductor process technology advances, semiconductor process nodes are shrinking in accordance with Moore's Law. To accommodate this shrinking process node, the channel length of MOSFETs is also continuously shortening. However, as the channel length decreases, the distance between the source and drain also decreases, resulting in poorer gate control over the channel and increasing the difficulty of pinching off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field-Effect Transistors (FinFETs). In FinFETs, the gate can control the ultra-thin body (fin) from at least both sides. Compared with planar MOSFETs, the gate has stronger control over the channel and can effectively suppress short-channel effects. Moreover, FinFETs have better compatibility with existing integrated circuit manufacturing compared to other devices. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and its formation method, as well as a mask layout, to improve the flexibility of adjusting the effective channel width of transistors.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, including a base and a plurality of parallel-arranged fins located on the substrate, the substrate including transistor cell regions for forming transistors, wherein in the transistor cell regions, the fins closest to the boundary of the transistor cell region in a direction perpendicular to the extension direction of the fins are designated as edge fins, and the edge fins have outer sidewalls facing the boundary of the transistor cell region; and a gate structure located on the substrate and spanning the fins, the gate structure covering a portion of the top and a portion of the sidewalls of the fins, wherein the gate structure exposes at least a portion of the outer sidewall of any of the edge fins.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a plurality of parallel fins located on the substrate, the substrate including a transistor cell region for forming a transistor, wherein in the transistor cell region, in a direction perpendicular to the extension direction of the fins, the fins closest to the boundary of the transistor cell region are designated as edge fins, and the edge fins have outer sidewalls facing the boundary of the transistor cell region; forming a gate structure across the fins on the substrate, the gate structure covering a portion of the top and a portion of the sidewalls of the fins; etching the gate structure on the outer sidewall of any of the edge fins to remove at least a portion of the gate structure on the outer sidewall.

[0007] Accordingly, embodiments of the present invention also provide a mask layout, comprising: an active region layout, including a transistor cell region for forming a transistor, wherein the transistor cell region has an active region pattern; a fin layout, including a plurality of parallel fin patterns located in the active region pattern, wherein the fin pattern closest to the boundary of the transistor cell region in a direction perpendicular to the extension direction of the fin pattern is designated as an edge fin pattern, and the edge fin pattern has an outer boundary facing the boundary of the transistor cell region; a gate layout, including a gate pattern located in the cell region, the gate pattern spanning the fin pattern and orthogonal to the fin pattern; and a gate cut-off layout, including a first gate cut-off pattern, the first gate cut-off pattern covering the gate pattern between any outer boundary and the boundary of the transistor cell region.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure provided by this invention, the substrate includes a transistor cell region for forming a transistor. In the transistor cell region, the fin closest to the boundary of the transistor cell region in a direction perpendicular to the fin's extension direction is designated as an edge fin, and the edge fin has an outer sidewall facing the boundary of the transistor cell region. A gate structure is located on the substrate and spans the fin. The gate structure covers a portion of the top and a portion of the sidewall of the fin, and the gate structure exposes at least a portion of the outer sidewall of any of the edge fins. Both the sidewall and top of the fin can be used to provide a channel for the transistor. That is, the height and width of the fin covered by the gate structure affect the effective channel width of the transistor. Therefore, by exposing at least a portion of the outer sidewall of any of the edge fins by the gate structure, the sidewall area of ​​the edge fin covered by the gate structure is reduced. This allows for adjusting the height of the exposed outer sidewall of the gate structure to reduce the effective channel width of the fin while ensuring normal transistor operation, thereby improving the flexibility of adjusting the effective channel width of the transistor.

[0010] In the semiconductor structure formation method provided by the present invention, the substrate includes a transistor cell region for forming a transistor. In the transistor cell region, the fin closest to the boundary of the transistor cell region in a direction perpendicular to the extension direction of the fin is designated as an edge fin, and the edge fin has an outer wall facing the boundary of the transistor cell region. After forming a gate structure spanning the fin on the substrate, the gate structure on the outer wall of any edge fin is etched to remove at least a portion of the gate structure on the outer wall. Both the sidewall and top of the fin can be used to provide a channel for the transistor. That is, the height and width of the fin covered by the gate structure affect the effective channel width of the transistor. Therefore, by etching the gate structure on the outer wall of any edge fin to remove at least a portion of the gate structure on the outer wall, the sidewall area of ​​the edge fin covered by the gate structure is reduced. This allows for adjustment of the height of the exposed outer wall of the gate structure while ensuring normal transistor operation, thereby reducing the effective channel width of the fin and improving the flexibility of adjusting the effective channel width of the transistor.

[0011] In the mask layout provided in this embodiment of the invention, the fin layout includes a plurality of parallel fin patterns located in the transistor cell region. The fin pattern closest to the boundary of the transistor cell region in a direction perpendicular to the extending direction of the fin patterns serves as an edge fin pattern, and the edge fin pattern has an outer boundary facing the boundary of the transistor cell region. The gate layout includes a gate pattern located in the cell region, the gate pattern spanning the fin patterns and orthogonal to the fin patterns. The mask layout includes a gate cut-off layout, which includes a first gate cut-off pattern covering the gate pattern between any outer boundary and the boundary of the transistor cell region. The fin patterns are used to form fins, the edge fin patterns are correspondingly used to form edge fins, the gate patterns are used to form the gate structure, and the first gate cut-off pattern is used to define the etched area in the gate structure. Therefore... By adding a first gate cut-off pattern to the mask layout, when forming a semiconductor structure using the mask layout, the gate structure on the outer wall of any edge fin can be etched, at least removing a portion of the gate structure on the outer wall. Both the sidewall and top of the fin can be used to provide a transistor channel. That is, the height and width of the fin covered by the gate structure affect the effective channel width of the transistor. Correspondingly, by etching the gate structure on the outer wall of any edge fin, at least a portion of the gate structure on the outer wall is removed, reducing the sidewall area of ​​the edge fin covered by the gate structure. This allows for adjusting the amount of etching on the gate structure on the outer wall to adjust the height of the exposed outer wall of the gate structure, thereby reducing the effective channel width of the fin and improving the flexibility of adjusting the effective channel width of the transistor. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a semiconductor structure.

[0013] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0014] Figure 3 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention.

[0015] Figure 4 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention.

[0016] Figures 5 to 7 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0017] Figures 8 to 9This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention.

[0018] Figure 10 This is a schematic diagram of another embodiment of the semiconductor structure formation method of the present invention.

[0019] Figure 11 This is the mask plate of the present invention. Figure 1 A schematic diagram of an embodiment. Detailed Implementation

[0020] Currently, adjusting the effective channel width of a transistor is quite difficult. The following analysis, with reference to the accompanying diagram, explains the reasons for this difficulty.

[0021] refer to Figure 1 The diagram shows a schematic of a semiconductor structure.

[0022] The semiconductor structure includes: a substrate 10; a fin 11 protruding from the substrate 10; an isolation layer 12 located on the substrate 10 exposed by the fin 11 and covering a portion of the sidewalls of the fin 11; and a gate structure 20 located on the isolation layer 12 and spanning the fin 11, the gate structure 20 covering a portion of the top and a portion of the sidewalls of the fin 11. The height and width of the fin 11 covered by the gate structure 20 both affect the effective channel width of the transistor. Specifically, when the gate structure 20 covers the top of the fin 11 and its two opposite sidewalls, the effective channel width provided by a single fin 11 is the sum of the width of the fin 11 and twice the effective height of the fin 11.

[0023] It should be noted that the effective height of the fin 11 refers to the height of the fin 11 exposed by the isolation layer 12.

[0024] In the current FinFET structure, the effective channel width provided by a single fin is fixed (i.e., the sum of the fin width and twice the effective fin height), and cannot be changed. The effective channel width of the transistor can only be changed by altering the number of fins corresponding to the transistor (e.g., Figure 1The diagram shows that the transistor has five fins (11). This means the effective channel width can only increase in positive integer multiples, making it difficult to freely adjust the effective channel width according to the transistor's performance requirements (e.g., saturation current). Similarly, for a standard cell, changing the number of fins in the standard cell controls leakage current and turn-on current to match the appropriate application, but the effective channel width still can only increase in positive integer multiples. Furthermore, when the standard cell is reduced from a 6-track (i.e., 6T) standard cell downwards, since the number of fins in each active region of the 6T standard cell is two, the height of the standard cell is difficult to further reduce, and the number of fins can only be reduced from two to one, resulting in low process flexibility. Moreover, reducing the number of fins in each active region to one can easily cause the problem of insufficient drive current.

[0025] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure comprising: a substrate, including a base and a plurality of parallel-arranged fins located on the substrate, the substrate including transistor cell regions for forming transistors, wherein in the transistor cell regions, the fins closest to the boundary of the transistor cell region in a direction perpendicular to the extension direction of the fins are designated as edge fins, and the edge fins have outer sidewalls facing the boundary of the transistor cell region; and a gate structure located on the substrate and spanning the fins, the gate structure covering a portion of the top and a portion of the sidewalls of the fins, wherein the gate structure exposes at least a portion of the outer sidewall of any of the edge fins. In the embodiments of the present invention, both the sidewalls and the top of the fins can be used to provide a channel for the transistor. That is, the height and width of the fins covered by the gate structure both affect the effective channel width of the transistor. Therefore, by exposing at least a portion of the outer sidewall of any of the edge fins by the gate structure, the sidewall area of ​​the edge fins covered by the gate structure is reduced. This allows for the reduction of the effective channel width of the fins by adjusting the height of the exposed outer sidewall of the gate structure while ensuring normal operation of the transistor, thereby improving the flexibility of adjusting the effective channel width of the transistor.

[0026] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0028] The semiconductor structure includes: a substrate 300, including a base 301 and a plurality of parallel fins 302 located on the base 301, the base 301 including transistor cell regions 300a for forming transistors, wherein in the transistor cell region 300a, the fins 302 closest to the boundary of the transistor cell region 300a in a direction perpendicular to the extending direction of the fins 302 serve as edge fins 325, and the edge fins 325 have an outer sidewall 326 facing the boundary of the transistor cell region 300a; and a gate structure 330 located on the base 300 and spanning the fins 302, the gate structure 330 covering a portion of the top and a portion of the sidewalls of the fins 302, wherein the gate structure 330 exposes at least a portion of the outer sidewall 326 of any of the edge fins 325.

[0029] Both the sidewalls and top of the fin 302 can be used to provide the channel for the transistor. That is, the height and width of the fin 302 covered by the gate structure 330 will affect the effective channel width of the transistor. When the gate structure 330 covers the fin 302, the effective channel width that one fin 302 can provide is the sum of the width of the fin 302 and twice the effective height of the fin 302. Therefore, by exposing at least a portion of the outer sidewall 326 of any of the edge fins 325 through the gate structure 330, the sidewall area of ​​the edge fin 325 covered by the gate structure 330 is reduced. This allows the effective channel width of the fin 302 to be reduced by adjusting the height of the exposed outer sidewall 326 of the gate structure 330 while ensuring normal operation of the transistor, thereby improving the flexibility of adjusting the effective channel width of the transistor. The width of the fin 302 refers to the size of the fin 302 in a direction parallel to the surface of the substrate 301 and perpendicular to the extension direction of the fin 302. The semiconductor structure typically also includes an isolation layer 303 located on the substrate 301 and covering part of the sidewalls of the fin 302. The effective height of the fin 302 refers to the height of the fin 302 exposed by the isolation layer.

[0030] Specifically, the solution provided in this embodiment can overcome the current limitation that the effective channel width of a transistor can only be changed by altering the number of fins corresponding to the transistor, i.e., it overcomes the limitation that the effective channel width can only increase in multiples of positive integers. Furthermore, in the transistor cell region 300a, when the number of fins 302 corresponding to each transistor is two, compared to a solution using only one fin, by exposing at least a portion of the outer wall 326 of any of the edge fins 325 through the gate structure 330, the effective channel width of the transistor can be reduced, and the problem of insufficient drive current can be improved. In addition, by exposing at least a portion of the outer wall 326 of any of the edge fins 325 through the gate structure 330, more design options can be provided for logic standard cells to match more application requirements. For example, the logic standard cell can be further reduced from a 6-track (i.e., 6T) standard cell to further decrease the height of the logic standard cell.

[0031] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the substrate 300 correspondingly includes a substrate 301 and a plurality of parallel-arranged fins 302 located on the substrate 301. In this embodiment, the material of the substrate 301 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0032] The fin 302 is disposed on the substrate 301, and a portion of the fin 302 is used to provide a channel for the fin field-effect transistor. In this embodiment, the fin 302 and the substrate 301 are an integral structure, and the material of the fin 302 is the same as that of the substrate 301, which is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. In other embodiments, depending on the actual situation, the fin may also be a semiconductor layer epitaxially grown on the substrate, and the materials of the fin and the substrate may also be different.

[0033] In this embodiment, in a direction perpendicular to the extension direction of the fin 302, the edge fin 325 has an outer sidewall 326 facing the boundary of the transistor cell region 300a, and the edge fin 325 also has an inner sidewall 327 opposite to the outer sidewall 326.

[0034] In this embodiment, the substrate 301 includes transistor cell regions 300a for forming transistors. Each transistor cell region 300a shares a common gate structure 330. It should be noted that each transistor cell region 300a is not limited to forming transistors of the same channel conductivity type. For example, one transistor cell region 300a can be used to form both NMOS and PMOS transistors; that is, one transistor cell region 300a can be used to form multiple transistors, with the NMOS and PMOS transistors sharing the gate structure 330. In other embodiments, depending on the circuit design, each transistor cell region is used only to form transistors of the same channel conductivity type (NMOS or PMOS transistors), and each transistor cell region is used only to form one transistor.

[0035] In this embodiment, the fin 302 closest to the boundary of the transistor cell region 300a serves as an edge fin 325. Since the transistor cell region 300a has two boundaries in a direction perpendicular to the extending direction of the fin 302, the number of edge fins 325 is correspondingly two. In this embodiment, the number of fins 302 in the transistor cell region 300a in a direction perpendicular to the extending direction of the fin 302 is multiple. Specifically, the number of fins 302 in the transistor cell region 300a is set according to the performance requirements of the transistor. The gate structure 330 spans the fin 302 and covers part of the top and sidewalls of the fin 302; therefore, both the sidewalls and top of the fin 302 can provide a channel for the transistor. The more fins 302 there are, the larger the effective channel width of the transistor. As an example, the number of fins 302 is two; correspondingly, both fins 302 can serve as edge fins 325. In other embodiments, for example, when the number of fins is five, the number of edge fins is two, and the number of remaining fins located between the edge fins is three.

[0036] In other embodiments, depending on actual needs, a fin near one boundary of the transistor cell region in a direction perpendicular to the fin's extension direction is designated as an edge fin, meaning the number of edge fins can also be one.

[0037] In this embodiment, in a direction perpendicular to the extending direction of the fin 302, the top width of the fin 302 is greater than the bottom width of the fin 302, that is, the cross-sectional shape of the fin 302 is trapezoidal.

[0038] In this embodiment, the substrate 300 further includes an isolation layer 303 located on the substrate 301 exposed by the fin 302, the isolation layer 303 covering a portion of the sidewalls of the fin 302. The isolation layer 303 serves as a shallow trench isolation (STI) structure to isolate adjacent devices. Furthermore, the isolation layer 303 defines the effective height of the fin 302; that is, the fin 302 exposed by the isolation layer 303 provides a channel for the transistor. The isolation layer 303 is made of an insulating material. As an example, the material of the isolation layer 303 is silicon oxide. In other embodiments, the material of the isolation layer may also be silicon nitride, silicon oxynitride, or silicon carbonitride.

[0039] In this embodiment, the gate structure 330 is a device gate structure. The device gate structure is used to control the turning on and off of the transistor channel. As an example, the gate structure 330 is a metal gate (MG) structure. Specifically, the metal gate structure includes a gate dielectric layer 331 that conformally covers the top and sidewalls of the conformal covering fin 302, a work function layer 332 that conformally covers the gate dielectric layer 331, and a gate electrode layer 333 that conformally covers the work function layer 332.

[0040] In this embodiment, the gate dielectric layer 331 is a high-k gate dielectric layer, and the material of the gate dielectric layer 331 is a high-k dielectric material. A high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the material of the gate dielectric layer 331 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the gate dielectric layer 331 is HfO2.

[0041] The work function layer 332 is used to adjust the threshold voltage of the fin field-effect transistor. When the device is a PMOS transistor, the work function layer 332 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when the device is an NMOS transistor, the work function layer 332 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0042] The gate electrode layer 333 is a metal gate layer used to expose the electrical properties of the metal gate structure. The material of the gate electrode layer 333 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, the material of the gate electrode layer 333 is W.

[0043] By adjusting the height of the exposed outer wall 326 of the gate structure 330, the effective channel width of the fin 302 is adjusted (specifically, the effective channel width of the fin 302 is reduced), thereby improving the flexibility of adjusting the effective channel width of the transistor. It should be noted that transistors located in the same transistor cell region 300a share the gate structure 330. Therefore, in the same transistor cell region 300a, the gate structure 330 between adjacent fins 302 cannot be disconnected; the gate structure 330 must expose at least a portion of the outer wall 326 of any edge fin 325 to ensure the integrity of the gate structure 330 in the same transistor cell region 300a, thereby ensuring the normal operation of the transistor.

[0044] In this embodiment, depending on the transistor's performance requirements and circuit design, the gate structure 330 can expose only a portion or the entire outer wall 326 of one edge fin 325, or it can expose a portion or the entire outer wall 326 of both edge fins 125. For example... Figure 3 As shown, as an example, the gate structure 330 exposes only the outer wall 326 of an edge fin 325.

[0045] In this embodiment, according to the performance requirements of the transistor, the gate structure 330 exposes a portion of the outer wall 326 of any edge fin 325; or, the gate structure 330 exposes the entire outer wall 326 of any edge fin 325; or, the gate structure 330 exposes the entire outer wall 326 of any edge fin 325 and also exposes a portion of the top of the edge fin 325; or, the gate structure 330 exposes the entire outer wall 326 of any edge fin 325 and also exposes the top of the edge fin 325. During the formation of the semiconductor structure, the gate structure 330 is typically etched to expose the outer wall 326. Since the top width of the fin 302 is greater than the bottom width of the fin 302 in a direction perpendicular to the extension direction of the fin 302, it is easy to achieve the effect of exposing a portion of the outer wall 326 of the edge fin 125 in the manufacturing process.

[0046] As an example, the gate structure 330 exposes the entire outer wall 326 of any edge fin 325, and also exposes a portion of the top of the edge fin 325. By exposing a portion of the top of the edge fin 325, the process window for etching the gate structure 330 is increased during the formation of the semiconductor structure, reducing the alignment accuracy requirements in the photolithography process. Furthermore, the fact that sufficient gate structure 330 still covers the edge fin 325 helps ensure the gate structure 330's control over the channel in the edge fin 325.

[0047] It should be noted that the edge fin 325 also has an inner sidewall 327 opposite to the outer sidewall 326, and the gate structure 330 covers the inner sidewall 327 of the edge fin 325 to ensure the normal performance of the transistor.

[0048] In this embodiment, the semiconductor structure further includes a gate oxide layer 320 located between the gate structure 330 and the fin 302. In other embodiments, the gate oxide layer may also extend to cover the exposed outer wall of the gate structure. During the formation of the semiconductor structure, when etching the gate structure 330, the gate oxide layer 320 on the surface of the edge fin 325 can serve as an etching stop layer, thereby reducing damage to the fin 302 caused by the etching process of the gate structure 330. Furthermore, for devices with high operating voltages (e.g., input / output devices), the gate oxide layer 320 also serves to isolate the gate structure 330 and the channel. The material of the gate oxide layer 320 includes one or both of silicon oxide and silicon oxynitride. As an example, the material of the gate oxide layer 320 is silicon oxide.

[0049] It should be noted that the semiconductor structure further includes an interlayer dielectric layer (not shown), located on the substrate 300 on the side of the gate structure 330 and covering the sidewall of the gate structure 330. The interlayer dielectric layer also covers the exposed edge fins 325 of the gate structure 330. The interlayer dielectric layer serves to isolate adjacent devices. The material of the interlayer dielectric layer is an insulating material. As an example, the material of the interlayer dielectric layer is silicon oxide.

[0050] Figure 3 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention.

[0051] The similarities between the embodiments of the present invention and the foregoing embodiments will not be repeated here. The difference between the embodiments of the present invention and the foregoing embodiments is that the number of transistor unit regions 400a is multiple.

[0052] In this embodiment, the transistors in each transistor cell region 400a share a common gate structure, and the gate structures (not shown) in adjacent transistor cell regions 400a are isolated from each other. In this embodiment, the fin closest to the boundary between adjacent transistor cell regions 400a is designated as the edge fin 425. That is, the gate structure exposes the outer wall 426 near the boundary between adjacent transistor cell regions 400a.

[0053] Specifically, during the formation of the semiconductor structure, the gate structure at the boundary of adjacent transistor cell regions 400a is typically subjected to gate cutting processing to divide the gate structure of adjacent transistor cell regions 400a in the extension direction of the gate structure. By exposing the outer wall 426 near the boundary of adjacent transistor cell regions 400a, the gate structure on the edge fin 425 and the gate cutting processing of the gate structure at the boundary of adjacent transistor cell regions 400a can be performed in the same step, thereby avoiding the introduction of additional process steps and allowing the use of the same photomask, thus avoiding the need for additional photomasks.

[0054] For a detailed description of the semiconductor structure, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0055] Figure 4 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention.

[0056] The similarities between the embodiments of the present invention and the foregoing embodiments will not be repeated here. The difference between the embodiments of the present invention and the foregoing embodiments is that: in the transistor cell region 700a, in the direction perpendicular to the extension direction of the fin 702, at the top surface position of the isolation layer 703, the edge fin 725 corresponding to the exposed outer wall 726 of the gate structure (not shown) has a first bottom width W1, and the remaining fin 702 has a second bottom width W2. The first bottom width W1 is smaller than the second bottom width W2.

[0057] Since the gate structure exposes at least part of the outer wall 726, by making the first bottom width W1 smaller than the second bottom width W2, the edge fin 725 corresponding to the exposed outer wall 726 of the gate structure has a smaller width compared to the other fins 702, thereby improving the gate structure's control over the channel in the edge fin 725 and reducing leakage current.

[0058] For a detailed description of the semiconductor structure, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0059] Figures 5 to 7 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0060] refer to Figure 5 A substrate 100 is provided, including a substrate 101 and a plurality of parallel-arranged fins 102 located on the substrate 101. The substrate 101 includes transistor cell regions 100a for forming transistors. In the transistor cell regions 100a, in a direction perpendicular to the extending direction of the fins 102 (e.g., Figure 5(As shown in the X direction), the fin 102 closest to the boundary of the transistor cell region 100a is an edge fin 125, and the edge fin 125 has an outer wall 126 facing the boundary of the transistor cell region 100a.

[0061] The substrate 100 provides the basis for the process operation of forming the semiconductor structure. In this embodiment, the semiconductor structure is a fin field-effect transistor, and the substrate 100 accordingly includes a substrate 101 and a plurality of parallel-arranged fins 102 located on the substrate 101. In this embodiment, the material of the substrate 101 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc., and the substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0062] The fin 102 is disposed on the substrate 101, and a portion of the fin 102 is used to provide a channel for the fin field-effect transistor. In this embodiment, the fin 102 and the substrate 101 are integrally formed, and the material of the fin 102 is the same as that of the substrate 101, which is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. In other embodiments, depending on the actual situation, the fin may also be a semiconductor layer epitaxially grown on the substrate, and the materials of the fin and the substrate may be different.

[0063] In this embodiment, in a direction perpendicular to the extension direction of the fin 102, the edge fin 125 has an outer wall 126 facing the boundary of the transistor cell region 100a, and the edge fin 125 also has an inner wall 127 opposite to the outer wall 126.

[0064] In this embodiment, the substrate 101 includes transistor cell regions 100a for forming transistors. Each transistor cell region 100a shares a common gate structure. It should be noted that each transistor cell region 100a is not limited to forming transistors of the same channel conductivity type. For example, one transistor cell region 100a can be used to form both NMOS and PMOS transistors; that is, one transistor cell region 100a can be used to form multiple transistors, with the NMOS and PMOS transistors sharing a common gate structure. In other embodiments, depending on the circuit design, each transistor cell region is used only to form transistors of the same channel conductivity type, and each transistor cell region is used only to form one transistor.

[0065] In this embodiment, the fin 102 closest to the boundary of the transistor cell region 100a serves as an edge fin 125. Since the transistor cell region 100a has two boundaries in a direction perpendicular to the extending direction of the fin 102, the number of edge fins 125 is correspondingly two. In this embodiment, the number of fins 102 in the transistor cell region 100a in a direction perpendicular to the extending direction of the fin 102 is multiple. Specifically, the number of fins 102 in the transistor cell region 100a is set according to the performance requirements of the transistor. The gate structure spans the fin 102 and covers part of the top and part of the sidewalls of the fin 102; therefore, both the sidewalls and top of the fin 102 can provide a channel for the transistor. The more fins 102 there are, the wider the transistor channel. As an example, the number of fins 102 is two; correspondingly, both fins 102 can serve as edge fins 125. In other embodiments, for example, when the number of fins is five, the number of edge fins is two, and the number of remaining fins located between the edge fins is three.

[0066] In other embodiments, depending on actual needs, a fin near one boundary of the transistor cell region in a direction perpendicular to the fin's extension direction can be designated as an edge fin, i.e., the number of edge fins can also be one.

[0067] In this embodiment, in a direction perpendicular to the extending direction of the fin 102, the top width of the fin 102 is greater than the bottom width of the fin 102, that is, the cross-sectional shape of the fin 102 is trapezoidal.

[0068] In this embodiment, the substrate 100 further includes an isolation layer 103 located on the substrate 101 exposed by the fin 102, the isolation layer 103 covering a portion of the sidewalls of the fin 102. The isolation layer 103 serves as a shallow trench isolation (STI) structure to isolate adjacent devices. Furthermore, the isolation layer 103 defines the effective height of the fin 102; that is, the fin 102 exposed above the isolation layer 103 is the effective fin, which provides the channel for the transistor. The isolation layer 103 is made of an insulating material. As an example, the material of the isolation layer 103 is silicon oxide. In other embodiments, the material of the isolation layer may also be silicon nitride, silicon oxynitride, or silicon carbonitride.

[0069] Continue to refer to Figure 5 A gate structure 130 is formed on the substrate 100, spanning the fin 102, the gate structure 130 covering part of the top and part of the sidewall of the fin 102.

[0070] The gate structure 130 may include a device gate structure or a dummy gate structure. The device gate structure is used to control the switching on and off of the transistor channel; the dummy gate structure is used to occupy space for the subsequent formation of the device gate structure. In this embodiment, when the gate structure 130 is a dummy gate structure, the dummy gate structure includes a polysilicon gate structure or an amorphous silicon gate structure; when the gate structure 130 is a device gate structure, the device gate structure includes a metal gate structure. As an example, the gate structure 130 is a metal gate structure. Specifically, the metal gate structure includes a gate dielectric layer 131 conformally covering the top and sidewalls of the conformally covered fin 102, a work function layer 132 conformally covering the gate dielectric layer 131, and a gate electrode layer 133 conformally covering the work function layer 132.

[0071] In this embodiment, the gate dielectric layer 131 is a high-k gate dielectric layer, and the material of the gate dielectric layer 131 is a high-k dielectric material. Specifically, the material of the gate dielectric layer 131 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the gate dielectric layer 131 is HfO2. The work function layer 132 is used to adjust the threshold voltage of the fin field-effect transistor. When the device is a PMOS transistor, the work function layer 132 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when the device is an NMOS transistor, the work function layer 132 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC. The gate electrode layer 133 is a metal gate layer, used to bring out the electrical properties of the metal gate structure. The gate electrode layer 133 is made of one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, the gate electrode layer 133 is made of W.

[0072] It should be noted that before forming the metal gate structure, a first interlayer dielectric layer (not shown) is formed on the substrate 100. A gate opening (not shown) is formed in the first interlayer dielectric layer, spanning the fin 102 and exposing a portion of the top and sidewalls of the fin 102. The gate opening is formed by removing a dummy gate structure; correspondingly, a metal gate structure is formed within the gate opening. In other embodiments, when the gate structure is a dummy gate structure, after forming the gate structure, the process further includes forming a first interlayer dielectric layer on the substrate on the side of the gate structure. The first interlayer dielectric layer covers the sidewalls of the dummy gate structure and exposes the top of the dummy gate structure. The first interlayer dielectric layer serves to isolate adjacent devices. The material of the first interlayer dielectric layer is an insulating material. As an example, the material of the first interlayer dielectric layer is silicon oxide.

[0073] In this embodiment, before forming the gate structure 130, the formation method further includes forming a gate oxide layer 120 on the top and sidewalls of the fin 102; correspondingly, in the step of forming the gate structure 130, the gate structure 130 covers the gate oxide layer 120, that is, a gate oxide layer 120 is also formed between the gate structure 130 and the fin 102. During subsequent etching of the gate structure 130, the gate oxide layer 120 can serve as an etching stop layer, thereby reducing damage to the fin 102 caused by the etching process of the gate structure 130. Furthermore, for devices with high operating voltages (e.g., input / output devices), the gate oxide layer 120 is also used to isolate the gate structure and the channel. The material of the gate oxide layer 120 includes one or both of silicon oxide and silicon oxynitride. As an example, the material of the gate oxide layer 120 is silicon oxide.

[0074] refer to Figure 6 The gate structure 130 on the outer wall 126 of any of the edge fins 125 is etched to remove at least a portion of the gate structure 130 on the outer wall 126.

[0075] Both the sidewalls and top of the fin 102 can be used to provide the channel of the transistor. That is, the height and width of the fin 102 covered by the gate structure 130 will affect the effective channel width of the transistor. When the gate structure 130 covers the fin 102, the channel width that one fin 102 can provide is the sum of the width of the fin 102 and twice the effective height of the fin 102. Therefore, by etching the gate structure 130 on the outer sidewall 126 of any edge fin 125, at least part of the gate structure 130 on the outer sidewall 126 is removed, thereby reducing the sidewall area of ​​the edge fin 125 covered by the gate structure 130. This allows the height of the exposed outer sidewall 126 of the gate structure 130 to be adjusted by adjusting the amount of etching on the gate structure 130 on the outer sidewall 126 while ensuring the normal operation of the transistor, thus reducing the effective channel width of the fin 102 accordingly. This improves the flexibility of adjusting the effective channel width of the transistor. The width of the fin 102 refers to the size of the fin 102 in a direction parallel to the surface of the substrate 101 and perpendicular to the extension direction of the fin 102; the effective height of the fin 102 refers to the height of the fin 102 exposed by the isolation layer 103.

[0076] Specifically, the solution provided in this embodiment overcomes the current limitation that the effective channel width of a transistor can only be changed by altering the number of fins corresponding to the transistor, i.e., it overcomes the limitation that the effective channel width can only increase in multiples of positive integers. Furthermore, in transistor cell region 100a, when the number of fins 102 corresponding to each transistor is two, compared to a solution using only one fin, removing a portion of the gate structure 130 on the outer wall 126 reduces the effective channel width of the transistor and improves the problem of insufficient drive current. In addition, removing a portion of the gate structure 130 on the outer wall 126 provides more design options for logic standard cells to match more application requirements. For example, the logic standard cell can be further reduced from a 6-track (i.e., 6T) standard cell to further decrease the height of the logic standard cell.

[0077] It should be noted that the transistors formed in the same transistor cell region 100a share a common gate structure 130. Therefore, in the same transistor cell region 100a, the gate structure 130 between adjacent fins 102 cannot be etched. Only the gate structure 130 on the edge fin 125 can be etched. The gate structure 130 on the outer wall 126 is etched first to ensure the integrity of the remaining gate structure 130 in the same transistor cell region 100a, thereby ensuring that the transistor can work normally.

[0078] Depending on the transistor's performance requirements and circuit design, the gate structure 130 on the outer wall 126 of one edge fin 125 can be etched, or the gate structures 130 on the outer walls 126 of both edge fins 125 can be etched. For example... Figure 6 As shown, as an example, only the gate structure 130 on one edge fin 125 is etched.

[0079] In this embodiment, according to the performance requirements of the transistor, in the step of etching the gate structure 130 on the outer wall 126 of any edge fin 125, a portion of the gate structure 130 on the outer wall 126 may be removed; or, the entire gate structure 130 on the outer wall 126 may be removed; or, the entire gate structure 130 on the outer wall 126 may be removed, and a portion of the gate structure 130 on the top of the edge fin 125 may also be removed; or, the entire gate structure 130 on the outer wall 126 may be removed, and the gate structure 130 on the top of the edge fin 125 may also be removed. The more gate structure 130 is removed from the edge fin 125, the smaller the channel width that the edge fin 125 can provide.

[0080] It should be noted that the edge fin 125 also has an inner sidewall 127 opposite to the outer sidewall 126. After etching the gate structure 130 on the outer sidewall 126 of any edge fin 125, the remaining gate structure 130 covers the inner sidewall 127 of the edge fin 125 to ensure the normal performance of the transistor. It should also be noted that since the top width of the fin 102 is greater than the bottom width of the fin 102 in the direction perpendicular to the extension direction of the fin 102, it is easy to remove part of the gate structure 130 on the outer sidewall 126 in the process.

[0081] As an example, removing the gate structure 130 on the entire outer sidewall 126 and also removing a portion of the gate structure 130 on the top of the edge fin 125 increases the process window for etching the gate structure 130, reduces the alignment accuracy requirements in the photolithography process, and ensures that the edge fin 125 is still covered with sufficient gate structure 130, which helps to ensure the gate structure 130's control over the channel in the edge fin 125.

[0082] Specifically, the step of etching the gate structure 130 on the outer wall 126 of any edge fin 125 includes: forming a mask layer 140 on top of the substrate 100 and the gate structure 130, the mask layer 140 exposing the gate structure 130 on the outer wall 126 of any edge fin 125; and etching the exposed gate structure 130 using the mask layer 140 as a mask. Correspondingly, when the entire gate structure 130 on the outer wall 126 is removed, and a portion of the gate structure 130 on the top of the edge fin 125 is also removed, the mask layer 140 still exposes a portion of the gate structure 130 on the top of the edge fin 125. The mask opening in the mask layer 140 has a large size, and the process window for forming the mask opening is large.

[0083] The material of the mask layer 140 is selected to be suitable as an etching mask, meaning there is an etching selectivity between the gate structure 130 and the mask layer 140. The material of the mask layer 140 can be a hard mask material or a photoresist. Specifically, the hard mask material is a dielectric material, such as silicon nitride.

[0084] In this embodiment, an anisotropic dry etching process is used to etch the gate structure 130 on the outer wall 126 of any edge fin 125. The anisotropic dry etching process has the characteristics of anisotropic etching, which is beneficial to improving etching controllability and improving the morphology quality of the etched profile of the remaining gate structure 130 after etching.

[0085] Specifically, in the etching step of the gate structure 130, the gate oxide layer 120 is used as an etching stop layer to reduce damage to the fin 102. There is typically a high etch selectivity between the gate structure 130 and the gate oxide layer 120.

[0086] Reference Figure 7 In this embodiment, after etching the gate structure 130, the method further includes etching the gate oxide layer 120 exposed by the remaining gate structure 130.

[0087] In this embodiment, after etching the gate structure 130 on the outer wall 126 of any edge fin 125, the process further includes removing the mask layer 140. Removing the mask layer 140 prepares the material for subsequent processes. Specifically, the mask layer 140 can be removed after etching the exposed gate oxide layer 120 of the remaining gate structure 130, allowing the mask layer 140 to continue functioning as an etching mask during the etching of the gate oxide layer 120, thereby protecting the remaining gate structure 130 or other protective films (e.g., interlayer dielectric layers).

[0088] In this embodiment, an anisotropic dry etching process is adopted. During the etching process, the etching parameters corresponding to each film layer are adjusted to sequentially etch the gate structure 130 and the gate oxide layer 120. The etching controllability is high and the morphology quality of the etching profile is high.

[0089] It should be noted that in other embodiments, to save process steps and reduce the impact on the edge fins, the gate oxide layer may not be etched. It should also be noted that after etching the gate structure 130 on the outer wall 126 of any edge fin 125, the process further includes forming a second interlayer dielectric layer (not shown) covering the exposed edge fins 125 of the remaining gate structure 130. The second interlayer dielectric layer and the first interlayer dielectric layer constitute an interlayer dielectric layer, thereby providing a process basis for subsequent processes. Furthermore, in other embodiments, when the gate structure is a dummy gate structure, the second interlayer dielectric layer covers the exposed edge fins of the remaining gate structure, thereby preparing for the subsequent formation of the device gate structure and ensuring that the device gate structure still exposes a portion of the edge fins 125. Specifically, the second interlayer dielectric layer is formed after etching the exposed gate oxide layer 120 of the remaining gate structure 130. The material of the second interlayer dielectric layer is an insulating material. As an example, the material of the second interlayer dielectric layer is silicon oxide.

[0090] Figures 8 to 9 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention.

[0091] The similarities between the embodiments of the present invention and the foregoing embodiments will not be repeated here. The difference between the embodiments of the present invention and the foregoing embodiments is that in the step of providing a substrate (not shown), the number of transistor cell regions 200a is multiple.

[0092] In this embodiment, the transistors in each transistor cell region 200a share a common gate structure 230, while the gate structures 230 in adjacent transistor cell regions 200a are isolated from each other. Specifically, as shown... Figure 8 As shown, in the step of forming a gate structure 230 on the substrate, the gate structure 230 spans multiple transistor cell regions 200a. The forming method further includes: performing a gate cutting process on the gate structure 230 at the junction of adjacent transistor cell regions 200a, which is used to divide the gate structure 230 of adjacent transistor cell regions 200a in the extension direction of the gate structure 230, so that the gate structures 230 in adjacent transistor cell regions 200a are isolated from each other.

[0093] In this embodiment, the gate structure 230 spans multiple transistor cell regions 200a, which increases the process window for forming the gate structure 230, thereby improving the formation quality of the gate structure 230. In particular, as the feature size of integrated circuits continues to decrease, the effect of improving the formation quality of the gate structure 230 is significant when the gate structure 230 is a thin-film stacked structure (e.g., when the gate structure 230 is a metal gate structure). In this embodiment, the gate structure 230 is a device gate structure. Specifically, the device gate structure is a metal gate structure. Compared to the approach of first forming a pseudo-gate structure spanning multiple transistor cell regions, then performing gate cutting on the pseudo-gate structure at the boundary of adjacent transistor cell regions, and subsequently replacing the pseudo-gate structure with the device gate structure, this embodiment first forms the device gate structure and then cuts it. This improves the difficulty of forming the device gate structure in the region between the opening sidewall and adjacent fins, which is beneficial for improving the integrity of the device gate structure and increasing the process window for forming the device gate structure, thereby improving the performance and performance uniformity of the transistor. Moreover, the above method has high process compatibility and a low probability of negatively impacting transistor performance.

[0094] In other embodiments, the gate structure may also be a pseudo-gate structure, depending on process requirements.

[0095] As an example, in the transistor cell region 200a, the fin closest to the boundary of the adjacent transistor cell region 200a is the edge fin 225.

[0096] refer to Figure 9The gate structure 230 at the junction of adjacent transistor cell regions 200a is subjected to gate cutting processing, which is used to divide the gate structure 230 of adjacent transistor cell regions 200a in the extending direction of the gate structure 230.

[0097] The transistors in each transistor cell region 200a share a common gate structure 230. By performing gate cut processing on the gate structures 230 at the junction of adjacent transistor cell regions 200a, the gate structures 230 of each transistor cell region 200a are isolated from each other, thereby enabling the gate structure 230 to control the channel in the corresponding transistor cell region 200a independently.

[0098] In this embodiment, during the gate cutting process, the gate structure 230 on the outer wall 226 of any of the edge fins 225 is etched, removing at least a portion of the gate structure 230 on the outer wall 226. In the same step, etching the gate structure 230 on any of the edge fins 225 and gate cutting the gate structure 230 at the boundary of adjacent transistor cell regions 200a are performed, thereby avoiding the introduction of additional process steps and allowing the use of the same photomask, avoiding the need for additional photomasks. Therefore, introducing the step of etching the gate structure 230 on any of the edge fins 225 into the process flow has high compatibility with conventional process flows and minimal impact on manufacturing efficiency and process cost.

[0099] Specifically, the step of etching the gate structure 230 on the outer wall 226 of any of the edge fins 225 includes: forming a mask layer 240 on the top of the substrate and the gate structure 230, the mask layer 240 exposing the gate structure 230 on the outer wall 226 of any of the edge fins 225 and the gate structure 230 at the junction of adjacent transistor cell regions 200a; and etching the gate structure 230 exposed by the mask layer 240 using the mask layer 240 as a mask. For a detailed description of the mask layer 240 and the etching process of the gate structure 230, please refer to the corresponding description in the foregoing embodiments, and it will not be repeated here.

[0100] In this embodiment, the fin closest to the boundary of the adjacent transistor cell region 200a is designated as the edge fin 225. Therefore, during the gate cutting process, the gate structure 230 on the outer wall 226 near the boundary of the adjacent transistor cell region 200a is etched. The mask layer 240 typically has mask openings to expose the top of the gate structure 230 to be etched. Therefore, by etching the gate structure 230 on the outer wall 226 near the boundary of the adjacent transistor cell region 200a, it is only necessary to increase the opening size of the mask opening at the boundary of the adjacent transistor cell region 200a in the conventional gate cutting process to expose the gate structure 230 to be etched on the edge fin 225. With only minor modifications to the conventional gate cutting process, the etching of the gate structure 230 on the edge fin 225 can be achieved. Correspondingly, when designing the photomask, only the pattern and size of the photomask used for the gate cutting process need to be adjusted. In other embodiments, the area where the gate is cut off can be isolated from the area where the gate structure on the edge fin is etched, depending on process requirements.

[0101] In this embodiment, after etching the gate structure 230, the process may further include etching away the gate oxide layer 220 exposed by the remaining gate structure 230.

[0102] A detailed description of the method for forming the semiconductor structure can be found in the corresponding descriptions in the foregoing embodiments, and will not be repeated here.

[0103] Figure 10 This is a schematic diagram of another embodiment of the semiconductor structure formation method of the present invention.

[0104] The similarities between the embodiments of the present invention and the foregoing embodiments will not be repeated here. The difference between the embodiments of the present invention and the foregoing embodiments is that: after etching the gate structure on the outer sidewall 626 of any of the edge fins 625, the present invention further includes: using the top surface of the isolation layer 603 as the etching stop position, etching away the remaining exposed edge fins 625 of the gate structure (not shown) to reduce the width of the edge fins 625.

[0105] There is typically an etching selectivity between the fin and the isolation layer 603, making it easy to use the top surface of the isolation layer 603 as the etching stop position. In this embodiment, after etching the gate structure on the exposed edge fin 625 using a mask layer (not shown) as a mask, the gate oxide layer (not shown) and the edge fin 625 are etched further to reduce the width of the edge fin 625.

[0106] In this embodiment, after etching away the remaining exposed edge fin 625 of the gate structure, in the transistor cell region 600a, in a direction perpendicular to the extension direction of the fin 602, at the top surface position of the isolation layer 603, the edge fin 625 corresponding to the exposed outer wall 626 of the gate structure has a first bottom width W1, and the remaining fin 602 has a second bottom width W2. The first bottom width W1 is smaller than the second bottom width W2.

[0107] After etching the gate structure on the outer sidewall 626 of the edge fin 625, the gate structure does not cover the top and the two opposite sidewalls of the edge fin 625, and at least part of the outer sidewall 626 is exposed. Therefore, by etching away the edge fin 625 exposed by the remaining gate structure, the width of the edge fin 625 is reduced, thereby improving the gate structure's control over the channel in the remaining edge fin 625 and reducing leakage current.

[0108] Specifically, an anisotropic dry etching process is adopted, and the etching parameters corresponding to each film layer are adjusted during the etching process. The gate structure 630, gate oxide layer 620 and edge fin 625 can be etched sequentially, and the etching controllability is high and the morphology quality of the etching profile is high.

[0109] A detailed description of the method for forming the semiconductor structure can be found in the corresponding descriptions in the foregoing embodiments, and will not be repeated here.

[0110] Figure 11 This is the mask plate of the present invention. Figure 1 A schematic diagram of an embodiment.

[0111] The mask layout 500 includes: an active region layout 510, including a transistor cell region 500a for forming transistors, wherein the transistor cell region 500a has an active region pattern 515; and a fin layout 520, including a plurality of parallel fin patterns 525 located in the active region pattern 515, wherein, in a direction perpendicular to the extending direction of the fin pattern 525, the fin pattern 525 closest to the boundary of the transistor cell region 500a serves as an edge fin pattern 550, and the edge... The fin pattern 550 has an outer boundary 555 facing the boundary of the transistor cell region 500a; the gate pattern 530 includes a gate pattern 535 located in the transistor cell region 500a, the gate pattern 535 spanning the fin pattern 525 and orthogonal to the fin pattern 525; the gate cut-off pattern 540 includes a first gate cut-off pattern 541, the first gate cut-off pattern 541 covering the gate pattern 535 between any outer boundary 555 and the boundary of the transistor cell region 500a.

[0112] The fin pattern 525 is used to form fins, the edge fin pattern 550 is correspondingly used to form edge fins, the gate pattern 535 is used to form gate structures, and the first gate cut-off pattern 541 is used to define the etched area in the gate structure. Therefore, by adding the first gate cut-off pattern 541 to the mask pattern 500, when forming a semiconductor structure using the mask pattern 500, the gate structure on the outer wall of any edge fin (i.e., the sidewall of the edge fin facing the boundary of the transistor cell region) can be etched, at least removing a portion of the gate structure on the outer wall. Both the fin sidewall and the top can be used to provide the channel of the transistor. That is, the height and width of the fin covered by the gate structure will affect the effective channel width of the transistor. Correspondingly, by etching the gate structure on the outer wall of any edge fin, at least a portion of the gate structure on the outer wall is removed, reducing the sidewall area of ​​the edge fin covered by the gate structure. Thus, while ensuring normal operation of the transistor, the effective channel width of the fin can be reduced by adjusting the height of the exposed outer wall of the gate structure, thereby improving the flexibility of adjusting the effective channel width of the transistor.

[0113] The photomask layout 500 is used to fabricate the photomask required to form the semiconductor structure. In this embodiment, the layout of a standard cell is used as an example. The layout of the standard cell is retrieved from a standard cell library, which contains various types of standard cells with different heights.

[0114] The standard cell library contains standard cells used in semiconductor processes, and the layout of these standard cells typically follows minimum design rules. These various types of standard cells have different heights to meet different chip performance requirements. It should be noted that the height of the standard cells in the standard cell library is usually fixed to facilitate layout. Furthermore, the height of the standard cells in the standard cell library is typically measured in tracks. For example, the height of a standard cell can be 6 tracks, 6.5 tracks, 7.5 tracks, or 9 tracks.

[0115] It should also be noted that for logic circuits, the area of ​​the active region is determined by the height of the standard cell. For example, for a fin field-effect transistor, the height of the standard cell is determined by the number of fins that the corresponding active region can accommodate, and standard cells of different heights have corresponding power consumption and power characteristics. As an example, the 6-track standard cell is the smallest standard cell in the standard cell library.

[0116] In other embodiments, the mask layout can also be the layout after the layout design is completed.

[0117] It should be noted that while transistors formed in the same transistor cell region 500a share a common gate structure, each transistor cell region 500a is not limited to forming transistors of the same channel conductivity type. For example, one transistor cell region 500a can be used to form both NMOS and PMOS transistors; that is, one transistor cell region 500a can be used to form multiple transistors, with the NMOS and PMOS transistors sharing a common gate structure. In other embodiments, depending on the circuit design, each transistor cell region is used only to form transistors of the same channel conductivity type, and each transistor cell region is used only to form one transistor.

[0118] It should also be noted that each transistor cell region 500a has boundaries in all directions.

[0119] The active region layout 510 includes a plurality of active region patterns 515, which define areas on the wafer where active devices are formed. Each active region pattern 515 defines a transistor formation location in a direction perpendicular to the extending direction of the fin pattern 525.

[0120] In this embodiment, the number of fin patterns 525 in each active region pattern 515 is two.

[0121] Fin pattern 525 is used to form fins that provide channels for transistors. Specifically, when the gate structure covers the fins, the channel width provided by the fins is the sum of the fin width and twice the effective height of the fins. Therefore, the more fins corresponding to a transistor, the larger the channel width of the transistor.

[0122] Each transistor cell region 500a has a boundary in each direction. In the direction perpendicular to the extension direction of the fin pattern 525, the fin pattern 525 closest to the boundary of the transistor cell region 500a is an edge fin pattern 550, and the edge fin pattern 550 has an outer boundary 555 facing the boundary of the transistor cell region 500a.

[0123] The gate pattern 535 is used to form a gate structure. In semiconductor processing, the gate structure spans the fin and covers part of the top and part of the sidewalls of the fin. Therefore, the gate pattern 535 spans the fin pattern 525 in the active region pattern 515 and is orthogonal to the fin pattern 525 in the active region pattern 515.

[0124] In this embodiment, the transistor cell region 500a includes a plurality of active region patterns 515, and the transistors formed in the same transistor cell region 500a share a common gate structure. Therefore, in the transistor cell region 500a, the gate pattern 535 spans the plurality of active region patterns 515 and is orthogonal to the fin pattern 525 in the plurality of active region patterns 515, and the plurality of active region patterns 515 share a common gate pattern 535.

[0125] The first gate cut-off pattern 541 covers the gate pattern 535 between any outer boundary 555 and the boundary of the transistor cell region 500a. The first gate cut-off pattern 541 is used to define the etching position of the gate structure corresponding to the gate pattern 535, so that the gate structure of the target area is etched away in the semiconductor manufacturing process. Therefore, when forming a semiconductor structure using the mask 500, the gate structure on the outer wall of any edge fin can be etched, at least removing part of the gate structure on the outer wall, so that the sidewall area of ​​the edge fin covered by the gate structure is reduced. Thus, while ensuring the normal operation of the transistor, the effective channel width of the fin can be reduced by adjusting the height of the exposed outer wall of the gate structure, thereby improving the flexibility of adjusting the effective channel width of the transistor.

[0126] It should be noted that in the semiconductor manufacturing process, when the gate structure in the region corresponding to the first gate cut pattern 541 is etched using a photomask prepared by the gate cut pattern 540, the exposed gate structure region can be adjusted by adjusting the parameters of the photolithography process, thereby controlling the area of ​​the etched gate structure. For example, a portion of the gate structure on the outer wall can be removed; or, the entire gate structure on the outer wall can be removed; or, the entire gate structure on the outer wall can be removed, and a portion of the gate structure on the top of the edge fin can also be removed; or, the entire gate structure on the outer wall can be removed, and the gate structure on the top of the edge fin can also be removed.

[0127] It should also be noted that, Figure 11 Only one transistor cell region 500a is illustrated. In the actual mask layout 500, within the active region layout 510, the number of transistor cell regions 500a can be multiple. Since each transistor cell region 500a has boundaries in all directions, when there are multiple transistor cell regions 500a, adjacent transistor cell regions 500a have an intersection, which is also the boundary of the transistor cell region 500a.

[0128] As an example, when there are multiple transistor cell regions 500a, in the gate layout 530, the gate pattern 535 spans across the multiple transistor cell regions 500a and is orthogonal to the fin patterns 525 in the multiple transistor cell regions 500a. Accordingly, in this embodiment, the gate layout 530 also includes a second gate cut-off pattern 542, which covers the gate pattern 535 at the boundary of adjacent transistor cell regions 500a. In the semiconductor manufacturing process, the second gate cut-off pattern 542 is used to divide the gate structure of adjacent transistor cell regions 500a in the extension direction of the gate structure.

[0129] In this embodiment, the first gate cut-off pattern 541 and the second gate cut-off pattern 542 are located in the same gate cut-off pattern 540. Therefore, even after adding the first gate cut-off pattern 541 to the mask pattern, the increase in the photomask size can still be avoided. In other embodiments, depending on the actual design requirements, the gate cut-off pattern may also include a first sub-gate cut-off pattern and a second sub-gate cut-off pattern located on different layers. The first gate cut-off pattern is located in the first sub-gate cut-off pattern, and the second gate cut-off pattern is located in the second sub-gate cut-off pattern. That is, the first gate cut-off pattern and the second gate cut-off pattern are disposed in different photomasks.

[0130] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a plurality of parallel fins located on the substrate, the substrate including a transistor cell region for forming a transistor, wherein in the transistor cell region, the fins closest to the boundary of the transistor cell region in a direction perpendicular to the extension direction of the fins are designated as edge fins, and the edge fins have an outer sidewall facing the boundary of the transistor cell region. A gate structure is formed on the substrate that spans the fin, the gate structure covering a portion of the top and a portion of the sidewalls of the fin; The gate structure on the outer wall of any of the edge fins is etched to remove at least a portion of the gate structure on the outer wall.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of etching the gate structure on the outer wall of any of the edge fins, a portion of the gate structure on the outer wall is removed. Alternatively, remove the gate structure from the entire outer wall; Alternatively, the gate structure on the entire outer wall can be removed, and a portion of the gate structure on the top of the edge fin can also be removed; Alternatively, the gate structure on the entire outer wall can be removed, and the gate structure on the top of the edge fin can also be removed.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a gate structure across the fin on the substrate, the gate structure includes a pseudo-gate structure or a device gate structure.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The pseudo-gate structure includes a polycrystalline silicon gate structure or an amorphous silicon gate structure, and the device gate structure includes a metal gate structure.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the number of transistor cell regions is multiple; In the step of forming a gate structure across the fin on the substrate, the gate structure spans multiple transistor cell regions; The forming method further includes: performing a gate cutting process on the gate structure at the junction of adjacent transistor cell regions, for dividing the gate structure of adjacent transistor cell regions in the extending direction of the gate structure, wherein, during the gate cutting process, the gate structure on the outer wall of any of the edge fins is etched.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, In the transistor cell region, the fin closest to the boundary of the adjacent transistor cell region is called the edge fin; During the gate cutting process, the gate structure on the outer wall near the boundary of the adjacent transistor cell region is etched.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes: an isolation layer located on the substrate exposed by the fin, the isolation layer covering a portion of the sidewall of the fin; After etching the gate structure on the outer sidewall of any of the edge fins, the method further includes: using the top surface of the isolation layer as the etching stop position, etching away the edge fins exposed by the gate structure to reduce the width of the edge fins.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of etching the gate structure on the outer sidewall of any of the said edge fins includes: forming a mask layer on top of the substrate and the gate structure, the mask layer exposing the gate structure on the outer sidewall of any of the said edge fins; and etching the gate structure exposed by the mask layer using the mask layer as a mask. The formation method further includes: removing the mask layer.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the gate structure, the method further includes: forming a gate oxide layer on the top and sidewalls of the fin; In the step of forming the gate structure, the gate structure covers the gate oxide layer; In the step of etching the gate structure on the outer wall of any of the said edge fins, the gate oxide layer is used as the etching stop layer.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, An anisotropic dry etching process is used to etch the gate structure on the outer wall of any of the edge fins.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the base, the top width of the fin is greater than the bottom width of the fin in a direction perpendicular to the extension direction of the fin.

12. A semiconductor structure, characterized in that, Formed using the semiconductor structure formation method according to any one of claims 1 to 11, comprising: The substrate includes a substrate and a plurality of parallel fins located on the substrate, the substrate including a transistor cell region for forming a transistor, wherein in the transistor cell region, the fin closest to the boundary of the transistor cell region in a direction perpendicular to the extension direction of the fins is an edge fin, and the edge fin has an outer wall facing the boundary of the transistor cell region. A gate structure is located on the substrate and spans the fin, the gate structure covering a portion of the top and a portion of the sidewalls of the fin, wherein the gate structure exposes at least a portion of the outer sidewall of any of the edge fins.

13. The semiconductor structure as described in claim 12, characterized in that, The gate structure exposes a portion of the outer wall of any of the edge fins; Alternatively, the gate structure exposes the entire outer wall of any of the edge fins; Alternatively, the gate structure exposes the entire outer wall of any of the edge fins, and also exposes a portion of the top of the edge fin; Alternatively, the gate structure exposes the entire outer wall of any of the edge fins, and also exposes the top of the edge fin.

14. The semiconductor structure as claimed in claim 12, characterized in that, The number of transistor unit regions is multiple; In the transistor cell region, the fin closest to the boundary of the adjacent transistor cell region is called the edge fin; The gate structures in adjacent transistor cell regions are isolated from each other.

15. The semiconductor structure as described in claim 12, characterized in that, The substrate further includes: an isolation layer located on the substrate exposed by the fin, the isolation layer covering a portion of the sidewall of the fin; In the transistor cell region, in a direction perpendicular to the extension direction of the fins, the edge fins corresponding to the exposed outer wall of the gate structure have a first bottom width at the top surface of the isolation layer, and the remaining fins have a second bottom width at the top surface of the isolation layer, wherein the first bottom width is smaller than the second bottom width.

16. The semiconductor structure as claimed in claim 12, characterized in that, The gate structure is a device gate structure, which includes a metal gate structure.

17. The semiconductor structure as claimed in claim 12, characterized in that, The gate structure is a device gate structure, which includes a gate dielectric layer and a gate layer covering the gate dielectric layer.

18. The semiconductor structure as claimed in claim 12, characterized in that, The semiconductor structure further includes: a gate oxide layer located between the gate structure and the fin; or, the gate oxide layer located between the gate structure and the fin, and further extending to cover the exposed outer wall of the gate structure.

19. The semiconductor structure as claimed in claim 18, characterized in that, The material of the gate oxide layer includes one or both of silicon oxide and silicon oxynitride.

20. The semiconductor structure as claimed in claim 12, characterized in that, In a direction perpendicular to the extension direction of the fin, the top width of the fin is greater than the bottom width of the fin.

21. The semiconductor structure as claimed in claim 17, characterized in that, The material of the gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

22. The semiconductor structure as claimed in claim 17, characterized in that, The material of the gate layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

23. A photomask layout, characterized in that, include: An active region layout includes transistor cell regions for forming transistors, wherein the transistor cell regions have active region patterns; The fin pattern includes a plurality of parallel fin patterns located in the active region pattern. In a direction perpendicular to the extension direction of the fin pattern, the fin pattern closest to the boundary of the transistor cell region is designated as an edge fin pattern, and the edge fin pattern has an outer boundary facing the boundary of the transistor cell region. A gate layout, including a gate pattern located in the cell region, the gate pattern spanning the fin pattern and orthogonal to the fin pattern; The gate cut-off pattern includes a first gate cut-off pattern that covers the gate pattern between any outer boundary and the boundary of the transistor cell region.

24. The mask layout as described in claim 23, characterized in that, In the active region layout, there are multiple transistor cell regions; in the gate layout, the gate pattern spans multiple transistor cell regions and is orthogonal to the fin patterns in the multiple transistor cell regions. The gate layout also includes a second gate cut-off pattern, which covers the gate pattern at the boundary of adjacent transistor cell regions.

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