An in-chip multi-mode current detection method

Abstract

The application discloses a kind of in-chip multi-mode current detection methods, it is related to integrated circuit design field, the in-chip multi-mode current detection method of the present application includes the following steps: step 1, set the threshold current size of protection, and output corresponding threshold voltage;Step 2, according to the threshold voltage size setting protection voltage;Compared with prior art, the beneficial effects of the present application are: the present application chip inside according to chip package heat dissipation thermal resistance sets overcurrent protection maximum I0cpm, customer can also customize overcurrent protection current limiting value I0 according to actual use, the setting range of I0 can be from very small current to I0cpm, I0cpm has three optional settings, one of which is external high-precision resistance, programmable resistance in chip and current type DAC, the setting range of self-defined overcurrent protection current limiting value I0 is larger, accurate current detection can be carried out in the range from smaller current to I0 larger.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, specifically to a multi-mode current detection method within a chip. Background Technology

[0002] Traditional chip-level current sensing methods are typically used for internal current control or overcurrent protection within the chip, and usually target a specific current value.

[0003] Its current detection is limited to a specific current value and cannot detect the operating current status within the chip over a wide range, resulting in incomplete protection, which needs improvement. Summary of the Invention

[0004] The purpose of this invention is to provide an in-chip multi-mode current detection method to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A multi-mode current detection method within a chip includes the following steps:

[0007] Step 1: Set the protection threshold current I0 and output the corresponding threshold voltage V1;

[0008] Step 2: Set the protection voltage V0 according to the threshold voltage V1.

[0009] Step 3: Sample the chip power path current, convert it into the corresponding power voltage Vcs, compare the power voltage Vcs with the protection voltage V0, and output the comparison voltage Vocp;

[0010] Step 4 is used to select whether to trigger overcurrent protection based on the voltage magnitude of the comparison voltage Vocp within a set time.

[0011] As a further aspect of the present invention: In step 1: the threshold current I0 for protection is set by an external high-precision resistor, and the corresponding threshold voltage V1 is output by the protection setting circuit; the protection setting circuit includes comparator A0, MOSFET M0, MOSFET M1, MOSFET M2, and resistor R1. The non-inverting input of comparator A0 is connected to the reference voltage Vset, the inverting input of comparator A0 is connected to the external high-precision resistor and the source (S) of MOSFET M0, the gate (G) of MOSFET M0 is connected to the output of comparator A0, the drain (D) of MOSFET M0 is connected to the drain (D) of MOSFET M1, the gate (G) of MOSFET M1, and the gate (G) of MOSFET M2, the source (S) of MOSFET M1 is connected to the voltage Vdd and the source (S) of MOSFET M2, the drain (D) of MOSFET M2 is connected to one end of resistor R1, and the other end of resistor R1 is grounded.

[0012] As a further aspect of the present invention: In step 2: different threshold voltages V1 generate different protection voltages V0 through a voltage judgment and selection circuit; the voltage judgment and selection circuit includes a comparator A3, an input 2-to-1 multiplexer MUX, a comparator A1, a MOSFET M3, and a resistor R2. The non-inverting input of the comparator A3 is connected to the voltage V2, the inverting input of the comparator A3 is connected to the threshold voltage V1 and the first terminal of the input 2-to-1 multiplexer MUX, the second terminal of the input 2-to-1 multiplexer MUX is connected to the voltage Vdd, the output of the comparator A3 is connected to the third terminal of the input 2-to-1 multiplexer MUX, the fourth terminal of the input 2-to-1 multiplexer MUX is connected to the first non-inverting input of the comparator A1, the second non-inverting input of the comparator A1 is connected to the reference voltage Vref, the inverting input of the comparator A1 is connected to one end of the resistor R2 and the source (S) terminal of the MOSFET M3, the gate (G) terminal of the MOSFET M3 is connected to the output of the comparator A1, and the drain (D) terminal of the MOSFET M3 is connected to the voltage Vdd.

[0013] As a further embodiment of the present invention: In step 3: the power voltage Vcs and the comparison voltage Vocp are obtained through the current sampling and judgment circuit; the current sampling and judgment circuit includes resistor Rs, resistor R3a, resistor R3b, comparator A2, comparator A4, and resistor R4. One end of resistor Rs is connected to one end of resistor R3a and voltage Vin1, and the other end of resistor Rs is connected to one end of resistor R3b and voltage Vrs1. The other end of resistor R3a is connected to the non-inverting input of comparator A2, the inverting input of comparator A2 is connected to the other end of resistor R3b, the output of comparator A2 is connected to one end of resistor R4 and the inverting input of comparator A4, the non-inverting input of comparator A4 is connected to the protection voltage V0, and the other end of resistor R4 is grounded.

[0014] As a further aspect of the present invention: in step 4: the overcurrent protection decision circuit selects whether to trigger overcurrent protection; the overcurrent protection decision circuit includes an overcurrent protection decision unit and an oscillator, the first end of the overcurrent protection decision unit is connected to the output end of the current sampling decision circuit, the second end of the overcurrent protection decision unit is connected to the oscillator, and the third end of the overcurrent protection decision unit outputs the control signal Ocp-ind.

[0015] As a further aspect of the present invention: in step 1: an on-chip adjustment resistor is used instead of an off-chip high-precision resistor.

[0016] As a further aspect of the present invention: in step 1, an on-chip current-mode DAC (digital-to-analog converter) is used to replace the off-chip high-precision resistor.

[0017] Compared with the prior art, the beneficial effects of the present invention are: the chip of the present invention sets the maximum overcurrent protection value I0cpm according to the thermal resistance of the chip package heat dissipation. Customers can also customize the overcurrent protection current limit value I0 according to the actual use. The setting range of I0 can be from a very small current to I0cpm. I0cpm has three settings that can be selected: external high-precision resistor, on-chip programmable resistor and on-chip current-type DAC. The setting range of the custom overcurrent protection current limit value I0 is large, and accurate current detection can be performed from a small current to a large I0. Attached Figure Description

[0018] Figure 1 Circuit diagram for protection of the set circuit.

[0019] Figure 2 The circuit diagram for selecting the voltage determination circuit.

[0020] Figure 3 This is a graph showing the transmission relationship between the threshold voltage V1 and the protection voltage V0.

[0021] Figure 4 The circuit diagram is for the current sampling and judgment circuit.

[0022] Figure 5 This is a schematic diagram of overcurrent protection and overcurrent release.

[0023] Figure 6 This is a schematic diagram of an overcurrent protection decision circuit. Detailed Implementation

[0024] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0025] Please see Figures 1 to 6 A multi-mode current detection method within a chip includes the following steps:

[0026] Step 1: Set the protection threshold current I0 and output the corresponding threshold voltage V1;

[0027] Step 2: Set the protection voltage V0 according to the threshold voltage V1.

[0028] Step 3: Sample the chip power path current, convert it into the corresponding power voltage Vcs, compare the power voltage Vcs with the protection voltage V0, and output the comparison voltage Vocp;

[0029] Step 4 is used to select whether to trigger overcurrent protection according to the voltage magnitude of the comparison voltage Vocp within a set time.

[0030] In this embodiment: Please refer to Figure 1 , in Step 1: Set the threshold current magnitude I0 of the protection through an off-chip high-precision resistor, and output the corresponding threshold voltage V1 through the protection setting circuit; the protection setting circuit includes a comparator A0, a MOS transistor M0, a MOS transistor M1, a MOS transistor M2, and a resistor R1. The non-inverting input terminal of the comparator A0 is connected to the reference voltage Vset, the inverting input terminal of the comparator A0 is connected to the off-chip high-precision resistor and the S pole of the MOS transistor M0, the G pole of the MOS transistor M0 is connected to the output terminal of the comparator A0, the D pole of the MOS transistor M0 is connected to the D pole of the MOS transistor M1, the G pole of the MOS transistor M1, and the G pole of the MOS transistor M2. The S pole of the MOS transistor M1 is connected to the voltage Vdd and the S pole of the MOS transistor M2. The D pole of the MOS transistor M2 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded.

[0031] Connect an off-chip high-precision resistor to the Rset port, and the other end of the off-chip high-precision resistor is grounded. Then the current flowing through the MOS transistors M0 and M1 is Vset / Rset, the current flowing through M2 is N*Vset / Rset, and the threshold voltage V1 = (N*Vset*R1) / Rset. R1 is an on-chip resistor. Select a polycrystalline resistor with a low temperature coefficient, and then through trimming (on-chip trimming), the accuracy of the threshold voltage V1 is relatively high.

[0032] In this embodiment: Please refer to Figure 2 and 3 , in Step 2: Different threshold voltages V1 generate different protection voltages V0 through the voltage judgment selection circuit; the voltage judgment selection circuit includes a comparator A3, an input multiplexer MUX, a comparator A1, a MOS transistor M3, and a resistor R2. The non-inverting input terminal of the comparator A3 inputs the voltage V2, the inverting input terminal of the comparator A3 is connected to the threshold voltage V1 and the first terminal of the input multiplexer MUX. The second terminal of the input multiplexer MUX is connected to the voltage Vdd. The output terminal of the comparator A3 is connected to the third terminal of the input multiplexer MUX. The fourth terminal of the input multiplexer MUX is connected to the first non-inverting input terminal of the comparator A1. The second non-inverting input terminal of the comparator A1 is connected to the reference voltage Vref. The inverting input terminal of the comparator A1 is connected to one end of the resistor R2 and the S pole of the MOS transistor M3. The G pole of the MOS transistor M3 is connected to the output terminal of the comparator A1. The D pole of the MOS transistor M3 is connected to the voltage Vdd.

[0033] The threshold voltage V1 = (N*Vset*R1) / Rset. If V1 > V2, then the MUX selects the threshold voltage V1 as the output, that is, V1* = V1. If V1 < V2, then the MUX selects the voltage Vdd as the output, that is, V1* = Vdd.

[0034] The normal voltage V2 is usually set small enough, such as 50 mV, to solve the problem that the undefined V1* caused by the floating Rset. The comparator A1 is a three-input operational amplifier, using PMOS as the differential input stage amplifier. The Vref cannot be set too high. For a supply voltage Vdd of 2 - 3V, it is generally about 1V. Due to the high gain of the comparator A1, when V1* is less than 1V, V1* will replace Vref as the effective input of the non-inverting terminal. When V1* is greater than 1V, Vref will replace V1* as the effective input of the non-inverting terminal. Thus, the transfer waveforms of the protection voltage V0 and the threshold voltage V1 can be drawn, as Figure 3 shown. The overcurrent protection point can be set within the entire range of voltage from V2 to Vref. The typical dynamic range is about 1V / 50mV, 20 times.

[0035] In this embodiment: Please refer to Figure 4 , in step 3: The power voltage Vcs and the comparison voltage Vocp are obtained through the current sampling and judgment circuit. The current sampling and judgment circuit includes a resistor Rs, a resistor R3a, a resistor R3b, a comparator A2, a comparator A4, and a resistor R4. One end of the resistor Rs is connected to one end of the resistor R3a and the voltage Vin1. The other end of the resistor Rs is connected to one end of the resistor R3b and the voltage Vrs1. The other end of the resistor R3a is connected to the non-inverting terminal of the comparator A2. The inverting terminal of the comparator A2 is connected to the other end of the resistor R3b. The output terminal of the comparator A2 is connected to one end of the resistor R4 and the inverting terminal of the comparator A4. The non-inverting terminal of the comparator A4 is connected to the protection voltage V0. The other end of the resistor R4 is grounded.

[0036] The comparator A2 samples the current flowing from Vin1 to Vrs1 through the current sampling resistor Rs. The resistors R3a and R3b are usually completely matched with nearly equal resistance values. The comparator A2 amplifies the voltage across the sampling resistor Rs by a factor of R4 / R3a. Vcs = (R4 / R3a)*(Vin1 - Vrs1). The signal of the pre-stage protection voltage V0 is sent to the positive terminal of the comparator A4. If the negative terminal voltage Vcs > V0, then Vocp flips to a low level, and Vocp outputs an overcurrent protection indication signal. On the contrary, if Vcs < V0, then Vocp is at a high level, in the normal operating state.

[0037] In this embodiment: Please refer to Figure 5 and Figure 6 , in step 4: It is determined whether to trigger the overcurrent protection through the overcurrent protection decision circuit. The overcurrent protection decision circuit includes an overcurrent protection decision unit and an oscillator. The first terminal of the overcurrent protection decision unit is connected to the output terminal of the current sampling and judgment circuit. The second terminal of the overcurrent protection decision unit is connected to the oscillator. The third terminal of the overcurrent protection decision unit outputs a control signal Ocp-ind.

[0038] The oscillator, typically a ring oscillator or relaxation oscillator, is already operating before overcurrent protection is detected. It generates a Vosc signal for the overcurrent protection decision unit. During normal operation, Ocp_ind is high. When Vocp is low, overcurrent protection is initiated, and Vosc starts counting the time Vocp remains low. If Vocp flips to high during the counting process, the count is invalidated, and Ocp_ind remains high until the next Vocp flips low, at which point the counting restarts. If Vocp remains low without change until the count time reaches the set T0, Ocp_ind flips low, indicating an overcurrent condition. The chip enters overcurrent protection mode, shutting down the power path. When Vocp is high, the voltage across Rs drops to 0. After N times T0, the power path is restarted. If the power path is still in an overcurrent state, the overcurrent protection mode is entered again. This cycle repeats until the overcurrent condition is resolved.

[0039] In this embodiment: Please refer to Figure 1 In step 1: the on-chip adjustment resistor is used to replace the off-chip high-precision resistor.

[0040] If Rset uses the on-chip adjustment resistor, resistor R1 can be directly selected as a resistor of the same type without adjustment. The output voltage V1 = (N * Vset * R1) / Rset.

[0041] In this embodiment: Please refer to Figure 1 In step 1: the external high-precision resistor is replaced by an on-chip current-mode DAC (digital-to-analog converter).

[0042] Using an on-chip current-mode DAC (digital-to-analog converter), the current-mode DAC will generate a corresponding current I0, and the output voltage V1 = N*I0*R1.

[0043] The working principle of this invention is as follows: First, the threshold current I0 for protection is set, and the corresponding threshold voltage V1 is output. Second, the protection voltage V0 is set according to the threshold voltage V1. Further, the chip power path current is sampled and converted into a corresponding power voltage Vcs. The power voltage Vcs and the protection voltage V0 are compared, and a comparison voltage Vocp is output. Finally, based on the magnitude of the comparison voltage Vocp within a set time, overcurrent protection is selected to be triggered. The custom overcurrent protection current limit value I0 has a large setting range, allowing for precise current detection from a small current to a large I0, and enabling the detection of a wide range of internal chip current information.

[0044] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0045] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A multi-mode current detection method within a chip, characterized in that: The multi-mode current detection method within the chip includes the following steps: Step 1: Set the protection threshold current and output the corresponding threshold voltage; Step 2: Set the protection voltage according to the threshold voltage. Step 3: Sample the chip power path current, convert it into the corresponding power voltage, compare the power voltage with the protection voltage, and output the comparison voltage; Step 4 is used to select whether to trigger overcurrent protection based on the voltage magnitude of the comparison voltage within a set time. In step 2: different threshold voltages V1 generate different protection voltages V0 through the voltage judgment and selection circuit; the voltage judgment and selection circuit includes comparator A3, input 2-to-1 circuit MUX, comparator A1, MOSFET M3, and resistor R2. The non-inverting input of comparator A3 is connected to the input voltage V2, the inverting input of comparator A3 is connected to the threshold voltage V1, the first terminal of the input 2-to-1 circuit MUX, the second terminal of the input 2-to-1 circuit MUX is connected to the voltage Vdd, the output of comparator A3 is connected to the third terminal of the input 2-to-1 circuit MUX, the fourth terminal of the input 2-to-1 circuit MUX is connected to the first non-inverting input of comparator A1, the second non-inverting input of comparator A1 is connected to the reference voltage Vref, the inverting input of comparator A1 is connected to one end of resistor R2 and the source (S) terminal of MOSFET M3, the gate (G) terminal of MOSFET M3 is connected to the output of comparator A1, the drain (D) terminal of MOSFET M3 is connected to the voltage Vdd, and the source terminal of MOSFET M3 outputs the protection voltage V0.

2. The on-chip multi-mode current detection method according to claim 1, characterized in that, In step 1: The threshold current I0 for protection is set by an external high-precision resistor, and the corresponding threshold voltage V1 is output by the protection setting circuit. The protection setting circuit includes comparator A0, MOSFETs M0, M1, and M2, and resistor R1. The non-inverting input of comparator A0 is connected to the reference voltage Vset, the inverting input of comparator A0 is connected to the external high-precision resistor and the source (S) of MOSFET M0, the gate (G) of MOSFET M0 is connected to the output of comparator A0, the drain (D) of MOSFET M0 is connected to the drain (D) of MOSFET M1, the gate (G) of MOSFET M1, and the gate (G) of MOSFET M2, the source (S) of MOSFET M1 is connected to the voltage Vdd and the source (S) of MOSFET M2, the drain (D) of MOSFET M2 is connected to one end of resistor R1, and the other end of resistor R1 is grounded.

3. The chip-based multi-mode current detection method according to claim 1, characterized in that, In step 3: the power voltage Vcs and the comparison voltage Vocp are obtained through the current sampling and judgment circuit. The current sampling and judgment circuit includes resistors Rs, R3a, R3b, comparator A2, comparator A4, and resistor R4. One end of resistor Rs is connected to one end of resistor R3a and voltage Vin1. The other end of resistor Rs is connected to one end of resistor R3b and voltage Vrs1. The other end of resistor R3a is connected to the non-inverting input of comparator A2. The inverting input of comparator A2 is connected to the other end of resistor R3b. The output of comparator A2 is connected to one end of resistor R4 and the inverting input of comparator A4. The non-inverting input of comparator A4 is connected to the protection voltage V0. The other end of resistor R4 is grounded. The output of comparator A4 outputs the control voltage Vocp.

4. The on-chip multi-mode current detection method according to claim 1, characterized in that, In step 4: the overcurrent protection decision circuit selects whether to trigger overcurrent protection; the overcurrent protection decision circuit includes an overcurrent protection decision unit and an oscillator. The first end of the overcurrent protection decision unit is connected to the output end of the current sampling decision circuit, the second end of the overcurrent protection decision unit is connected to the oscillator, and the third end of the overcurrent protection decision unit outputs the control signal Ocp-ind.

5. The multi-mode current detection method within a chip according to claim 2, characterized in that, In step 1: the on-chip adjustment resistor is used to replace the off-chip high-precision resistor.

6. The on-chip multi-mode current detection method according to claim 2, characterized in that, In step 1: the external high-precision resistor is replaced by an on-chip current-mode DAC.

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