A method of evaluating a probe card

Abstract

The application provides a kind of probe card evaluation method, through the accurate measurement of the voltage and displacement between the upper and lower poles of tungsten and copper contained in the N*N piezoelectric ceramic components of piezoelectric ceramic force sensor array distributed in the center position of the wafer to be measured, and the probe needle position, flatness and elastic coefficient are obtained by using the positive piezoelectric effect calculation, whether the change range of the three parameters is in the allowable change range to fully evaluate the health status of all probes of the probe card. The application avoids the problem that the probe card may cause probe displacement, deformation and other problems that are difficult to meet the detection requirements due to wear, contact or improper operation and other reasons after being used for many times during CP test. At the same time, after fully evaluating the health status of the probe card, the probe card with healthy status can be used for each special situation without re-producing the probe card, thereby avoiding the increase of production cost, test time cost and the occurrence of test low good problem.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit testing, and in particular to a method for evaluating probe cards. Background Technology

[0002] A probe card is an interface between the chip under test (DUT) and the testing equipment in circuit testing (CP). The working principle of a probe card is to use probes on the card to directly contact the pads on the chip, creating a test path between the tester and the probe card. This allows for signal transmission, enabling the identification of chip signals and the screening out of defective chips.

[0003] During CP testing, the lifespan of a probe card ranges from hundreds of thousands to millions of cycles. During use, wear, contact issues, or improper operation can cause probe displacement or deformation, making it difficult to meet testing requirements. Remanufacturing probe cards for each specific situation would not only increase production costs but also test time. Therefore, probes require regular maintenance and upkeep; otherwise, test results will be suboptimal.

[0004] Changes in probe position (X, Y) can cause probe mark displacement, which means that the repeatability of probe card tests will be affected. Flatness exceeding 25μm can lead to poor contact between high-position probes and the wafer, or damage to the pads by low-position probes. Probe contact pressure is the force applied by the probe on the contact surface. The probe's elastic modulus affects the contact pressure; too high a contact pressure will damage the pads, while too low a contact pressure will not penetrate the oxide layer on the pad surface, resulting in unreliable test results and thus affecting test efficiency. Summary of the Invention

[0005] The purpose of this invention is to provide a method for evaluating probe cards, in order to solve the problems that in the current CP testing process, a probe card may be displaced or deformed due to wear, contact or improper operation, making it difficult to meet the testing requirements. If a probe card is remade for each special case, it will not only increase the production cost, but also increase the testing time cost.

[0006] To address the aforementioned technical problems, this invention provides a method for evaluating probe cards, comprising the following steps:

[0007] Provide a wafer to be tested, and perform wafer testing on the wafer to be tested;

[0008] During the wafer testing process, three parameters are obtained: probe position, flatness, and elasticity coefficient.

[0009] The health status of all probes on the probe card used in the wafer testing process is assessed based on the three parameters mentioned above.

[0010] Furthermore, the wafer testing system may include: a tester, a lifting platform, a circuit board, a fixing ring, a probe cantilever support ring, and multiple test probes; wherein,

[0011] The lifting platform is used to carry and move the wafer to be tested;

[0012] The circuit board is equipped with a test circuit for electrical testing of the internal condition of the chip on the wafer.

[0013] The probe cantilever support ring is fixed to the bottom of the circuit board by the fixing ring; and,

[0014] Multiple test probes are fixed to the bottom of a probe cantilever support ring. The tips of the test probes are used to contact the pads on at least one chip under test on the wafer under test. When the contact occurs, the probes form a needle mark on the pads on the surface of the wafer under test.

[0015] Furthermore, the center of the wafer under test is provided with a piezoelectric ceramic force sensor array containing N*N piezoelectric ceramic components, where N≥3.

[0016] Furthermore, the size of the piezoelectric ceramic sensor array is the same as the size of the pads on the chip under test, and the size range of the piezoelectric ceramic sensor array can be 50μm*50μm to 90μm*90μm.

[0017] Furthermore, the piezoelectric ceramic assembly may include: an insulating base of a predetermined height, and tungsten, piezoelectric ceramic, and copper components stacked sequentially from top to bottom on the insulating base.

[0018] Furthermore, the size range of the piezoelectric ceramic can be 20*20*10μm to 30*30*10μm.

[0019] Furthermore, in the piezoelectric ceramic assembly, the tungsten is the upper electrode and the copper is the lower electrode; the step of obtaining the three parameters of probe position, flatness and elastic coefficient during the wafer testing process includes: reading the voltage and displacement between the upper and lower electrodes of the piezoelectric ceramic assembly through the wafer testing system, and calculating the three parameters of probe position, flatness and elastic coefficient using the positive piezoelectric effect of the piezoelectric ceramic.

[0020] Furthermore, the allowable variation range of the parameter probe position can be -6μm to 6μm.

[0021] Furthermore, the allowable variation range of the flatness parameter can be -25μm to 25μm.

[0022] Furthermore, the elastic modulus of the tungsten and rhenium-tungsten can be 4 × 10⁻⁶. -4 N / μm~1×10 -3 The elastic modulus of beryllium copper and palladium copper-silver alloys can be 2 × 10 N / μm. -4 N / μm~6.4×10 -4 N / μm.

[0023] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0024] In this invention, a method for evaluating a probe card is proposed. First, the wafer to be tested is subjected to wafer testing using a wafer testing system. Then, during the wafer testing process, three parameters are obtained: probe position, flatness, and elasticity coefficient. Ideally, the health status of all probes on the probe card used in the wafer testing process is evaluated based on these three parameters. This invention precisely measures the voltage and displacement between the upper and lower tungsten and copper plates of N*N piezoelectric ceramic components distributed at the center of the wafer under test. The three parameters—probe position, flatness, and elasticity coefficient—are calculated using the positive piezoelectric effect of the piezoelectric ceramics. The health status of all probes on the probe card is then fully evaluated by checking whether the variation range of these three parameters is within the allowable range.

[0025] Therefore, this avoids problems during CP testing, such as probe card wear, contact issues, or improper operation that could lead to probe displacement or deformation, making it difficult to meet testing requirements. Furthermore, by fully assessing the health status of the probe cards, healthy cards can be used for each specific situation without the need for remanufacturing, thus avoiding increased production costs, testing time costs, and the occurrence of low-yield testing issues. Attached Figure Description

[0026] Figure 1 This is a flowchart illustrating the testing method for a probe card according to an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of the piezoelectric ceramic force sensor array distributed at the center of the wafer under test during the testing process of the probe card evaluation method provided in one embodiment of the present invention;

[0028] Figure 3 This is a schematic cross-sectional view of the piezoelectric ceramic component during the testing process of the probe card evaluation method provided in one embodiment of the present invention.

[0029] Among them, the appendix Figure 3 The markings are as follows:

[0030] 100 - Wafer to be tested; 110 - Insulating base;

[0031] 120 - Lower electrode plate; 130 - Piezoelectric ceramic;

[0032] 140 - Upper plate. Detailed Implementation

[0033] As described in the background section, a probe card is the interface between the chip under test (CUT) and the testing equipment in circuit testing (CP). The working principle of a probe card is to use the probes on the card to directly contact the pads on the chip, creating a test path between the tester and the probe card to achieve signal transmission. This allows the chip signal to be extracted, and defective chips to be screened out.

[0034] During CP testing, the lifespan of a probe card ranges from hundreds of thousands to millions of cycles. During use, wear, contact issues, or improper operation can cause probe displacement or deformation, making it difficult to meet testing requirements. Remanufacturing probe cards for each specific situation would not only increase production costs but also test time. Therefore, probes require regular maintenance and upkeep; otherwise, test results will be suboptimal.

[0035] Changes in probe position (X, Y) can cause probe mark displacement, which means that the repeatability of probe card tests will be affected. Flatness exceeding 25μm can lead to poor contact between high-position probes and the wafer, or damage to the pads by low-position probes. Probe contact pressure is the force applied by the probe on the contact surface. The probe's elastic modulus affects the contact pressure; too high a contact pressure will damage the pads, while too low a contact pressure will not penetrate the oxide layer on the pad surface, resulting in unreliable test results and thus affecting test efficiency.

[0036] Therefore, the purpose of this invention is to provide a method for evaluating probe cards, in order to solve the problem that in the current CP testing process, a probe card may be displaced or deformed due to wear, contact or improper operation, making it difficult to meet the testing requirements. If a probe card is remade for each special case, it will not only increase the production cost, but also increase the testing time cost.

[0037] For example, refer to Figure 1 As shown, the evaluation method for a probe card includes the following steps:

[0038] Step S100: Provide a wafer to be tested and perform wafer testing on the wafer to be tested;

[0039] Step S200: During the wafer testing process, three parameters are obtained: probe position, flatness, and elasticity coefficient.

[0040] Step S300: Assess the health status of all probes on the probe card used in the wafer testing process based on the three parameters.

[0041] Specifically, in the probe card evaluation method proposed in this invention, firstly, the wafer to be tested is subjected to wafer testing using a wafer testing system; then, during the wafer testing process, three parameters are obtained: probe position, flatness, and elastic coefficient; preferably, the health status of all probes on the probe card used in the wafer testing process is evaluated based on these three parameters. This invention precisely measures the voltage and displacement between the upper and lower tungsten and copper plates of the N*N piezoelectric ceramic components contained in the piezoelectric ceramic force sensor array distributed at the center of the wafer to be tested, and calculates the three parameters—probe position, flatness, and elastic coefficient—using the positive piezoelectric effect of the piezoelectric ceramic. The health status of all probes on the probe card is fully evaluated by checking whether the variation range of these three parameters is within the allowable range. Therefore, it avoids the problem that probe card wear, contact issues, or improper operation after repeated use during CP testing may lead to probe displacement or deformation, making it difficult to meet testing requirements. Meanwhile, by fully assessing the health status of the probe cards, healthy probe cards can be used for each special case without having to remake them, thereby avoiding increased production costs, testing time costs, and the occurrence of low-yield testing problems.

[0042] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the probe card evaluation method proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention can also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0043] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0044] The following section provides a detailed description of the testing method for the probe card provided by this invention. For specific details, please refer to... Figures 2-3 As shown, Figure 2 This is a schematic diagram of the piezoelectric ceramic force sensor array distributed at the center of the wafer under test during the testing process of the probe card evaluation method provided in one embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of the piezoelectric ceramic assembly during the testing process of the probe card evaluation method provided in one embodiment of the present invention. The probe card evaluation method may include the following steps:

[0045] In step S100, please refer to the following for details. Figure 2 A wafer 100 to be tested is provided, comprising a plurality of chips to be tested. Specifically, in this embodiment, the material of the wafer is selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the wafer may also be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon carbon germanium (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors; the wafer may also be other semiconductor materials such as a ceramic substrate of alumina, quartz, or glass substrate. Exemplarily, in this embodiment, the wafer is silicon.

[0046] A piezoelectric ceramic force sensor array containing N*N piezoelectric ceramic components is distributed at the center of the wafer 100 under test, where N ≥ 3. The size of the piezoelectric ceramic array is approximately the same as the size of the pads on the chip under test. The size of the piezoelectric ceramic sensor array ranges from 50μm*50μm to 90μm*90μm. For example, in this embodiment, preferably, N = 3, the piezoelectric ceramic force sensor array contains 3*3 piezoelectric ceramic components, each voltage measurement channel is independent and numbered from 1 to 9, and the corresponding size of the piezoelectric ceramic sensor array is 60μm*60μm.

[0047] Each square in the piezoelectric ceramic sensor array represents a piezoelectric ceramic component, and a detailed structural diagram of the piezoelectric ceramic component can be found in [reference needed]. Figure 3 The array includes: an insulating base 110 of a predetermined height, and an upper electrode plate 140, a piezoelectric ceramic 130, and a lower electrode plate 120 stacked sequentially from top to bottom on the insulating base 110. Exemplarily, in this embodiment, the upper electrode plate 140 is made of tungsten or rhenium-tungsten; the lower electrode plate 120 is made of copper, beryllium copper, or a palladium-copper-silver alloy. Specifically, in this embodiment, the upper electrode plate 140 is made of tungsten, and the lower electrode plate 120 is made of copper. Therefore, the upper and lower electrodes of each component in the piezoelectric ceramic sensor array are connected by tungsten and copper wiring to lead out voltage signals. The size of the piezoelectric ceramic ranges from 20*20*10μm to 30*30*10μm. In this embodiment, preferably, the size of the piezoelectric ceramic is 20*20*10μm; correspondingly, the size of the insulating base is 20*20*200μm. Specifically, the piezoelectric ceramic is lead zirconate titanate piezoelectric ceramic, which is both an elastic body and a dielectric. When physical pressure is applied to the piezoelectric material, the electric dipole moment within the material will shorten due to compression. At this time, in order to resist this change, the piezoelectric material will generate equal amounts of positive and negative charges on opposite surfaces of the material to maintain its original shape. When the external force is removed, the crystal returns to its uncharged state. This is the positive piezoelectric effect of the piezoelectric material. The positive piezoelectric effect is essentially the conversion of mechanical energy into electrical energy. The amount of charge generated by the crystal under force is proportional to the magnitude of the external force. The inverse piezoelectric effect is the opposite of the positive piezoelectric effect. It can convert electrical energy into mechanical energy and control the deformation of the object through an electric field.

[0048] In step S200, continue to refer to Figure 2 and Figure 3A wafer under test (DUT) with a piezoelectric ceramic force sensor array composed of the piezoelectric ceramic components is placed in a wafer testing system for testing. The wafer testing system includes: a tester, a lifting platform, a circuit board, a fixing ring, a probe cantilever support ring, and multiple test probes. The lifting platform is used to carry and move the DUT. The circuit board contains test circuitry for electrical detection of the internal condition of the chips on the wafer. The probe cantilever support ring is fixed to the bottom of the circuit board by the fixing ring. Multiple test probes are fixed to the bottom of the probe cantilever support ring, and the tips of the test probes are used to contact the pads on at least one chip under test on the DUT, forming a needle mark on the pads on the surface of the DUT when contact occurs. Exemplarily, in this embodiment, the DUT is placed at the center of the lifting platform, which can rise or fall at a uniform speed. The probe card is located directly above the piezoelectric ceramic components in the piezoelectric ceramic force sensor array at the center of the DUT. Specifically, for the same product, the coordinates of each probe are fixed. The lifting platform starts from zero and moves horizontally along the coordinates until the center of the piezoelectric ceramic force sensor array is directly below a probe. Then, it rises at a constant speed (in this embodiment, it rises at a constant speed of 5μm increments) until the probe contacts the piezoelectric ceramic component. The lifting platform continues to rise by about 50μm, causing the piezoelectric ceramic to be compressed. The voltage and displacement between the upper and lower plates of the tungsten and copper electrodes are read by a testing instrument (the maximum voltage is approximately 30V). After the first probe is tested, the lifting platform descends to zero and then moves to directly below the second probe for precise measurement. This testing process is repeated until all probes are tested.

[0049] In step S300, voltage-displacement data are obtained during the test. Utilizing the positive piezoelectric effect of the piezoelectric ceramic, specifically, the known pressure / voltage relationship is... Where t is the thickness of the piezoelectric ceramic, g 33F is a constant, F is the applied pressure, and A is the area of ​​the piezoelectric ceramic. These values ​​can be converted to obtain a linear curve of pressure versus displacement. The x-axis at the starting point of the curve can be used to calculate the probe height, and further, the flatness of the probe card can be calculated. The slope of the curve, ΔF / ΔL, is the elastic coefficient. Based on the performance of the probe position, flatness, and elastic coefficient, the health status of all probes on the entire probe card can be fully assessed. For example, in this embodiment, the allowable variation range of the parameter probe position is -6μm to 6μm, specifically -6μm, -5μm, -4μm, -3μm, -2μm, -1μm, 1μm, 2μm, 3μm, 4μm, 5μm, and 6μm, any two of the above numerical ranges; the allowable variation range of the parameter flatness is -25μm to 25μm, specifically -25μm, -24μm, -23μm, -22μm, -21μm, -20μm, -19μm, -18μm, -17μm, - The thicknesses are 16μm, -15μm, -14μm, -13μm, -12μm, -11μm, -10μm, -9μm, -8μm, -7μm, -6μm, -5μm, -4μm, -3μm, -2μm, -1μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, and 25μm. The elastic modulus of the tungsten and rhenium-tungsten is 4×10⁻⁶. -4 N / μm~1×10 -3 N / μm; while the elastic modulus of beryllium copper and palladium copper-silver alloys is 2×10 N / μm. -4 N / μm~6.4×10 -4 N / μm, specifically, 2×10 -4 N / μm, 3×10 -4 N / μm, 4×10 - 4 N / μm, 5×10 -4 N / μm, 6×10 -4 N / μm, 6.1×10 -4 N / μm, 6.2×10 -4 N / μm, 6.3×10 -4 N / μm and 6.4×10 -4 N / μm. The changes in needle position, flatness, and elastic coefficient are calculated using the positive piezoelectric effect formula of the piezoelectric ceramic to determine whether they are within the allowable range of each parameter, thus enabling a comprehensive assessment of the health status of all probes on the entire probe card.

[0050] In summary, the proposed method for evaluating a probe card involves several steps. First, the wafer under test is tested using a wafer testing system. Then, during the wafer testing process, three parameters are obtained: probe position, flatness, and elasticity coefficient. Finally, the health status of all probes on the probe card used in the wafer testing process is assessed based on these three parameters. This invention precisely measures the voltage and displacement between the tungsten and copper upper and lower plates of the N*N piezoelectric ceramic components in a piezoelectric ceramic force sensor array located at the center of the wafer under test. The probe position, flatness, and elasticity coefficient are calculated using the positive piezoelectric effect of the piezoelectric ceramics. The health status of all probes on the probe card is then fully evaluated by checking whether the variation range of these three parameters is within the allowable range. Therefore, this method avoids the problems that may arise during CP testing, such as probe displacement or deformation due to wear, contact issues, or improper operation after repeated use, which can lead to failure to meet testing requirements. Meanwhile, by fully assessing the health status of the probe cards, healthy probe cards can be used for each special case without having to remake them, thereby avoiding increased production costs, testing time costs, and the occurrence of low-yield testing problems.

[0051] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0052] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0053] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for evaluating a probe card, characterized in that, Includes the following steps: Provide a wafer to be tested, and perform wafer testing on the wafer to be tested; During the wafer testing process, three parameters are obtained: probe position, flatness, and elasticity coefficient. The health status of all probes on the probe card used in the wafer testing process is assessed based on the three parameters mentioned above. The wafer under test is equipped with a piezoelectric ceramic force sensor array containing N*N piezoelectric ceramic components, where N≥3; In the piezoelectric ceramic assembly, tungsten is the upper electrode and copper is the lower electrode. The steps for obtaining the three parameters of probe position, flatness, and elastic coefficient during the wafer testing process include: reading the voltage and displacement between the upper and lower plates of the piezoelectric ceramic component through the wafer testing system, converting them into a linear curve of pressure and displacement of the piezoelectric ceramic, and calculating the three parameters of probe position, flatness, and elastic coefficient using the positive piezoelectric effect of the piezoelectric ceramic.

2. The testing method for the probe card as described in claim 1, characterized in that, The wafer testing system includes: a tester, a lifting platform, a circuit board, a fixing ring, a probe cantilever support ring, and multiple test probes; wherein... The lifting platform is used to carry and move the wafer to be tested; The circuit board is equipped with a test circuit for electrical testing of the internal condition of the chip on the wafer. The probe cantilever support ring is fixed to the bottom of the circuit board by the fixing ring; and, Multiple test probes are fixed to the bottom of a probe cantilever support ring. The tips of the test probes are used to contact the pads on at least one chip under test on the wafer under test. When the contact occurs, the probes form a needle mark on the pads on the surface of the wafer under test.

3. The testing method for the probe card as described in claim 1, characterized in that, The size of the piezoelectric ceramic sensor array is the same as the size of the pads on the chip under test, and the size range of the piezoelectric ceramic sensor array is 50μm*50μm~90μm*90μm.

4. The testing method for the probe card as described in claim 1, characterized in that, The piezoelectric ceramic assembly includes: an insulating base of a predetermined height, and tungsten, piezoelectric ceramic, and copper components stacked sequentially from top to bottom on the insulating base.

5. The testing method for the probe card as described in claim 4, characterized in that, The size range of the piezoelectric ceramic is 20*20*10μm~30*30*10μm.

6. The testing method for the probe card as described in claim 1, characterized in that, The allowable variation range for the probe needle position is -6μm to 6μm.

7. The testing method for the probe card as described in claim 1, characterized in that, The allowable variation range for the flatness parameter is -25μm to 25μm.

8. The testing method for the probe card as described in claim 4, characterized in that, The elastic modulus of the tungsten and rhenium-tungsten is 4 × 10⁻⁶. -4 N / μm ~ 1×10 -3 The elastic modulus of beryllium copper and palladium copper-silver alloy is 2 × 10 N / μm. -4 N / μm ~6.4×10 -4 N / μm.

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