A low-power high-linearity analog baseband circuit with variable gain and bandwidth

Abstract

The application relates to a low-power-consumption high-linearity analog baseband circuit with variable gain and bandwidth, which comprises a variable gain amplifier with a built-in DC offset elimination loop and a bandwidth-reconfigurable low-pass filter. The variable gain amplifier is located at the first stage, the second stage and the last stage of the analog baseband, and is used for amplifying the output signal of a mixer, so that a 6-66dB gain control range is realized. The low-pass filter is located at the third stage as a whole, adopts four second-order units to realize an eight-order Butterworth response, is used for filtering the output signal of the mixer, and controls the bandwidth of the filter by adjusting the capacitance value, so that five cut-off frequencies of 500kHz, 1MHz, 3MHz, 8MHz and 15MHz are realized. The analog baseband circuit has the characteristics of low power consumption, high linearity and accurate gain control.

Description

Technical Field

[0001] This invention relates to the field of millimeter-wave radar technology, and in particular to a low-power, high-linearity analog baseband circuit with variable gain and bandwidth. Background Technology

[0002] In recent years, millimeter-wave radar has developed rapidly due to its advantages such as low cost and robustness to extreme weather conditions. Currently, research on millimeter-wave radar mainly focuses on the 77 GHz to terahertz band. Higher operating frequencies allow for higher resolution and a more compact footprint, which is beneficial for cost reduction and increased integration. Furthermore, CMOS technology, due to its low cost, low power consumption, and high integration, is increasingly being applied to advanced radar systems. Frequency-modulated continuous wave (FMCH) radar is commonly used in millimeter-wave radar to reduce circuit complexity and power consumption.

[0003] Millimeter-wave radar receivers mainly consist of a receiving antenna, a low-noise amplifier, a mixer, and analog baseband circuitry. The analog baseband circuitry typically includes a variable gain amplifier and filters. The variable gain amplifier is used to adjust the amplitude of input signals of different strengths and can be divided into open-loop and closed-loop structures. Open-loop structures generally have a large bandwidth but poor linearity, while closed-loop structures generally have high linearity but small bandwidth. During signal transmission, DC offset components often occur. These DC offset components mainly originate from the mixing of the signal leaked from the transmitting antenna and the local oscillator signal, as well as mismatches generated by the analog baseband itself. DC offset cancellation circuits with continuous-time negative feedback structures are typically used to reduce this. Filters are used to filter out out-of-band signals and interference. They have reconfigurable bandwidth to adapt to different radar detection ranges and often employ low-power, high-bandwidth Gm-C structures or high-linearity active RC structures.

[0004] When configuring the cascading order of variable gain amplifiers and filters, a trade-off must be struck between the linearity and noise performance of the analog baseband. Distributing the gain in the pre-stage of the analog baseband can effectively suppress noise, but it places higher demands on the linearity of the filter. On the other hand, distributing the gain in the post-stage of the analog baseband can alleviate the linearity requirements of the filter, but it results in poorer noise suppression. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and propose a low-power, high-linearity analog baseband circuit with variable gain and bandwidth, featuring reconfigurable gain and bandwidth, low power consumption, and high linearity.

[0006] The technical problem solved by this invention is achieved through the following technical solution:

[0007] A low-power, high-linearity analog baseband circuit with variable gain and bandwidth is characterized by comprising a variable gain amplifier with an embedded DC offset cancellation loop and a low-pass filter with reconfigurable bandwidth. The variable gain amplifier with the embedded DC offset cancellation loop is located in the first, second, and last stages, and is used to amplify the signal output from the mixer and eliminate DC offset generated from the analog baseband preamplifier stage and itself. The low-pass filter is located in the third stage, and its bandwidth is controlled by adjusting the capacitor value for signal filtering.

[0008] Furthermore, the variable gain amplifier with embedded DC offset cancellation loop includes a variable gain amplifier core circuit, a DC offset cancellation circuit, and a common-mode feedback circuit. The variable gain amplifier core circuit is a two-stage fully differential structure. The first stage input transistor is a PMOS pair, whose source terminal is simultaneously connected to the source negative feedback resistor, the drain terminal of the PMOS current source, and the source terminal of the diode-connected PMOS transistor. Its drain terminal is simultaneously connected to the NMOS current source, the drain terminal of the DC offset circuit feedback transistor, the gate terminal of the local feedback NMOS transistor, and the gate terminal of the second stage input transistor. The gate terminal and drain terminal of the diode-connected PMOS transistor are connected to the drain terminal of the NMOS feedback transistor. The second stage is a common-source amplifier with a current source load, and the gate terminal of the current source load is controlled by the output of the common-mode feedback circuit.

[0009] Furthermore, the input of the DC offset cancellation circuit is the output of the core circuit of the variable gain amplifier. It is connected to the gate of the PMOS input pair in the DC offset circuit amplifier through a resistor. The source of the PMOS pair is connected to the tail current source, and the drain is connected as the output of the DC offset circuit to the diode-type NMOS load and the cross-coupled negative resistance pair. The output is connected to the gate of the DC offset feedback transistor in the core circuit of the variable gain amplifier.

[0010] Furthermore, the common-mode feedback circuit has a two-stage structure. Its input is the output of the core circuit of the variable gain amplifier, which is connected to the gate of one PMOS input transistor in the error amplifier through a resistor. The gate of the other PMOS input transistor is connected to the reference level. The source terminals of these two PMOS input transistors are connected to the tail current source, and the drain terminals are connected to the single-ended output NMOS current mirror load. The second stage of the common-mode feedback circuit is a common-source amplifier with a diode MOS load. The gate and drain terminals of the diode MOS load are connected as the output of the second stage to the gate of the common-mode feedback control transistor in the core circuit of the variable gain amplifier. A series resistor and capacitor are connected between the two output stages of the common-mode feedback circuit to generate a zero point to compensate for the common-mode loop stability of the variable gain amplifier.

[0011] Furthermore, the resistors in the DC offset circuit are MOS transistors operating in the subthreshold region to reduce the chip area.

[0012] Moreover, the variable gain amplifier achieves gain control by adjusting the resistance value of the source negative feedback resistor.

[0013] Furthermore, the bandwidth-reconfigurable low-pass filter has an eighth-order Butterworth response and is composed of four cascaded second-order units, used to filter out-of-band signals and interference; the input of the low-pass filter is the output of the second-stage variable gain amplifier, and its output is connected to the input of the last-stage variable gain amplifier.

[0014] Furthermore, the second-order unit is based on a pseudo-differential form of a flip-flop voltage follower structure, and on this basis, three control bandwidth capacitors, two neutralizing capacitors, and a level shifting circuit are introduced; the control bandwidth capacitors are respectively connected across the source and drain terminals of the FVF input transistor and between the differential output terminals; the two MOSFETs are cross-coupled between the input and output of the second-order unit as neutralizing capacitors; the level shifting circuit includes a diode-connected MOSFET and its bias current source, which is used to improve the saturation voltage margin of the FVF input transistor, wherein the gate terminal of the diode-connected MOSFET is connected to the drain terminal of the FVF input transistor, and the source terminal is connected to the gate of the feedback transistor in the FVF.

[0015] Furthermore, the FVF structure consists of three MOS transistors: an input transistor, a feedback transistor, and a MOS transistor that serves as a bias current source. The input transistor and the feedback transistor are of the same type, while the bias current source transistor is of a complementary type. The source terminal of the input transistor is connected to the drain terminal of the feedback transistor and serves as the output. The gate terminal of the feedback transistor is connected to the drain terminal of the input transistor and the drain terminal of the bias current source.

[0016] Furthermore, the four second-order units of the low-pass filter are arranged in a cross-type configuration of PMOS and NMOS input units to achieve direct coupling.

[0017] The advantages and positive effects of this invention are:

[0018] This invention includes a variable gain amplifier with an embedded DC offset cancellation loop and a low-pass filter with reconfigurable bandwidth. The variable gain amplifier with the embedded DC offset cancellation loop is located in the first, second, and last stages, used to amplify the signal output from the mixer and eliminate DC offset generated from the analog baseband preamplifier stage and itself. The low-pass filter is located in the third stage, and its bandwidth is controlled by adjusting the capacitor value for signal filtering. The analog baseband circuit of this invention features low power consumption, high linearity, and precise gain control. Attached Figure Description

[0019] Figure 1 This is a block diagram of a millimeter-wave radar receiver system and a schematic diagram illustrating the content of this invention.

[0020] Figure 2 This is a schematic diagram of the overall structure of the present invention;

[0021] Figure 3 This is a schematic diagram of the variable gain amplifier unit in this invention;

[0022] Figure 4 This is a schematic diagram of the structure of the second-order unit of the low-pass filter in this invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings.

[0024] like Figure 1 As shown, the receiving antenna transmits the received radio frequency signal to a low-noise amplifier for initial amplification, and then the signal is down-converted by a mixer to generate an intermediate frequency (IF) signal. This IF signal is the input signal to the analog baseband circuit. The analog baseband circuit performs amplitude adjustment, filtering, and DC offset cancellation on the input signal, and then sends the adjusted signal to the analog-to-digital converter for processing.

[0025] like Figure 2 As shown, this invention provides an analog baseband circuit for millimeter-wave radar. The analog baseband circuit includes a variable gain amplifier with an embedded DC offset cancellation loop and a bandwidth-reconfigurable low-pass filter. The input signal to the analog baseband circuit is the output signal of a mixer. It is first amplified and DC offset cancelled by two stages of variable gain amplifiers, then filtered by an eighth-order low-pass filter, and finally amplified and DC offset cancelled by a single stage of variable gain amplifier.

[0026] like Figure 3 As shown, the variable gain amplifier with an embedded DC offset cancellation loop includes a variable gain amplifier core circuit, a DC offset cancellation circuit, and a common-mode feedback circuit. The variable gain amplifier core circuit is a two-stage fully differential structure. The input signal is connected to the gate terminal of transistor M1. The source terminal of transistor M1 is simultaneously connected to the source negative feedback resistor RS, the source terminal of transistor M3, and the drain terminal of transistor M4. The drain terminal of M4 is simultaneously connected to the drain terminals of transistors M5 and M6, and the gate terminals of transistors M2 and M7. The gate-drain of transistor M3 is shorted to the drain terminal of transistor M2. The source terminals of transistors M2, M5, M6, and M7 are all grounded. The drain terminal of transistor M8 is connected to the drain terminal of transistor M7 as the output of the variable gain amplifier core circuit, and its source terminal is connected to the power supply. The core circuit of this variable gain amplifier operates as follows: the differential input signal is transmitted to the source negative feedback resistor RS and generates a current signal. This current signal flows into the M2 feedback transistor, and the M7 transistor replicates the current signal of the M2 transistor proportionally. Subsequently, the current signal in the M7 transistor is transmitted to the sensing resistor RCM in the common-mode feedback circuit and generates an output voltage. As a result, the gain of the variable gain amplifier is related to RS, RCM, and the current replication ratio. Although this structure is an open-loop structure, the linearity of the variable gain amplifier is improved due to the introduction of the source negative feedback resistor and local feedback.

[0027] DC offset cancellation circuit in a variable gain amplifier, such as Figure 3 As shown, its input is the output of the variable gain amplifier core circuit, which is connected to the gate of transistor M10 through resistor R1. The source of transistor M10 is connected to a tail current source, and its drain is connected to transistor M11 (diode-connected) and cross-coupled negative resistor transistor M12. Simultaneously, the drain of transistor M10 serves as the output of the DC offset cancellation circuit, connected to the gate of transistor M6 in the variable gain core circuit. The working principle of this DC offset circuit is as follows: Resistor R1 and capacitor C1, after being Miller-multiplied, form a low-pass filter to extract the low-frequency components from the output signal of the variable gain amplifier core circuit. This low-frequency component is input to the amplifier in the DC offset cancellation circuit and generates a differential current. This differential current is fed back to the variable gain amplifier core circuit through transistor M5 and adjusts the current of transistor M2, thereby adjusting the current of transistor M7, ultimately completing the DC offset cancellation.

[0028] Common-mode feedback circuit in a variable gain amplifier, such as Figure 3 As shown, this common-mode feedback circuit has a two-stage structure. Its input is the output of the variable gain amplifier core circuit, which is connected to the gate of transistor M14a through resistor RCM. The gate of transistor M14b is connected to the reference level. The sources of transistors M14a and M14b are connected to tail current sources, and their drains are connected to a single-ended current mirror load composed of a pair of M15 transistors. The drain of transistor M15a serves as the output of the first stage of the common-mode feedback circuit. The output of the first stage is connected to the gate of transistor M16. The drain of transistor M16 is connected to transistor M17, which has a diode connection. The gate and drain of transistor M17 serve as the output of the common-mode feedback circuit and are connected to the gate of transistor M8 in the variable gain amplifier core circuit. A series connection of resistor R2 and capacitor C2 is used between the outputs of the two stages of the common-mode feedback circuit to generate a zero point to compensate for the common-mode loop stability of the variable gain amplifier.

[0029] Figure 4 This is a schematic diagram of the second-order unit in the bandwidth-reconfigurable low-pass filter of the present invention, using an NMOS input second-order unit as an example. Figure 4 As shown, this second-order unit is based on an NMOS input transistor with an FVF structure, and incorporates three control bandwidth capacitors, two neutralizing capacitors, and a level shifting circuit. The input signal is connected to the gate of transistor M1, and the source of transistor M1 is connected to the drain of transistor M2 as the output of this second-order unit. Transistor M3 acts as a current source, providing bias current to transistors M1 and M2. Capacitor C1 is connected between the source and drain of transistor M1, and capacitor C2 is connected between the differential output terminals. Transistor M6 acts as a MOS capacitor, fulfilling the function of a neutralizing capacitor to improve the stopband rejection of the filter. The level shifting circuit includes transistor M5 in diode configuration and its bias current source M4, used to improve the saturation voltage margin of transistor M1.

[0030] A bandwidth-reconfigurable low-pass filter consists of four cascaded second-order units, such as... Figure 2 As shown, the four second-order units of the low-pass filter are arranged in an alternating pattern of PMOS and NMOS input units to achieve direct coupling between stages. The cutoff frequency of the low-pass filter is adjusted by changing the capacitance values ​​in the second-order units.

[0031] It should be emphasized that the embodiments described in this invention are illustrative rather than limiting. Therefore, this invention includes, but is not limited to, the embodiments described in the specific implementation. Any other implementations derived by those skilled in the art based on the technical solutions of this invention are also within the scope of protection of this invention.

Claims

1. A low-power, high-linearity analog baseband circuit with variable gain and bandwidth, characterized in that: It includes a variable gain amplifier with an embedded DC offset cancellation loop and a low-pass filter with reconfigurable bandwidth; wherein, the variable gain amplifier with an embedded DC offset cancellation loop is located in the first, second and last stages, and is used to amplify the signal output by the mixer and eliminate DC offset generated from the analog baseband preamplifier and itself; the low-pass filter is located in the third stage, and the bandwidth of the filter is controlled by adjusting the capacitance value, and it is used to filter the signal; The variable gain amplifier with embedded DC offset cancellation loop includes a variable gain amplifier core circuit, a DC offset cancellation circuit, and a common-mode feedback circuit. The variable gain amplifier core circuit is a two-stage fully differential structure. The first stage input transistor is a PMOS pair, whose source terminal is simultaneously connected to the source negative feedback resistor, the drain terminal of the PMOS current source, and the source terminal of the diode-connected PMOS transistor. Its drain terminal is simultaneously connected to the NMOS current source, the drain terminal of the DC offset circuit feedback transistor, the gate terminal of the local feedback NMOS transistor, and the gate terminal of the second stage input transistor. The gate and drain terminals of the diode-connected PMOS transistor are connected to the drain terminal of the NMOS feedback transistor. The second stage is a common-source amplifier with a current source load, and the gate terminal of the current source load is controlled by the output of the common-mode feedback circuit. The input of the DC offset cancellation circuit is the output of the core circuit of the variable gain amplifier. It is connected to the gate of the PMOS input pair in the DC offset circuit amplifier through a resistor. The source of the PMOS pair is connected to the tail current source, and the drain is connected to the output of the DC offset circuit as a diode-type NMOS load and a cross-coupled negative resistance pair. The output is connected to the gate of the DC offset feedback transistor in the core circuit of the variable gain amplifier. The common-mode feedback circuit has a two-stage structure. Its input is the output of the core circuit of the variable gain amplifier, which is connected to the gate of one PMOS input transistor in the error amplifier through a resistor. The gate of the other PMOS input transistor is connected to the reference level. The source terminals of these two PMOS input transistors are connected to the tail current source, and the drain terminals are connected to the single-ended output NMOS current mirror load. The second stage of the common-mode feedback circuit is a common-source amplifier with a diode MOS load. The gate and drain terminals of the diode MOS load are connected as the output of the second stage to the gate of the common-mode feedback control transistor in the core circuit of the variable gain amplifier. A series resistor and capacitor are connected between the two outputs of the common-mode feedback circuit to generate a zero point to compensate for the common-mode loop stability of the variable gain amplifier. The resistor in the DC offset circuit is a MOS transistor operating in the subthreshold region to reduce the chip area.

2. The low-power, high-linearity analog baseband circuit with variable gain and bandwidth according to claim 1, characterized in that: The variable gain amplifier achieves gain control by adjusting the resistance value of the source negative feedback resistor.

3. The low-power, high-linearity analog baseband circuit with variable gain and bandwidth according to claim 1, characterized in that: The bandwidth-reconfigurable low-pass filter has an eighth-order Butterworth response and is composed of four cascaded second-order units. It is used to filter out-of-band signals and interference. The input of the low-pass filter is the output of the second-stage variable gain amplifier, and its output is connected to the input of the last-stage variable gain amplifier.

4. The low-power, high-linearity analog baseband circuit with variable gain and bandwidth according to claim 3, characterized in that: The second-order unit is based on a pseudo-differential flip-flop voltage follower structure, and incorporates three control bandwidth capacitors, two neutralizing capacitors, and a level shifting circuit. The control bandwidth capacitors are connected across the source and drain terminals of the FVF input transistor and between the differential output terminals, respectively. Two MOSFETs are cross-coupled between the input and output of the second-order unit as neutralizing capacitors. The level shifting circuit includes a diode-connected MOSFET and its bias current source to improve the saturation voltage margin of the FVF input transistor. The gate of the diode-connected MOSFET is connected to the drain terminal of the FVF input transistor, and the source terminal is connected to the gate of the feedback transistor in the FVF.

5. The low-power, high-linearity analog baseband circuit with variable gain and bandwidth according to claim 4, characterized in that: The FVF structure consists of three MOSFETs: an input MOSFET, a feedback MOSFET, and a MOSFET that serves as a bias current source. The input MOSFET and the feedback MOSFET are of the same type, while the bias current source MOSFET is of a complementary type. The source terminal of the input MOSFET is connected to the drain terminal of the feedback MOSFET and serves as the output. The gate terminal of the feedback MOSFET is connected to the drain terminal of the input MOSFET and the drain terminal of the bias current source.

6. The low-power, high-linearity analog baseband circuit with variable gain and bandwidth according to claim 3, characterized in that: The four second-order units of the low-pass filter are arranged in a cross-type configuration of PMOS and NMOS input units to achieve direct coupling.

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