A hardware implementation method for reducing algorithm power consumption and an algorithm power consumption reduction device

Abstract

The application provides a hardware implementation method for reducing algorithm power consumption, comprising the following steps: inputting plaintext and performing algorithm encryption; using a 32-round symmetric algorithm of SM4 as a round operation of the hardware implementation method for reducing algorithm power consumption; setting clock frequency division parameters according to circuit requirements to perform iteration control on the algorithm; selecting and setting the number of rounds of the hardware implementation method for reducing algorithm power consumption; setting the number of clocks according to the number of rounds, and the number of clocks is 32 / number of rounds; the working time of the algorithm is 32 / frequency; the hardware implementation method for reducing algorithm power consumption can set a plurality of clocks to perform a plurality of rounds of algorithm encryption on the plaintext, and after outputting a round result, the round result is subjected to reverse sequence transformation to output ciphertext. The hardware implementation method for reducing algorithm power consumption provided by the application reduces the working power consumption of the algorithm, the chip and the device while keeping the algorithm performance unchanged.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to a hardware implementation method and device for reducing algorithm power consumption. Background Technology

[0002] SM4 is a block cipher standard adopted by the government of the People's Republic of China and issued by the State Cryptography Administration. The relevant standard is "GM / T 0002-2012 'SM4 Block Cipher Algorithm' (formerly SMS4 Block Cipher Algorithm)". It is widely used in China, employing the SM4 algorithm, which features high performance and strong security, and is used in various security fields across the country.

[0003] In the field of handheld or battery-powered devices, the battery capacity is relatively small, and the power consumption of encryption chips is a burden on these devices. Adding encryption chips significantly shortens the battery life of mobile devices, affecting usage time and the implementation of the device's algorithm functions, and also impacting the device's overall functionality. Therefore, how to reduce the power consumption of encryption chips while maintaining algorithm performance is a key technical challenge that needs to be overcome. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a hardware implementation method to reduce the power consumption of the algorithm, so as to solve the problem of high power consumption of existing chips. This technical solution enables the chip to reduce power consumption while maintaining performance.

[0005] To address the aforementioned technical problems, this application provides a hardware implementation method for reducing algorithm power consumption, comprising the following steps:

[0006] Encrypt the input plaintext using an algorithm;

[0007] The 32-round symmetric algorithm of SM4 is used as one round of operation in the hardware implementation method of reducing the power consumption of the algorithm; the clock division parameters are set according to the circuit requirements to iteratively control the algorithm;

[0008] Select the number of rounds in the hardware implementation method for reducing algorithm power consumption; set the number of clock cycles according to the number of rounds, where the number of clock cycles is 32 / number of rounds; the working time of one algorithm cycle is 32 / frequency;

[0009] The hardware implementation method for reducing algorithm power consumption can set several clocks to perform several rounds of algorithm encryption on the plaintext. After outputting the round results, the round results are reversed to output the ciphertext.

[0010] In one possible implementation of the above hardware implementation method, the working cycle range of the hardware implementation method for reducing algorithm power consumption is T. min To Tmax The working period of the SM4 symmetric algorithm is T. rnd ;and

[0011] T rnd <T min .

[0012] In one possible implementation of the above hardware implementation method, the number of rounds can be set to 1, 2, 4, or 8.

[0013] In one possible implementation of the above hardware implementation method, when the number of rounds is set to be neither 1, nor 2, nor 4, nor 8, the hardware implementation method for reducing algorithm power consumption will automatically reduce the number of rounds to the nearest selection range, which includes 1, 2, 4, or 8.

[0014] In one possible implementation of the above hardware method, the specific steps of the symmetric algorithm include:

[0015] The plaintext is row-shifted, the shifted data is encrypted with a round key, the encrypted data is replaced with SBOX, and the replaced data is then column-obfuscated.

[0016] In one possible implementation of the above hardware implementation method, the number of rounds of the hardware implementation method for reducing algorithm power consumption corresponds to the number of round keys, and the round keys in the hardware implementation method for reducing algorithm power consumption in each round are different.

[0017] In one possible implementation of the above hardware implementation method, the number of rounds of the hardware implementation method for reducing algorithm power consumption is m, and the m rounds of SM4 calculation are respectively n, n+1, n+2, ..., n+m-1 rounds of encryption calculation.

[0018] This application also provides an algorithm power consumption reduction device, applied in the aforementioned hardware implementation method, including:

[0019] Plaintext register, used to store input plaintext;

[0020] The clock division selection unit is used to select the number of rounds used in the hardware implementation method to reduce the power consumption of the algorithm;

[0021] An iterative controller is used to iteratively control the frequency division algorithm according to the number of rounds;

[0022] The round result register is used to store the result calculated by the frequency division algorithm;

[0023] The SM4 chip is used for computation using the SM4 symmetric algorithm.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The hardware implementation method for reducing algorithm power consumption provided by this invention reduces the operating power consumption of the algorithm, chip and device; by setting the operating clock frequency division, the number of calculation rounds per clock is increased, so that the algorithm performance remains unchanged while reducing power consumption. Attached Figure Description

[0026] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0027] Figure 1 This is a schematic diagram of a clock frequency divider.

[0028] Figure 2 A schematic diagram of a single-cycle symmetric algorithm calculation under a clock frequency division of 4;

[0029] Figure 3 Timing requirements diagrams for different frequency divisions;

[0030] Figure 4 Calculate waveforms for symmetric algorithms under different frequency divisions. Detailed Implementation

[0031] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0032] The present invention discloses a clock frequency division method and apparatus, such as... Figure 1 The diagram shows a hardware implementation structure of SM4 without degrading clock frequency division performance. It includes a plaintext register for storing the input plaintext; a clock frequency division selection unit for selecting the number of rounds used in the hardware implementation method to reduce algorithm power consumption; an iterative controller for iteratively controlling the frequency division algorithm according to the number of rounds; a round result register for storing the result after the frequency division algorithm; and an SM4 chip for calculation using the SM4 symmetric algorithm.

[0033] A hardware implementation method for reducing algorithm power consumption includes the following steps: inputting plaintext and encrypting the plaintext using an algorithm.

[0034] The 32-round symmetric algorithm of SM4 is used, where the 32 rounds of SM4 constitute one round of the hardware implementation method for reducing algorithm power consumption. Clock division parameters are set according to circuit requirements to iteratively control the algorithm. The number of rounds in the hardware implementation method for reducing algorithm power consumption is selected. The number of clocks is set according to the number of rounds, where the number of clocks is 32 / number of rounds. The working time of one algorithm cycle is 32 / frequency. The hardware implementation method for reducing algorithm power consumption can symmetrically set several clocks to encrypt plaintext through several rounds of algorithm. After outputting the round results, the round results are reversed to output ciphertext.

[0035] Based on the system's power consumption requirements, the software can select the number of rounds for the hardware implementation method to reduce algorithm power consumption, choosing between a 1, 2, 4, or 8-fold frequency division. The clock division value controls the iteration control logic, controlling different SM4 rounds of calculation for each clock cycle according to different clock division values. The corresponding result is latched into the round result register, and the round counter is adjusted. A 1-fold division selects one round of SM4 calculation for each clock cycle, selecting one round channel to latch into the round result register, and incrementing the round counter by 1 for each clock cycle. When the round counter reaches 32, one SM4 calculation is completed, and the ciphertext is output. A 2-fold division selects two rounds of SM4 calculation for each clock cycle, selecting two round channels to latch into the round result register, and incrementing the round counter by 2 for each clock cycle. When the round counter reaches 32, one SM4 calculation is completed, and the ciphertext is output. For clock divisions of 4 or 8, 4 or 8 channels are selected for latching, and the clock increments by 4 or 8 for each clock cycle.

[0036] For a specific implementation of the above-described multi-round SM4 calculation, please refer to... Figure 2 ,like Figure 2 The diagram illustrates a single-cycle SM4 calculation under a clock frequency divided by 4. With the operating clock frequency divided by 4, each clock cycle performs four rounds of SM4 calculations. The symmetric algorithm is identical in each round, and these four rounds are cascaded. Each round undergoes the same operations, with encryption methods sequentially: row shift, round key addition, SBOX substitution, and column obfuscation. A hardware implementation method to reduce algorithm power consumption uses m rounds of SM4 calculations, where n, n+1, n+2, ..., n+m-1 are the number of rounds; where n ranges from 1 to 29, and n is an odd number.

[0037] The algorithm calculation operation in each round is the same, but the round keys are different. When the number of algorithm rounds is 4, the round keys calculated by the four-round SM4 symmetric algorithm are respectively the nth, n+1th, n+2th and n+3th round keys, where n is an odd number and can be any one of 1, 5, 9, 13, 17, 21, 25 and 29. The round keys are generated in advance before the SM4 algorithm calculation, and the round key corresponding to the current round is selected during the SM4 calculation. The number of rounds of the hardware implementation method for reducing algorithm power consumption corresponds to the number of round keys, and the round keys in the hardware implementation method for reducing algorithm power consumption in each round are different from each other.

[0038] In the hardware implementation of the apparatus of the hardware implementation method for reducing algorithm power consumption, the timing requirement of the synchronous circuit must be met. When the working clock is not divided, the maximum working frequency of the chip is Fmax, and the period is Tmin=1 / Fmax. At this time, only one round of SM4 calculation is performed in one clock cycle. Assuming that the time for one round of SM4 is Trnd, to meet the timing requirement that the calculation delay of one clock cycle is less than one period, Trnd must be less than Tmin. Under 2, 4 or 8 clock division, the periods are 2*Tmin, 4*Tmin and 8*Tmin respectively. It is respectively set that one clock cycle performs 2, 4 or 8 rounds of SM4 symmetric algorithm calculation, which takes 2*Trnd, 4*Trnd and 8*Trnd respectively. At this time, the timing requirements become 2*Trnd<2*Tmin, 4*Trnd<4*Tmin and 8*Trnd<8*Tmin, which are simplified to Trnd<Tmin, consistent with the timing requirement without clock division. Figure 3 This is a schematic diagram of timing requirements under different clock divisions of 1, 2, 4 or 8. In general, the multi-round calculation time per clock cycle needs to be less than the clock period. When the number of rounds is set to a value other than 1, 2, 4 or 8, the hardware implementation method for reducing algorithm power consumption will automatically perform a reduction selection process, and the selection range is 1, 2, 4 or 8.

[0039] Figure 4 These are respectively the waveform diagrams of SM4 calculation under 1, 2 and 4 clock divisions. When the clock is not divided and the number of algorithm rounds is 1, 1 round is calculated per clock cycle. Under 2 clock division, 2 rounds are calculated per clock cycle, for example, the first clock cycle calculates round 1 and round 2, and the second clock cycle calculates round 3 and round 4. Under 4 clock division, 4 rounds are calculated per clock cycle, for example, the first clock cycle calculates the symmetric algorithm of round 1, round 2, round 3 and round 4, and the second clock cycle calculates the symmetric algorithm of round 5, round 6, round 7 and round 8. A complete SM4 operation requires 32 rounds of iteration, according to Figure 4 It can be seen that under different clock divisions, although the clock frequencies vary greatly, the increment of the number of SM4 rounds is the same, which has little relation to the number of clocks with different divisions. Therefore, although the working clock is divided, the algorithm performance of SM4 is not reduced, achieving the effect of reducing power consumption without changing performance.

[0040] In summary, the hardware implementation method for reducing algorithm power consumption provided by this invention reduces the operating power consumption of the algorithm, chip, and device; by setting the operating clock frequency division and increasing the number of calculation rounds per clock, the power consumption is reduced while maintaining the algorithm performance, which has potential for widespread application.

[0041] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A hardware implementation method for reducing algorithm power consumption, characterized in that, Includes the following steps: Encrypt the input plaintext using an algorithm; The 32-round symmetric algorithm of SM4 is used as one round of operation in the hardware implementation method of reducing the power consumption of the algorithm; the clock division parameters are set according to the circuit requirements to iteratively control the algorithm; Select the number of rounds in the hardware implementation method for reducing algorithm power consumption; set the number of clock cycles according to the number of rounds, where the number of clock cycles is 32 / number of rounds; the working time of one algorithm cycle is 32 / frequency; The hardware implementation method for reducing algorithm power consumption sets up several clocks to perform several rounds of algorithm encryption on the plaintext. After outputting the round results, the round results are reversed to output the ciphertext. The hardware implementation method for reducing algorithm power consumption is configured to select the number of rounds, choosing a frequency divider of 1, 2, 4, or 8 to control SM4 calculations to be performed in 1, 2, 4, or 8 rounds per clock cycle. The corresponding result is latched into the round result register, and the round counter is adjusted. Based on the frequency divider value, the round counter is incremented by the corresponding step size. After the round result is output, an SM4 calculation is completed when the round counter reaches 32. The round result is then reversed and the ciphertext is output.

2. The hardware implementation method for reducing algorithm power consumption according to claim 1, characterized in that, The working cycle range of the hardware implementation method for reducing algorithm power consumption is... to The working cycle of the SM4 symmetric algorithm is ;and < 。 3. The hardware implementation method for reducing algorithm power consumption according to claim 1, characterized in that, The number of rounds can be set to 1, 2, 4, or 8.

4. The hardware implementation method for reducing algorithm power consumption according to claim 1, characterized in that, When the number of rounds is set to be neither 1, nor 2, nor 4, nor 8, the hardware implementation method for reducing algorithm power consumption will automatically reduce the number of rounds to the nearest selection range, which includes 1, 2, 4, or 8.

5. The hardware implementation method for reducing algorithm power consumption according to claim 1, characterized in that, The specific steps of the symmetric algorithm include: The plaintext is row-shifted, the shifted data is encrypted with a round key, the encrypted data is replaced with SBOX, and the replaced data is then column-obfuscated.

6. The hardware implementation method for reducing algorithm power consumption according to claim 5, characterized in that, The number of rounds in the hardware implementation method for reducing algorithm power consumption corresponds to the number of round keys, and the round keys in the hardware implementation method for reducing algorithm power consumption in each round are different.

7. The hardware implementation method for reducing algorithm power consumption according to claim 6, characterized in that, The hardware implementation method for reducing algorithm power consumption has m rounds, where m rounds of SM4 calculation are n, n+1, n+2, ..., n+m-1 rounds of encryption calculation, where n is an odd number and the value of n ranges from 1 to 29.

8. An algorithm power consumption reduction device, using the hardware implementation method for reducing algorithm power consumption as described in any one of claims 1 to 7, characterized in that, include: Plaintext register, used to store input plaintext; The clock division selection unit is used to select the number of rounds used in the hardware implementation method to reduce the power consumption of the algorithm; An iterative controller is used to iteratively control the frequency division algorithm according to the number of rounds; The round result register is used to store the result calculated by the frequency division algorithm; The SM4 chip is used for computation using the SM4 symmetric algorithm.

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