Reset circuit and reset control method

Abstract

The reset circuit and the reset control method, the reset circuit comprises a first control circuit, a non-user mode instruction acquisition circuit and a second control circuit. The first control circuit outputs a first control signal according to the initial state of the target pin. When the first control signal is a non-user mode enable signal, the non-user mode instruction acquisition circuit receives a non-user mode instruction signal. When the second control circuit receives the non-user mode enable signal but does not receive the non-user mode instruction signal, the second control circuit controls the state of the target pin to be a preset state. Based on this, when the chip pin is disturbed by electrostatic discharge and mistakenly enters the non-user mode pin state, the reset circuit can reset the state of the target pin according to the received non-user mode enable signal but not the non-user mode instruction signal, so as to make the chip return to the user mode and ensure the normal work of the chip.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a reset circuit and a reset control method. Background Technology

[0002] Chips typically operate in user mode and non-user mode. When chip pin resources are limited, pin multiplexing is a common practice for chip mode selection. The state of the multiplexed pin is latched by an external reset pin or an internal power-on reset, and then the latched state value is used to assign the chip to various modes. This mode signal is maintained until the chip is powered off.

[0003] In existing technologies, some chip multiplexed pins are not packaged or are left floating in the board-level system. The chip may be susceptible to electrostatic discharge (ESD) interference and mistakenly enter non-user mode. If the chip is battery-powered, the battery powers the chip in the system and then remains powered on. Therefore, if a chip mistakenly enters non-user mode due to ESD interference during normal application, the chip in the system will remain in non-user mode and will not return to user mode, potentially leading to system malfunctions. Summary of the Invention

[0004] Therefore, it is necessary to provide a reset circuit and reset control method to address the problem in the prior art where a chip cannot return to user mode after mistakenly entering non-user mode.

[0005] Firstly, this application provides a reset circuit. The reset circuit includes:

[0006] A first control circuit is used to output a first control signal according to the initial state of the target pin; when the initial state meets a preset condition, the first control signal output by the first control circuit is a non-user mode enable signal.

[0007] A non-user mode instruction acquisition circuit, connected to the first control circuit, begins to receive and send non-user mode instruction signals when it receives the non-user mode enable signal.

[0008] The second control circuit is connected to the first control circuit and the non-user mode instruction acquisition circuit, respectively, and is used to determine the second control signal based on the first control signal and the non-user mode instruction signal; when the second control circuit receives the non-user mode enable signal but does not receive the non-user mode instruction signal, the second control signal is a reset signal, and the reset signal is used to control the state of the target pin to a preset state.

[0009] In one embodiment, the second control circuit includes:

[0010] A timing circuit is connected to the first control circuit and the non-user mode instruction acquisition circuit, respectively, and is used to determine a first time according to the non-user mode enable signal and the non-user mode instruction signal. When the first time meets the preset time condition, the timing circuit outputs the reset signal.

[0011] In one embodiment, the target pin includes a first pin and a second pin, the preset condition includes a first preset condition and a second preset condition, and the first control circuit includes:

[0012] A latching circuit is used to output a first latching signal according to the initial state of the first pin, and to output a second latching signal according to the initial state of the second pin.

[0013] An OR gate circuit, connected to the latching device, is used to output an initial control signal according to the first latch signal, the second latch signal, and the preset condition; when the initial control signal satisfies the first preset condition, the first control signal is a non-user mode enable signal; when the initial control signal satisfies the second preset condition, the first control signal is a user mode enable signal.

[0014] In one embodiment, the reset circuit further includes:

[0015] User-mode instruction acquisition circuit, used to receive and send user-mode instruction signals;

[0016] The selector is connected to the OR gate circuit, the non-user mode instruction acquisition circuit, the user instruction acquisition circuit, and the second control circuit, respectively. It is used to determine the target signal based on the first control signal, the non-user mode instruction signal, and the user mode instruction signal, and output the target signal to the second control circuit. The second control circuit is also used to determine the second control signal based on the first control signal and the target signal.

[0017] In one embodiment, when the first control signal is a non-user mode enable signal, the selector uses the received non-user mode instruction signal as the target signal; when the first control signal is a user mode enable signal, the selector uses the received user mode instruction signal as the target signal.

[0018] In one embodiment, the second control signal further includes a first target control signal and a second target control signal;

[0019] The second control circuit determines the first target control signal based on the received user mode enable signal and user mode instruction signal; the first target control signal is used to control the target circuit to execute the user mode instruction.

[0020] The second control circuit determines the second target control signal based on the received non-user mode enable signal and non-user mode instruction signal; the second target control signal is used to control the target circuit to execute the non-user mode instruction.

[0021] The second control circuit determines the reset signal based on the received non-user mode enable signal, but without receiving the non-user mode command signal.

[0022] In one embodiment, the second control circuit further includes a timing circuit;

[0023] When the timing circuit receives the non-user mode enable signal, it starts timing to determine the non-user mode signal reception time. If the non-user mode signal reception time is longer than a preset time, and the timing circuit does not receive the non-user mode command signal, the timing circuit outputs the reset signal.

[0024] Secondly, this application also provides a reset control method, the method comprising:

[0025] The target pin output state is obtained, and a first control signal is determined based on the initial state and preset conditions; when the initial state satisfies the preset conditions, the first control signal is determined to be a non-user mode enable signal.

[0026] Based on the non-user mode enable signal, receive and send non-user mode instruction signals;

[0027] A second control signal is determined based on the non-user mode enable signal and the non-user mode instruction signal; when the non-user mode enable signal is determined but the non-user mode instruction signal is not received, the second control signal is determined to be a reset signal; the reset signal is used to control the state of the target pin to a preset state.

[0028] In one embodiment, determining the second control signal based on the non-user mode enable signal and the non-user mode instruction signal includes:

[0029] The first time is determined based on the non-user mode enable signal and the non-user mode instruction signal;

[0030] The second control signal is determined based on the first time and the preset time condition.

[0031] In one embodiment, the target pin includes a first pin and a second pin, the preset conditions include a first preset condition and a second preset condition, and the step of acquiring the target pin output state and determining a first control signal based on the initial state and the preset conditions includes:

[0032] The first latch signal is determined based on the initial state of the first pin; and the second latch signal is determined based on the initial state of the second pin.

[0033] The initial control signal is determined based on the OR gate logic, the first latch signal, and the second latch signal;

[0034] The first control signal is determined based on the initial control signal and the preset conditions; when the initial control signal satisfies the first preset conditions, the first control signal is determined to be a non-user mode enable signal; when the initial control signal satisfies the second preset conditions, the first control signal is determined to be a user mode enable signal.

[0035] Thirdly, this application also provides a reset control device, the device comprising:

[0036] The acquisition module is used to acquire the output state of the target pin and determine a first control signal based on the initial state and preset conditions; when the initial state meets the preset conditions, the first control signal is determined to be a non-user mode enable signal.

[0037] The receiving module is used to receive and send a non-user mode instruction signal according to the non-user mode enable signal;

[0038] The determining module is configured to determine a second control signal based on the non-user mode enable signal and the non-user mode instruction signal; when the non-user mode enable signal is determined but the non-user mode instruction signal is not received, the second control signal is determined to be a reset signal; the reset signal is used to control the state of the target pin to a preset state.

[0039] Fourthly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps described in the second aspect above.

[0040] Fifthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the steps described in the second aspect above.

[0041] Sixthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps described in the second aspect above.

[0042] In the aforementioned reset circuit and reset control method, the reset circuit includes a first control circuit, a non-user mode instruction acquisition circuit, and a second control circuit. The first control circuit outputs a first control signal based on the initial state of the target pin. When the first control signal is a non-user mode enable signal, the non-user mode instruction acquisition circuit receives a non-user mode instruction signal. When the second control circuit receives the non-user mode enable signal but does not receive the non-user mode instruction signal, it controls the state of the target pin to a preset state. Therefore, when a chip pin is accidentally entered a non-user mode state due to electrostatic discharge interference, the aforementioned reset circuit, based on receiving the non-user mode enable signal but not the non-user mode instruction signal, can reset the state of the target pin, causing the chip to return to user mode and ensuring normal chip operation. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a structural diagram of the reset circuit in one embodiment;

[0045] Figure 2 This is a structural diagram of the reset circuit in another embodiment;

[0046] Figure 3 This is a flowchart illustrating a reset control method in one embodiment;

[0047] Figure 4 This is a structural block diagram of the reset control device in one embodiment;

[0048] Figure 5 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided through embodiments and in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0050] The serial numbers assigned to components in this document, such as "first" and "second," are used solely to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages). It should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are used solely for the convenience of describing this application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0051] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0052] Chips typically operate in user mode and non-user mode. When chip pin resources are limited, pin multiplexing (strapping pins) is a common practice for mode selection. The state of the multiplexed pin is latched using an external reset pin or an internal power-on reset, and then the latched state value is used to assign different modes to the chip. This mode signal is maintained until the chip is powered off. However, in TPMS (Tire Pressure Monitoring System), these multiplexed pins are not packaged or are left floating in the board-level system. They may be susceptible to electrostatic discharge interference and mistakenly enter non-user mode. Since TPMS systems are battery-powered and do not power off after power-on, if a non-user mode is mistakenly entered during normal application, the system will remain in this mode and will not return to user mode, potentially leading to system malfunctions.

[0053] Based on this, such as Figure 1 As shown, this application provides a reset circuit, which includes:

[0054] The first control circuit is used to output a first control signal according to the initial state of the target pin; when the initial state meets the preset conditions, the first control signal output by the first control circuit is a non-user mode enable signal.

[0055] The non-user mode instruction acquisition circuit is connected to the first control circuit. When it receives the non-user mode enable signal, the non-user mode instruction acquisition circuit starts to receive and send non-user mode instruction signals.

[0056] The second control circuit is connected to the first control circuit and the non-user mode instruction acquisition circuit respectively, and is used to determine the second control signal based on the first control signal and the non-user mode instruction signal. When the second control circuit receives the non-user mode enable signal but does not receive the non-user mode instruction signal, the second control signal is a reset signal. The reset signal is used to control the state of the target pin to a preset state.

[0057] The initial state can be the voltage level of the target pin, which can be either low or high. The initial state of the target pin can indicate the chip's operating mode. In practical applications, a high initial state of the target pin can indicate that the chip is in non-user mode, or a high initial state of the target pin can indicate that the chip is in user mode. The control principles of the two methods are essentially the same. In this application, we will use the example of a high initial state of the target pin indicating that the chip is in non-user mode for explanation.

[0058] In one embodiment, when the initial state of the target pin is high, the chip system where the target pin is located is in non-user mode, and the first control circuit outputs a first control signal as a non-user mode enable signal; when the initial state of the target pin is low, the chip system where the target pin is located is in user mode, and the first control circuit outputs a first control signal as a user mode enable signal.

[0059] Specifically, the non-user mode instruction acquisition circuit can be connected to the target pin to acquire the non-user mode instruction signal. The non-user mode instruction acquisition circuit will not acquire the non-user mode instruction signal if it does not receive a non-user mode enable signal.

[0060] Furthermore, when the second control circuit receives both a non-user mode command signal and a non-user mode enable signal, it determines that the second control signal is a non-user mode command signal and executes the non-user mode command.

[0061] In one embodiment of this application, the non-user mode instruction can be a non-user mode watchdog instruction, and the second control circuit can be a watchdog circuit. When the watchdog circuit receives both a non-user mode watchdog instruction signal and a non-user mode enable signal, it can perform watchdog processing according to the non-user mode watchdog instruction. When the watchdog circuit receives a non-user mode enable signal but does not receive a non-user mode watchdog instruction signal, it indicates that the target pin is being interfered with and has mistakenly entered a non-user mode state. At this time, the watchdog circuit outputs a reset signal to the target pin, pulling the high level of the target pin down to a low level, so that the state of the target pin automatically returns to the user mode state.

[0062] The aforementioned reset circuit includes a first control circuit, a non-user mode instruction acquisition circuit, and a second control circuit. The first control circuit outputs a first control signal based on the initial state of the target pin. When the first control signal is a non-user mode enable signal, the non-user mode instruction acquisition circuit receives a non-user mode instruction signal. When the second control circuit receives the non-user mode enable signal but not the non-user mode instruction signal, it controls the state of the target pin to a preset state. Therefore, when a chip pin is accidentally entered a non-user mode state due to electrostatic discharge interference, the aforementioned reset circuit can reset the state of the target pin by detecting the receipt of a non-user mode enable signal but the absence of a non-user mode instruction signal, thereby returning the chip to user mode and ensuring normal chip operation.

[0063] In one embodiment of this application, the second control circuit includes:

[0064] The timing circuit is connected to the first control circuit and the non-user mode instruction acquisition circuit respectively. It is used to determine the first time according to the non-user mode enable signal and the non-user mode instruction signal. When the preset time condition is met at the first time, the timing circuit outputs a reset signal.

[0065] Specifically, the timing circuit starts timing upon receiving a non-user mode enable signal and stops timing and resets to zero upon receiving a non-user mode command signal. If the timing circuit receives the non-user mode enable signal but does not receive the non-user mode command signal, and the initial timing time exceeds the preset time, it indicates that the target pin has been interfered with and mistakenly entered the non-user mode state. The timing circuit will output a reset signal to pull the high level of the target pin down to a low level, so that the target pin can automatically return to the user mode state.

[0066] In one embodiment of this application, the target pin includes a first pin and a second pin, and the preset conditions include a first preset condition and a second preset condition, such as... Figure 2 As shown, the first control circuit includes:

[0067] A latching circuit is used to output a first latching signal based on the initial state of the first pin and a second latching signal based on the initial state of the second pin.

[0068] An OR gate circuit, connected to a latching device, is used to output an initial control signal based on a first latching signal, a second latching signal, and a preset condition; when the initial control signal meets the first preset condition, the first control signal is a non-user mode enable signal; when the initial control signal meets the second preset condition, the first control signal is a user mode enable signal.

[0069] Specifically, the number of target pins includes, but is not limited to, two; this application uses two pins as an example. A latching device corresponds one-to-one with each target pin. The latching device may include a first latch and a second latch. The first latch outputs a first latch signal based on the initial state of the first pin, and the second latch outputs a second latch signal based on the initial state of the second pin. In this specification, "1" represents a high level and "0" represents a low level. The initial state of the first pin can be either high or low, and the initial state of the second pin can also be either high or low. Therefore, the signal received by the OR gate circuit can be "11", "10", "01", or "00". When the first latch signal and the second latch signal received by the OR gate are "11", "10" or "01", the output initial control signal is "1", which indicates that the target pin is in non-user mode and the first control signal is the non-user mode enable signal; when the first latch signal and the second latch signal received by the OR gate are "00", the output initial control signal is "0", which indicates that the target pin is in user mode and the first control signal is the user mode enable signal.

[0070] In one embodiment of this application, the reset circuit further includes:

[0071] User-mode instruction acquisition circuit, used to receive and send user-mode instruction signals;

[0072] The selector is connected to an OR gate circuit, a non-user mode instruction acquisition circuit, a user instruction acquisition circuit, and a second control circuit, respectively. It is used to determine a target signal based on a first control signal, a non-user mode instruction signal, and a user mode instruction signal, and output the target signal to the second control circuit. The second control circuit is also used to determine a second control signal based on the first control signal and the target signal.

[0073] The user mode command signal can be generated by an external circuit. In this application, the user mode command signal is only used to receive and send user mode commands.

[0074] In one embodiment of this application, when the first control signal is a non-user mode enable signal, the selector uses the received non-user mode instruction signal as the target signal; when the first control signal is a user mode enable signal, the selector uses the received user mode instruction signal as the target signal.

[0075] Specifically, when the first control signal is a non-user mode enable signal, the non-user mode instruction acquisition circuit starts acquiring non-user mode instruction signals and can output non-user mode instructions to the second control circuit through a selector; when the first control signal is a user mode enable signal, the user mode instruction acquisition circuit starts acquiring user mode instruction signals and can output user mode instructions to the second control circuit through a selector. At this time, the non-user mode instruction acquisition circuit stops acquiring non-user mode instruction signals.

[0076] Specifically, the selector can be a two-input selector, comprising two input terminals, one selection terminal, and one output terminal. The selection terminal is controlled by a first control signal. The output terminal of the non-user mode instruction acquisition circuit is connected to the selector's input "1", and the output terminal of the user mode instruction acquisition circuit is connected to the selector's input "0". When the first control signal is a non-user mode enable signal (i.e., "1"), the input "1" terminal is turned on, and the non-user mode instruction signal can be transmitted to the second control circuit as the target signal; when the first control signal is a user mode enable signal (i.e., "0"), the input "0" terminal is turned on, and the user mode instruction signal can be transmitted to the second control circuit as the target signal.

[0077] In one embodiment of this application, the second control signal further includes a first target control signal and a second target control signal;

[0078] The second control circuit determines the first target control signal based on the received user mode enable signal and user mode instruction signal; the first target control signal is used to control the target circuit to execute the user mode instruction.

[0079] The second control circuit determines the second target control signal based on the received non-user mode enable signal and non-user mode instruction signal; the second target control signal is used to control the target circuit to execute the non-user mode instruction.

[0080] The second control circuit determines the reset signal based on the received non-user mode enable signal, but not the received non-user mode command signal.

[0081] In one embodiment of this application, the non-user mode command signal can be a non-user mode watchdog command signal, the user mode command signal can be a user mode watchdog command signal, and the second control circuit can be a watchdog circuit. The watchdog circuit can execute the non-user mode watchdog command upon receiving a non-user mode enable signal and a non-user mode watchdog command; the watchdog circuit can execute the user mode watchdog command upon receiving both a user mode enable signal and a user mode watchdog command; the watchdog circuit outputs a reset signal upon receiving a non-user mode enable signal but not a non-user mode watchdog command, causing the target pin that has mistakenly entered the non-user mode state to return to the user mode state. Based on this, the reset circuit provided in this application can not only execute control commands in non-user mode and control commands in user mode, but also automatically adjust the state of the target pin to a preset state to return to user mode when the target pin mistakenly enters the non-user mode.

[0082] In one embodiment of this application, the second control circuit further includes a timing circuit;

[0083] When the timing circuit receives the non-user mode enable signal, it starts timing to determine the non-user mode signal reception time. If the non-user mode signal reception time is longer than the preset time, the timing circuit does not receive the non-user mode command signal and outputs a reset signal.

[0084] Specifically, the timing circuit starts timing upon receiving a non-user mode enable signal and stops timing and resets to zero upon receiving a non-user mode command signal. If the timing circuit receives the non-user mode enable signal but does not receive the non-user mode command signal, and the initial timing time exceeds the preset time, it indicates that the target pin has been interfered with and mistakenly entered the non-user mode state. The timing circuit will output a reset signal to pull the high level of the target pin down to a low level, so that the target pin can automatically return to the user mode state.

[0085] Based on this, such as Figure 3 As shown, this application provides a reset control method, which includes the following steps:

[0086] Step S301: Obtain the target pin output state and determine the first control signal based on the initial state and preset conditions; when the initial state meets the preset conditions, determine the first control signal as a non-user mode enable signal.

[0087] Specifically, when the initial state of the target pin is high, the chip system where the target pin is located is in non-user mode, and the first control circuit outputs the first control signal as a non-user mode enable signal; when the initial state of the target pin is low, the chip system where the target pin is located is in user mode, and the first control circuit outputs the first control signal as a user mode enable signal.

[0088] Step S302: Based on the non-user mode enable signal, receive and send a non-user mode command signal.

[0089] Specifically, when the first control signal is a non-user mode enable signal, the non-user mode command signal is obtained through the target pin; when the first control signal is a user mode enable signal, the non-user mode command signal is not obtained through the target pin, and the user mode command signal is obtained through the user mode acquisition circuit.

[0090] Step S303: Determine the second control signal based on the non-user mode enable signal and the non-user mode instruction signal; when the non-user mode enable signal is determined but the non-user mode instruction signal is not received, determine the second control signal as a reset signal; the reset signal is used to control the state of the target pin to a preset state.

[0091] The non-user mode instruction can be a non-user mode watchdog feed instruction, and the second control circuit can be a watchdog circuit. When the watchdog circuit receives a non-user mode enable signal but does not receive a non-user mode watchdog feed instruction signal, it indicates that the target pin has been interfered with and has mistakenly entered the non-user mode state. At this time, the watchdog circuit outputs a reset signal to the target pin, pulling the high level of the target pin down to the low level, so that the state of the target pin automatically returns to the user mode state.

[0092] The above reset control method acquires the initial state of the target pin and determines the first control signal based on the initial state. When the first control signal is a non-user mode enable signal, it begins to acquire the non-user mode command signal. If the non-user mode enable signal is determined but the non-user mode command signal is not received, it indicates that the target pin has been interfered with and mistakenly entered non-user mode. At this time, a reset signal is output to reset the state of the target pin, returning it to the user mode state.

[0093] In one embodiment of this application, step S303, which determines the second control signal based on the non-user mode enable signal and the non-user mode instruction signal, includes:

[0094] The first time is determined based on the non-user mode enable signal and the non-user mode instruction signal;

[0095] The second control signal is determined based on the first time and the preset time condition.

[0096] Specifically, timing begins upon receiving a non-user mode enable signal and stops and resets to zero upon receiving a non-user mode command signal. If the timing circuit receives the non-user mode enable signal but does not receive the non-user mode command signal, and the initial timing time exceeds the preset time, it indicates that the target pin has been interfered with and mistakenly entered the non-user mode state. The timing circuit will output a reset signal to pull the high level of the target pin down to a low level, so that the target pin can automatically return to the user mode state.

[0097] In one embodiment of this application, the target pin includes a first pin and a second pin, and the preset conditions include a first preset condition and a second preset condition; step S301 above, obtaining the output state of the target pin and determining a first control signal based on the initial state and preset conditions, includes:

[0098] The first latch signal is determined based on the initial state of the first pin; and the second latch signal is determined based on the initial state of the second pin.

[0099] The initial control signal is determined based on the OR gate logic, the first latch signal, and the second latch signal;

[0100] The first control signal is determined based on the initial control signal and preset conditions; when the initial control signal meets the first preset conditions, the first control signal is determined to be a non-user mode enable signal; when the initial control signal meets the second preset conditions, the first control signal is determined to be a user mode enable signal.

[0101] Specifically, in this specification, "1" represents a high level and "0" represents a low level. The initial state of the first pin can be either high or low, and the initial state of the second pin can also be either high or low. When the first latch signal and the second latch signal are "11", "10", or "01", the initial control signal determined by the OR gate logic is "1", indicating that the target pin is in non-user mode, and the first control signal is the non-user mode enable signal. When the first latch signal and the second latch signal are "00", the initial control signal determined by the OR gate logic is "0", indicating that the target pin is in user mode, and the first control signal is the user mode enable signal.

[0102] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with at least some steps or stages in other steps.

[0103] Based on the same inventive concept, this application also provides a reset control device for implementing the reset control method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more reset control device embodiments provided below can be found in the limitations of the reset control method described above, and will not be repeated here.

[0104] Based on this, such as Figure 4 As shown, this application provides a reset control device 400, which can be applied to the above-described reset control method. The method includes the following modules:

[0105] The acquisition module 410 is used to acquire the output state of the target pin and determine the first control signal based on the initial state and preset conditions; when the initial state meets the preset conditions, the first control signal is determined to be a non-user mode enable signal.

[0106] Receiver module 420 is used to receive and send non-user mode command signals according to the non-user mode enable signal;

[0107] The determination module 430 is used to determine the second control signal based on the non-user mode enable signal and the non-user mode instruction signal; when the non-user mode enable signal is determined but the non-user mode instruction signal is not received, the second control signal is determined to be a reset signal; the reset signal is used to control the state of the target pin to a preset state.

[0108] In one embodiment of this application, the determining module 430 is specifically used for:

[0109] The first time is determined based on the non-user mode enable signal and the non-user mode instruction signal;

[0110] The second control signal is determined based on the first time and the preset time condition.

[0111] In one embodiment of this application, the target pin includes a first pin and a second pin, and the preset conditions include a first preset condition and a second preset condition; the acquisition module 410 is specifically used for:

[0112] The first latch signal is determined based on the initial state of the first pin; and the second latch signal is determined based on the initial state of the second pin.

[0113] The initial control signal is determined based on the OR gate logic, the first latch signal, and the second latch signal;

[0114] A first control signal is determined based on an initial control signal and preset conditions; if the initial control signal meets the first preset conditions, the first control signal is determined to be a non-user mode enable signal; if the initial control signal meets the second preset conditions, the first control signal is determined to be a user mode enable signal.

[0115] The modules of the aforementioned reset control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0116] In one embodiment of this application, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows. Figure 5 As shown, the computer device includes a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a reset control method. The display screen can be an LCD screen or an e-ink display screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0117] Those skilled in the art will understand that Figure 5The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0118] In one embodiment of this application, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0119] In one embodiment of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps in the above-described method embodiments.

[0120] In one embodiment of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0121] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0122] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0123] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0124] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A reset circuit, characterized in that, include: The first control circuit is used to output a first control signal according to the initial state of the target pin; When the initial state meets the preset conditions, the first control signal output by the first control circuit is a non-user mode enable signal. The target pin includes a first pin and a second pin, the preset conditions include a first preset condition and a second preset condition, and the first control circuit includes: A latching circuit is used to output a first latching signal according to the initial state of the first pin, and to output a second latching signal according to the initial state of the second pin. An OR gate circuit, connected to a latching device, is used to output an initial control signal based on the first latch signal, the second latch signal, and the preset condition; when the initial control signal satisfies the first preset condition, the first control signal is a non-user mode enable signal; when the initial control signal satisfies the second preset condition, the first control signal is a user mode enable signal. A non-user mode instruction acquisition circuit, connected to the first control circuit, begins to receive and send non-user mode instruction signals when it receives the non-user mode enable signal. The second control circuit is connected to the first control circuit and the non-user mode instruction acquisition circuit, respectively, and is used to determine the second control signal based on the first control signal and the non-user mode instruction signal; when the second control circuit receives the non-user mode enable signal but does not receive the non-user mode instruction signal, the second control signal is a reset signal, and the reset signal is used to control the state of the target pin to a preset state.

2. The reset circuit as described in claim 1, characterized in that, The second control circuit includes: A timing circuit is connected to the first control circuit and the non-user mode instruction acquisition circuit, respectively, and is used to determine a first time according to the non-user mode enable signal and the non-user mode instruction signal. When the first time meets the preset time condition, the timing circuit outputs the reset signal.

3. The reset circuit as described in claim 1, characterized in that, The reset circuit also includes: User-mode instruction acquisition circuit, used to receive and send user-mode instruction signals; The selector is connected to the OR gate circuit, the non-user mode instruction acquisition circuit, the user instruction acquisition circuit, and the second control circuit, respectively. It is used to determine the target signal based on the first control signal, the non-user mode instruction signal, and the user mode instruction signal, and output the target signal to the second control circuit. The second control circuit is also used to determine the second control signal based on the first control signal and the target signal.

4. The reset circuit as described in claim 3, characterized in that, When the first control signal is a non-user mode enable signal, the selector uses the received non-user mode instruction signal as the target signal; when the first control signal is a user mode enable signal, the selector uses the received user mode instruction signal as the target signal.

5. The reset circuit as described in claim 4, characterized in that, The second control signal also includes a first target control signal and a second target control signal; The second control circuit determines the first target control signal based on the received user mode enable signal and user mode instruction signal; the first target control signal is used to control the target circuit to execute the user mode instruction. The second control circuit determines the second target control signal based on the received non-user mode enable signal and non-user mode instruction signal; the second target control signal is used to control the target circuit to execute the non-user mode instruction. The second control circuit determines the reset signal based on the received non-user mode enable signal, but without receiving the non-user mode command signal.

6. The reset circuit as described in claim 5, characterized in that, The second control circuit also includes a timing circuit; When the timing circuit receives the non-user mode enable signal, it starts timing to determine the non-user mode signal reception time. If the non-user mode signal reception time is longer than a preset time, and the timing circuit does not receive the non-user mode command signal, the timing circuit outputs the reset signal.

7. A reset control method, characterized in that, The method includes: The target pin output state is obtained, and a first control signal is determined based on the initial state and preset conditions; when the initial state meets the preset conditions, the first control signal is determined to be a non-user mode enable signal. The target pin includes a first pin and a second pin, the preset conditions include a first preset condition and a second preset condition, and the step of acquiring the output state of the target pin and determining the first control signal based on the initial state and the preset conditions includes: The first latch signal is determined based on the initial state of the first pin; and the second latch signal is determined based on the initial state of the second pin. The initial control signal is determined based on the OR gate logic, the first latch signal, and the second latch signal; The first control signal is determined based on the initial control signal and the preset condition; when the initial control signal satisfies the first preset condition, the first control signal is determined to be a non-user mode enable signal; when the initial control signal satisfies the second preset condition, the first control signal is determined to be a user mode enable signal. Based on the non-user mode enable signal, receive and send non-user mode instruction signals; A second control signal is determined based on the non-user mode enable signal and the non-user mode instruction signal; when the non-user mode enable signal is determined but the non-user mode instruction signal is not received, the second control signal is determined to be a reset signal; the reset signal is used to control the state of the target pin to a preset state.

8. The reset control method as described in claim 7, characterized in that, The step of determining the second control signal based on the non-user mode enable signal and the non-user mode instruction signal includes: The first time is determined based on the non-user mode enable signal and the non-user mode instruction signal; The second control signal is determined based on the first time and the preset time condition.

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