Memory bandwidth test method, device, equipment and computer readable storage medium
By sharding the test array under the NUMA architecture and storing it in the near-end memory area of the CPU node, and using multi-threaded read and write operations, the problem of inaccurate memory bandwidth test results in the prior art is solved, and more accurate memory bandwidth test is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA MOBILE GROUP ZHEJIANG
- Filing Date
- 2021-10-21
- Publication Date
- 2026-08-04
AI Technical Summary
Under the NUMA architecture, existing memory bandwidth testing tools need to frequently access remote memory areas through the Noc interface between CPU nodes, which limits performance and makes the test results unable to reflect the true situation of memory bandwidth in domestic servers.
By obtaining the total number of CPU nodes in the system, the test array is sharded, and the sharded array is stored in the near-end memory area corresponding to the CPU node. Read and write operations are performed using a multi-threaded approach, which conforms to the characteristics of NUMA architecture.
It improves the accuracy of memory bandwidth testing, enabling test results to truly reflect the memory bandwidth of domestically produced servers under NUMA architecture, reducing human intervention and improving the intelligence and robustness of the test.
Smart Images
Figure CN116010222B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory testing technology, and in particular to a memory bandwidth testing method, apparatus, device, and computer-readable storage medium. Background Technology
[0002] In existing technologies, the Stream testing tool, under the NUMA (Non-Uniform Memory Access Architecture) architecture, needs to continuously access the remote memory area through the Noc (network-on-chip) interface between CPU (Central Processing Unit) nodes, which limits its performance and the test results cannot reflect the true memory bandwidth of domestic servers under the NUMA architecture. Summary of the Invention
[0003] The main objective of this invention is to provide a memory bandwidth testing method, apparatus, device, and computer-readable storage medium, aiming to improve the accuracy of testing memory bandwidth under NUMA architecture.
[0004] To achieve the above objectives, the present invention provides a memory bandwidth testing method, which includes the following steps:
[0005] Get the total number of CPU nodes in the system;
[0006] The test array is divided according to the total number of nodes to obtain a sharded array;
[0007] The shard array is stored in the near-end memory area corresponding to the CPU node, wherein the CPU node performs read and write operations corresponding to the memory bandwidth test thread based on the shard array of the near-end memory area.
[0008] Optionally, the step of obtaining the total number of CPU nodes in the system includes the following steps before:
[0009] If the CPU architecture in the system is NUMA, then read the system's free memory value;
[0010] Determine whether the system's free memory value meets the preset test requirements;
[0011] If the system's free memory value meets the test requirements, then the step of obtaining the total number of CPU nodes in the system is executed.
[0012] Optionally, the step of dividing the test array according to the total number of nodes to obtain a sharded array includes:
[0013] The number of test arrays is determined based on the system's available memory value;
[0014] The test array is divided into sharded arrays based on the array size and the total number of nodes.
[0015] Optionally, after the step of determining whether the system's free memory value meets the preset test requirements, the method further includes:
[0016] If the system's free memory value does not meet the test requirements, then check whether there are running application processes in the system;
[0017] If the application process exists in the system, terminate the operation of the application process and return to the step of reading the system's free memory value.
[0018] Optionally, the step of determining whether the system's free memory value meets the preset test requirements includes:
[0019] Obtain the number of CPUs in the system, the total number of CPU nodes, and the L3 cache capacity corresponding to each CPU node;
[0020] The number of CPUs, the total number of nodes, and the L3 cache capacity are input into a preset verification formula for calculation to obtain the verification result;
[0021] Based on the verification results, it is determined whether the system's free memory value meets the preset test requirements.
[0022] Optionally, the verification formula includes:
[0023]
[0024] Where FreeMen is the system's free memory value, SocketNum is the number of CPUs, NodeNum is the total number of CPU nodes, and NodeL3Size is... (n) This represents the L3 cache capacity of the nth CPU node.
[0025] Optionally, the step of storing the shard array into the near-end memory region corresponding to the CPU node includes:
[0026] The preset memory bandwidth test items are bound to the CPU node to obtain the memory bandwidth test thread corresponding to the CPU node.
[0027] Furthermore, to achieve the above objectives, the present invention also provides a memory bandwidth testing device, comprising:
[0028] The parameter acquisition module is used to obtain the total number of CPU nodes in the system;
[0029] An array segmentation module is used to segment the test array according to the total number of nodes to obtain a segmented array;
[0030] An array binding module is used to store the sharded array into the near-end memory area corresponding to the CPU node, wherein the CPU node performs read and write operations corresponding to the memory bandwidth test thread based on the sharded array in the near-end memory area.
[0031] In addition, to achieve the above objectives, the present invention also provides a memory bandwidth testing device, which includes a memory, a processor, and a memory bandwidth testing program stored on the memory and executable on the processor. When the memory bandwidth testing program is executed by the processor, it implements the steps of the memory bandwidth testing method described above.
[0032] In addition, to achieve the above objectives, the present invention also provides a computer-readable storage medium storing a memory bandwidth testing program, which, when executed by a processor, implements the steps of the memory bandwidth testing method described above.
[0033] This invention achieves the following steps: obtaining the total number of CPU nodes in the system; dividing the test array according to the total number of nodes to obtain a sharded array; and storing the sharded array in the near-end memory area corresponding to each CPU node. This ensures that the sharded test array is stored in the near-end memory area corresponding to each CPU node. Finally, the CPU nodes execute read and write operations corresponding to the memory bandwidth test thread based on the sharded array in their near-end memory areas. This multi-threaded approach allows each CPU node to handle the read and write calculations of its respective sharded array in its near-end memory area. This transforms the process, which previously required multiple accesses to the remote memory area via the Noc interface, into a process where only the nearest access is needed, conforming to the characteristics of NUMA architecture. Such test results can accurately reflect the memory bandwidth of domestic servers under NUMA architecture, thereby improving the accuracy of memory bandwidth testing under NUMA architecture. Attached Figure Description
[0034] Figure 1 This is a schematic diagram of the terminal / device structure of the hardware operating environment involved in the embodiments of the present invention;
[0035] Figure 2 This is a schematic diagram of read and write operations for Copy test items under an SMP architecture in one embodiment;
[0036] Figure 3 This is a schematic diagram of read and write operations for a Scale test item under an SMP architecture in one embodiment;
[0037] Figure 4 This is a schematic diagram of the read and write operation of the Add test item under the SMP architecture in one embodiment;
[0038] Figure 5 This is a schematic diagram of read and write operations of a Triad test item under an SMP architecture in one embodiment;
[0039] Figure 6 This is a schematic diagram of the read and write operations of the Copy test item under the NUMA architecture before optimization in one embodiment;
[0040] Figure 7 This is a schematic diagram of read and write operations of a Scale test item under the NUMA architecture before optimization in one embodiment;
[0041] Figure 8 This is a schematic diagram of the read and write operations of the Add test item under the NUMA architecture before optimization in one embodiment;
[0042] Figure 9 This is a schematic diagram of the read and write operations of the Triad test item under the NUMA architecture before optimization in one embodiment;
[0043] Figure 10 This is a flowchart illustrating the first embodiment of the memory bandwidth testing method of the present invention;
[0044] Figure 11 This is a schematic diagram of read and write operations of the Copy test item under the optimized NUMA architecture according to an embodiment of the present invention;
[0045] Figure 12 This is a schematic diagram of read and write operations of Scale test items under the optimized NUMA architecture according to an embodiment of the present invention;
[0046] Figure 13 This is a schematic diagram of the read and write operation of the Add test item under the optimized NUMA architecture according to an embodiment of the present invention.
[0047] Figure 14 This is a schematic diagram of read and write operations of Triad test items under the optimized NUMA architecture according to an embodiment of the present invention;
[0048] Figure 15 This is a flowchart illustrating the second embodiment of the memory bandwidth testing method of the present invention;
[0049] Figure 16 This is a detailed flowchart of step S200 in the third embodiment of the memory bandwidth testing method of the present invention;
[0050] Figure 17 This is a detailed flowchart of step S600 in the fourth embodiment of the memory bandwidth testing method of the present invention;
[0051] Figure 18This is a flowchart illustrating a specific embodiment of the memory bandwidth testing method of the present invention;
[0052] Figure 19 This is a schematic diagram of the device modules of the memory bandwidth testing apparatus according to an embodiment of the present invention;
[0053] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0054] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0055] like Figure 1 As shown, Figure 1 This is a schematic diagram of the terminal structure of the hardware operating environment involved in the embodiments of the present invention.
[0056] In this embodiment of the invention, the terminal is a memory bandwidth testing device.
[0057] like Figure 1 As shown, the terminal may include: a processor 1001, such as a CPU; a network interface 1004; a user interface 1003; a memory 1005; and a communication bus 1002. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen and an input unit such as a keyboard. Optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed RAM or non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
[0058] Optionally, the terminal may also include a camera, RF (Radio Frequency) circuitry, audio circuitry, and a WiFi module, etc. Sensors may include light sensors, motion sensors, and other sensors. Specifically, the light sensor may include an ambient light sensor and a proximity sensor. The ambient light sensor can adjust the brightness of the display screen according to the ambient light level, and the proximity sensor can turn off the display screen and / or backlight when the terminal device is moved to the ear. Of course, the terminal device may also be equipped with other sensors such as a gyroscope, barometer, hygrometer, thermometer, and infrared sensor, which will not be elaborated upon here.
[0059] Those skilled in the art will understand that Figure 1The terminal structure shown does not constitute a limitation on the terminal and may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0060] like Figure 1 As shown, the memory 1005, which is a computer-readable storage medium, may include an operating system, a network communication module, a user interface module, and a memory bandwidth testing program.
[0061] exist Figure 1 In the terminal shown, network interface 1004 is mainly used to connect to the backend server and communicate with it; user interface 1003 is mainly used to connect to the client (user terminal) and communicate with it; while processor 1001 can be used to call the memory bandwidth test program stored in memory 1005 and perform the following operations:
[0062] Get the total number of CPU nodes in the system;
[0063] The test array is divided according to the total number of nodes to obtain a sharded array;
[0064] The shard array is stored in the near-end memory area corresponding to the CPU node, wherein the CPU node performs read and write operations corresponding to the memory bandwidth test thread based on the shard array of the near-end memory area.
[0065] To aid in understanding this invention, the research background of this invention is described below:
[0066] From upstream semiconductor materials, to core chips, supporting components, operating system software, then to complete systems, application software, and finally system integration and end customers, self-reliance and controllability constitute a large-scale and complete industrial chain. Currently, domestically produced server chips, such as Kunpeng and Phytium, are based on the ARM (Acorn RISC Machine) architecture, while Loongson uses the MIPS (Microprocessor without interlocked piped stages) architecture. This differs from the currently mainstream x86 architecture, and their software ecosystems also lag significantly. For both ARM and MIPS architecture chip platforms, domestic manufacturers have released operating systems based on open-source Linux versions.
[0067] Provided by Virginia University, Stream is an open-source performance testing tool for x86 chip platforms and Linux systems based on SMP architecture. It tests the memory bandwidth of high-performance computers by generating memory read and write operations under four different modes. Taking an SMP architecture with a terminal containing one CPU and four cores as an example, the four test items of the Stream tool are as follows:
[0068] (a) For the Copy test item, please refer to... Figure 2 This test item represents the simplest operation: reading a number from one memory location and copying it to another. It involves two memory accesses, with a read-then-write operation. Its main internal processing is as follows:
[0069] c 64f [i] = a 64f [i](i = 0, 1, 2, ..., N);
[0070] Among them, c 64f and a 64f Both are 64-bit floating-point arrays. This test actually copies array a to array c.
[0071] (b) Scale test items, please refer to Figure 3 This test item includes floating-point multiplication and assignment operations. A number is read from one memory location, multiplied by the constant `scale`, and the result is written to another memory location, involving two memory accesses. The main internal processing is as follows: (Read first, multiply, then write).
[0072] b 64f [i] = K 64f ×c 64f [i](i = 0, 1, 2, ..., N);
[0073] Among them, b 64f and c 64f Both are 64-bit floating-point arrays, K 64f It is a 64-bit floating-point constant factor. The test involves multiplying the elements of one array by a factor and then assigning the result to another array.
[0074] (c) Add test items, please refer to Figure 4 This test item includes floating-point addition and assignment operations. Two numbers are read from two separate memory locations, added together, and the result is written to another memory location. There are three memory accesses: two reads, one write, and one addition operation. Its main internal processing is as follows:
[0075] c 64f [i] = a 64f [i]+b 64f [i](i = 0, 1, 2, ..., N);
[0076] Among them, a 64f b 64f and c 64f Both are 64-bit floating-point arrays. This test involves summing the two arrays and then assigning the sum to the other array.
[0077] (d) Triad test items, please refer to Figure 5 This test item combines the previous three methods, including floating-point multiplication, addition, and assignment operations. First, a number is read from memory, multiplied by `scale` to obtain a product. Then, a number is read from another memory location and added to the previous product. The result is then written back to memory. Therefore, there are 3 memory accesses, 2 reads, 1 write, 1 addition, and 1 multiplication operation. Its main internal processing is as follows:
[0078] a 64f [i] = b 64f [i]+K 64f ×c 64f [i](i = 0, 1, 2, ..., N);
[0079] Among them, a 64f b 64f and c 64f Both are 64-bit floating-point arrays, K 64f It is a 64-bit floating-point constant factor. The test involves multiplying one array by the factor, summing it with another array, and finally assigning the result back to the first array.
[0080] Parameter descriptions for the Stream tool:
[0081]
[0082] It's important to note that the Stream testing tool is based on the X86 chip platform with an SMP architecture, while most domestically produced chips are based on the ARM platform, with an underlying CPU architecture of NUMA. Under the NUMA architecture, the relationship between the CPU and memory changes, resulting in a distinction between near-end memory and far-end memory. Taking a terminal with one CPU, four cores, and two CPU nodes in a NUMA architecture as an example, the memory read / write process based on the four test items of the Stream tool would look like this:
[0083] Please refer to the copy test items. Figure 6 For the scale test items, please refer to [link / reference]. Figure 7 To add test items, please refer to [link / reference]. Figure 8 For the Triad test items, please refer to [link / reference]. Figure 9 .
[0084] according to Figures 6 to 9As can be seen, under the NUMA architecture, the stream tool tests arrays a[], b[], and c[], which are stored in the memory corresponding to different nodes. During the test, the CPU node not only accesses data from the near-end memory area but also from the far-end memory area. It needs to continuously access the far-end memory area through the Noc interface between CPU nodes, which limits performance. Therefore, the test results cannot reflect the true memory bandwidth of domestic servers under the NUMA architecture.
[0085] The preceding description is intended to provide general background information and does not necessarily constitute prior art.
[0086] Based on this, this invention provides a memory bandwidth testing method for domestically developed NUMA architecture platforms.
[0087] Please refer to Figure 10 This is a first embodiment of the memory bandwidth testing method of the present invention, which includes the following steps:
[0088] For ease of description, the main body of the memory bandwidth test below is referred to as the terminal. Those skilled in the art will understand that the terminal in this embodiment may include desktop computers, laptops, and mobile phones, etc., and this embodiment does not limit the terminal.
[0089] Step S100: Obtain the total number of CPU nodes in the system;
[0090] In this context, a CPU node refers to a Node. In one embodiment, a CPU has two CPU nodes. In another embodiment, a CPU has four CPU nodes, and in yet another embodiment, a CPU has six CPU nodes. Figure 11 As shown, this indicates that the CPU has two CPU nodes and is a quad-core CPU. In one embodiment, a terminal has two CPUs. In another embodiment, a terminal has four CPUs, and in yet another embodiment, a terminal has eight CPUs, as shown... Figure 11 The terminal shown only displays one CPU.
[0091] It is understood that when a terminal has four CPUs, and each CPU has four CPU nodes, the total number of CPU nodes in the terminal is 16. When a terminal has eight CPUs, and each CPU has four CPU nodes, the total number of CPU nodes in the terminal is 32. When a terminal has two CPUs, and each CPU has two CPU nodes, the total number of CPU nodes in the terminal is 4. It should be noted that the above does not constitute a limitation on the total number of CPU nodes and the number of CPUs in the embodiments of the present invention, but is only used to fully understand the meaning of the total number of CPU nodes in the embodiments of the present invention.
[0092] Step S200: Divide the test array according to the total number of nodes to obtain a sharded array;
[0093] Specifically, the test array is divided into N shard arrays based on the total number of nodes.
[0094] Step S300: Store the shard array in the near-end memory area corresponding to the CPU node, wherein the CPU node performs read and write operations corresponding to the memory bandwidth test thread based on the shard array in the near-end memory area.
[0095] In one embodiment, the total number of CPU nodes is 16. The test array is divided into 16 equal parts, resulting in 16 fragmented arrays. These 16 fragmented arrays are then stored one-to-one with the 16 CPU nodes. In another embodiment, the total number of CPU nodes is 32. The test array is divided into 32 equal parts, resulting in 32 fragmented arrays. These 32 fragmented arrays are then stored one-to-one with the 32 CPU nodes. That is, one fragmented array corresponds to one CPU node.
[0096] Taking a terminal with a NUMA architecture consisting of one CPU, four cores, and two CPU nodes as an example, the optimized memory read / write process for the four test items based on the Stream tool will look like this:
[0097] Please refer to the copy test items. Figure 11 For the scale test items, please refer to [link / reference]. Figure 12 To add test items, please refer to [link / reference]. Figure 13 For the Triad test items, please refer to [link / reference]. Figure 14 .
[0098] This invention optimizes the test data structure based on the number of nodes inside the CPU, splits the test array, and binds the memory bandwidth test thread to the node, finally obtaining more realistic memory bandwidth data for the domestic platform.
[0099] This embodiment achieves the following steps: obtaining the total number of CPU nodes in the system; dividing the test array according to the total number of nodes to obtain a sharded array; and storing the sharded array in the near-end memory area corresponding to each CPU node. This ensures that the sharded test array is stored in the near-end memory area corresponding to each CPU node. Finally, the CPU nodes execute read and write operations corresponding to the memory bandwidth test thread based on the sharded array in their near-end memory areas. This multi-threaded approach allows each CPU node to handle the read and write calculations of its respective sharded array in its near-end memory area. This transforms the process, which previously required each CPU node to access the remote memory area multiple times via the Noc interface, into a process where only the nearest memory area is accessed, conforming to the characteristics of NUMA architecture. Such test results can accurately reflect the memory bandwidth of domestic servers under NUMA architecture, thereby improving the accuracy of memory bandwidth testing under NUMA architecture.
[0100] Further, the step of storing the fragment array into the near-end memory region corresponding to the CPU node includes:
[0101] Step a: Bind the preset memory bandwidth test items to the CPU node to obtain the memory bandwidth test thread corresponding to the CPU node.
[0102] As will be understood by those skilled in the art, the preset memory bandwidth test items may include the four test items of the Stream tool: Add, Triad, Copy, and Scale. Of course, other memory bandwidth test items may also be included, and this embodiment does not impose specific limitations. This embodiment binds the preset memory bandwidth test items to the CPU node, thereby obtaining the memory bandwidth test thread corresponding to the CPU node. This allows each CPU node, which loads its own memory bandwidth test thread, to perform read and write operations corresponding to the memory bandwidth test thread on the slice array in its respective near-end memory region, thus achieving memory bandwidth testing of the terminal.
[0103] Furthermore, referring to Figure 15 Based on the first embodiment of the present invention described above, a second embodiment of the memory bandwidth testing method of the present invention is proposed. In this embodiment, the method includes the following steps before step S100:
[0104] Step S400: Determine whether the CPU architecture in the system is a NUMA architecture;
[0105] Those skilled in the art will understand that CPU architecture may include NUMA architecture or SMP architecture. Currently, SMP architecture may also be referred to as UMA (Uniform Memory Access Architecture).
[0106] Step S500: If the CPU architecture in the system is NUMA, then read the system's free memory value.
[0107] The system's free space refers to the remaining running memory of the terminal.
[0108] Step S600: Determine whether the system's free memory value meets the preset test requirements;
[0109] If the system's free memory value meets the test requirements, then step S100 is executed: obtain the total number of CPU nodes in the system.
[0110] It should be noted that terminals, such as computers, generally use caching technology. In order to ensure that the test can accurately reflect the terminal's memory bandwidth read and write performance, the amount of data used in the test should be much larger than the cache size. The system's free memory value represents the cache size. Therefore, memory bandwidth performance testing can only be carried out when the terminal's system free memory value is large enough, that is, when the system free memory value meets the preset test requirements.
[0111] This embodiment determines whether the CPU architecture is a NUMA architecture. If the CPU architecture is a NUMA architecture, step S100 is executed: obtain the total number of CPU nodes in the system, thereby realizing a memory bandwidth test method corresponding to the CPU architecture, thus improving the accuracy of memory bandwidth testing.
[0112] This embodiment determines whether the current system free memory value is suitable for the memory bandwidth test environment by reading the system's free memory value and judging whether the system free memory value meets the preset test requirements. Under the condition that the current system free memory value is suitable for the memory bandwidth test environment, the terminal's memory bandwidth is tested, which further improves the accuracy of memory bandwidth testing.
[0113] Furthermore, referring to Figure 16 Based on the second embodiment of the present invention described above, a third embodiment of the memory bandwidth testing method of the present invention is proposed. In this embodiment, step S200, which involves dividing the test array according to the total number of nodes to obtain a sharded array, includes:
[0114] Step S210: Determine the number of test arrays based on the system's free memory value;
[0115] The array size value of the test array refers to the STREAM_ARRAY_SIZE tool parameter, which specifies the size of arrays a[], b[], and c[] in the calculation.
[0116] Step S220: The test array is divided according to the array quantity value and the total number of nodes to obtain a sharded array.
[0117] That is, by dividing the test arrays a[], b[], and c[] equally according to the total number of CPU nodes, a number of partitioned arrays are obtained. In one embodiment, the total number of CPU nodes is 16, so the test array is divided into 16 equal parts. In another embodiment, the total number of CPU nodes is 32, so the test array is divided into 32 equal parts.
[0118] Furthermore, the step of determining the number of test arrays based on the system's free memory value includes:
[0119] Step b: Determine the number of test arrays based on the system's free memory value and a preset array solving formula.
[0120] The array calculation formula includes:
[0121] STREAM_ARRAY_SIZE=80%×FreeMem×1024÷3÷8;
[0122] Where STREAM_ARRAY_SIZE is the array size value, and FreeMem is the system free memory value.
[0123] In this embodiment, the tool parameter STREAM_ARRAY_SIZE specifies the number of arrays a[], b[], and c[] used in the calculation. Its size has a significant impact on the test results. Its value cannot be too large or too small. If it is too large, it will exceed the memory limit and cause an error, or it will encroach on the system's own memory, affecting system performance and causing inaccurate test results. If the array size value is too small, the terminal's L3 cache capacity, or CPU cache, will interfere with the test results, preventing the measurement of the true memory bandwidth.
[0124] The STREAM_ARRAY_SIZE parameter is manually set, which is prone to errors. Determining the appropriate array size value places high demands on the user, making it a challenging task. This embodiment reduces manual intervention by providing a standard workflow and formula calculation. Based on the open-source code of stream, this embodiment has been further developed to automate parameter setting with a single click, lowering the barrier to entry.
[0125] This embodiment addresses the shortcomings of Stream tools in China, which suffer from inaccurate manual setting of test parameters in a domestic environment, by determining the number of test arrays based on the system's available memory. It proposes a fully automated process, reduces human intervention, eliminates test accuracy issues caused by improper setting of the number of test arrays, and makes test results more accurate.
[0126] Furthermore, after the step of determining whether the system's free memory value meets the preset test requirements, the method further includes:
[0127] Step c: If the system's free memory value does not meet the test requirements, then check whether there are running application processes in the system;
[0128] Step d: If the application process exists in the system, terminate the operation of the application process and return to the step of reading the system's free memory value.
[0129] Furthermore, if no application process exists in the system, a warning message indicating that memory bandwidth testing cannot be performed will be output.
[0130] This embodiment terminates the application process if it exists in the system and returns to the step of reading the system's free memory value. This proactively creates a memory bandwidth testing environment, improving the robustness of the memory bandwidth testing method. Furthermore, by outputting a warning message indicating that the memory bandwidth test cannot be performed if no application process exists, the method alerts the user that the system memory is insufficient, thus enhancing the intelligence of the memory bandwidth testing method.
[0131] Furthermore, referring to Figure 17 Based on the third embodiment of the present invention described above, a fourth embodiment of the memory bandwidth testing method of the present invention is proposed. In this embodiment, step S600, determining whether the system's free memory value meets the preset test requirements, includes:
[0132] Step S610: Obtain the number of CPUs in the system, the total number of CPU nodes, and the L3 cache capacity value corresponding to each CPU node.
[0133] Step S610: Input the number of CPUs, the total number of nodes, and the L3 cache capacity into a preset verification formula for calculation to obtain the verification result;
[0134] Step S630: Based on the verification result, determine whether the system's free memory value meets the preset test requirements.
[0135] This embodiment determines the system's free memory value required for memory bandwidth testing by summing the L3 cache capacity values of each CPU node under the domestic NUMA architecture, and then determines whether the current system's free memory value meets the test requirements. This embodiment provides a standard process method and formula for calculation to verify whether the terminal meets the test environment conditions for memory bandwidth, making the test results more accurate.
[0136] Furthermore, the verification formula includes:
[0137]
[0138] Where FreeMen is the system's free memory value, SocketNum is the number of CPUs, NodeNum is the total number of CPU nodes, and NodeL3Size is... (n) This represents the L3 cache capacity of the nth CPU node.
[0139] If the verification result of the verification formula is true, it is determined that the system's free memory value meets the test requirements; if the verification result of the verification formula is false, it is determined that the system's free memory value does not meet the test requirements.
[0140] This embodiment, under the domestic NUMA architecture, provides a standard verification formula to eliminate the accuracy problem caused by the terminal system's free memory not meeting the memory bandwidth test environment conditions, thus making the test results more accurate. At the same time, it proposes an automatic verification process to reduce manual intervention, complete the test work with one click, automatically perform parameter calculation and setting, tool operation, report output, etc., lower the threshold for use, and thus improve the intelligence of the memory bandwidth test method of this embodiment.
[0141] To facilitate a full understanding of the present invention, a specific embodiment is provided below. Please refer to it. Figure 18 , Figure 18 This is a flowchart illustrating the memory bandwidth testing method in a specific embodiment of the present invention. It should be noted that many specific details are described in the following specific embodiment to provide a thorough understanding of the invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the present invention is not limited to specific embodiment one. Specific Implementation Example 1:
[0143] (1) Obtain the number of CPUs, SoctetNum, through the system interface; if it is a NUMA architecture CPU, you also need to obtain the number of nodes in the CPU, NodeNum, through the system interface.
[0144] (2) Obtain the L3 cache size L3Size(n) of each CPU through the system interface, in KB; if it is a NUMA architecture CPU, obtain the L3 cache size NodeL3Size(n) of each node, in KB.
[0145] (3) Obtain the system's free memory size FreeMem through the system interface, in KB.
[0146] (4) Determine whether the CPU architecture is NUMA architecture. If not, use Formula 1 in the following formulas to determine whether the free memory meets the minimum memory usage requirements of the testing tool. If it is NUMA architecture, use Formula 2 to determine whether the free memory meets the minimum memory usage requirements of the testing tool.
[0147] (5) If the available memory does not meet the minimum requirements of the Stream tool, check if there is an application process in the system. If not, prompt that the system memory is insufficient and the memory test cannot be performed, and the test ends; if there is, terminate the application process, release the memory, and return to step 4 to check the available memory size again.
[0148] (6) If the free memory meets the minimum requirements of the tool Stream, the free memory is converted into the value of STREAM_ARRAY_SIZE through "Formula 3" in the following formula, and Stream is automatically set.
[0149] (7) Determine if the CPU architecture is NUMA. If yes, obtain the number of CPU nodes, divide the test arrays a[], b[], and c[], and bind the test threads to each node; otherwise, skip this step.
[0150] (8) Run the test tool and generate a test report.
[0151] The formulas include:
[0152] Formula 1:
[0153] Formula 2:
[0154] Formula 3: STREAM_ARRAY_SIZE = 80% × FreeMem × 1024 ÷ 3 ÷ 8.
[0155] This embodiment optimizes the source code of the stream tool by splitting its test arrays a[], b[], and c[] into slices based on the number of CPU nodes n. The sliced arrays a[]n, b[], and c[]n are then stored in the memory corresponding to each node. The program uses a multi-threaded approach, binding each node's CPU to handle read / write calculations for its nearest memory location. This transforms the process, which previously required multiple accesses to the remote memory region via Noc, into a single access to the nearest memory location, conforming to the characteristics of the NUMA architecture. Such test results accurately reflect the memory bandwidth of domestic servers under the NUMA architecture, thus improving the accuracy of memory bandwidth testing under NUMA architecture. This embodiment optimizes the test data structure based on the number of nodes within the CPU, splits the test array, and binds the execution thread to the node, ultimately obtaining more realistic memory bandwidth data for domestic platforms. Furthermore, this embodiment reduces manual intervention by providing standard process methods and formula calculations. Based on the open-source code of stream, secondary development is performed to automate parameter settings, allowing for one-click completion and lowering the barrier to entry.
[0156] In addition, refer to Figure 19 This invention also provides a memory bandwidth testing device, comprising:
[0157] The parameter acquisition module A10 is used to obtain the total number of CPU nodes in the system.
[0158] The array segmentation module A20 is used to segment the test array according to the total number of nodes to obtain a segmented array;
[0159] The array binding module A30 is used to store the sharded array into the near-end memory area corresponding to the CPU node, wherein the CPU node performs read and write operations corresponding to the memory bandwidth test thread based on the sharded array in the near-end memory area.
[0160] Optionally, the parameter acquisition module A10 is also used for:
[0161] If the CPU architecture in the system is NUMA, then read the system's free memory value;
[0162] Determine whether the system's free memory value meets the preset test requirements;
[0163] If the system's free memory value meets the test requirements, then the step of obtaining the total number of CPU nodes in the system is executed.
[0164] Optionally, the array splitting module A20 is also used for:
[0165] The number of test arrays is determined based on the system's available memory value;
[0166] The test array is divided into sharded arrays based on the array size and the total number of nodes.
[0167] Optionally, the array splitting module A20 is also used for:
[0168] If the system's free memory value does not meet the test requirements, then check whether there are running application processes in the system;
[0169] If the application process exists in the system, terminate the operation of the application process and return to the step of reading the system's free memory value.
[0170] Optionally, the array splitting module A20 is also used for:
[0171] Obtain the number of CPUs in the system, the total number of CPU nodes, and the L3 cache capacity corresponding to each CPU node;
[0172] The number of CPUs, the total number of nodes, and the L3 cache capacity are input into a preset verification formula for calculation to obtain the verification result;
[0173] Based on the verification results, it is determined whether the system's free memory value meets the preset test requirements.
[0174] Optionally, the array splitting module A20 is also used for:
[0175]
[0176] Where FreeMen is the system's free memory value, SocketNum is the number of CPUs, NodeNum is the total number of CPU nodes, and NodeL3Size is... (n) This represents the L3 cache capacity of the nth CPU node.
[0177] Optionally, the array binding module A30 is also used for:
[0178] The preset memory bandwidth test items are bound to the CPU node to obtain the memory bandwidth test thread corresponding to the CPU node.
[0179] The steps for implementing each functional unit of the memory bandwidth testing device can be referred to in the various embodiments of the memory bandwidth testing method of the present invention, and will not be repeated here.
[0180] Furthermore, the present invention also provides a memory bandwidth testing device, which includes: a memory, a processor, and a memory bandwidth testing program stored on the memory; the processor is used to execute the memory bandwidth testing program to implement the steps of the above-described embodiments of the memory bandwidth testing method.
[0181] The present invention also provides a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the steps of the embodiments of the memory bandwidth testing method described above.
[0182] The specific implementation of the computer-readable storage medium of the present invention is basically the same as the embodiments of the memory bandwidth testing method described above, and will not be repeated here.
[0183] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.
[0184] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0185] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.
[0186] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.
Claims
1. A memory bandwidth testing method, characterized by, The memory bandwidth testing method includes the following steps: Get the total number of CPU nodes in the system; The test array is divided according to the total number of nodes to obtain a sharded array; The shard array is stored in the near-end memory area corresponding to the CPU node, wherein the CPU node performs read and write operations corresponding to the memory bandwidth test thread based on the shard array of the near-end memory area; Before the step of obtaining the total number of CPU nodes in the system, the following steps are included: If the CPU architecture in the system is NUMA, then read the system's free memory value; Obtain the number of CPUs in the system, the total number of CPU nodes, and the L3 cache capacity corresponding to each CPU node; The number of CPUs, the total number of nodes, and the L3 cache capacity are input into a preset verification formula for calculation to obtain the verification result; Based on the verification results, determine whether the system's free memory value meets the preset test requirements; If the system's free memory value does not meet the test requirements, then check whether there are running application processes in the system; If the application process exists in the system, terminate the execution of the application process and return to the step of reading the system's free memory value. If the system's free memory value meets the test requirements, then the step of obtaining the total number of CPU nodes in the system is executed; The verification formula includes: ； Wherein, FreeMen is the system free memory value, SocketNum is the CPU quantity, NodeNum is the total node number of CPU node, NodeL3Size （n） is the third cache capacity value of the nth CPU node.
2. The memory bandwidth testing method of claim 1, wherein, The step of dividing the test array according to the total number of nodes to obtain the sharded array includes: The number of test arrays is determined based on the system's available memory value; The test array is divided into sharded arrays based on the array size and the total number of nodes.
3. The memory bandwidth testing method of claim 1, wherein, The step of storing the fragmented array into the near-end memory region corresponding to the CPU node includes: The preset memory bandwidth test items are bound to the CPU node to obtain the memory bandwidth test thread corresponding to the CPU node.
4. A memory bandwidth testing apparatus, characterized by, The memory bandwidth testing device includes: The parameter acquisition module is used to obtain the total number of CPU nodes in the system; The array segmentation module is used to segment the test array according to the total number of nodes to obtain a segmented array; An array binding module is used to store the sharded array into the near-end memory area corresponding to the CPU node, wherein the CPU node performs read and write operations corresponding to the memory bandwidth test thread based on the sharded array in the near-end memory area; Before the step of obtaining the total number of CPU nodes in the system, the following steps are included: If the CPU architecture in the system is NUMA, then read the system's free memory value; Obtain the number of CPUs in the system, the total number of CPU nodes, and the L3 cache capacity corresponding to each CPU node; The number of CPUs, the total number of nodes, and the L3 cache capacity are input into a preset verification formula for calculation to obtain the verification result; Based on the verification results, determine whether the system's free memory value meets the preset test requirements; If the system's free memory value does not meet the test requirements, then check whether there are running application processes in the system; If the application process exists in the system, terminate the execution of the application process and return to the step of reading the system's free memory value. If the system's free memory value meets the test requirements, then the step of obtaining the total number of CPU nodes in the system is executed; The verification formula includes: ； Wherein, FreeMen is the system free memory value, SocketNum is the CPU quantity, NodeNum is the total node number of CPU node, NodeL3Size （n） is the third cache capacity value of the nth CPU node.
5. A memory bandwidth testing device, characterized by, The memory bandwidth testing device includes: a memory, a processor, and a memory bandwidth testing program stored in the memory and executable on the processor. When the memory bandwidth testing program is executed by the processor, it implements the steps of the memory bandwidth testing method as described in any one of claims 1 to 3.
6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a memory bandwidth testing program, which, when executed by a processor, implements the steps of the memory bandwidth testing method as described in any one of claims 1 to 3.