A method, apparatus and system for processing a request

Abstract

The application provides a method, device and system for processing a request, which can enable a first node to read data of a second node or write data to the second node. The first node obtains a corresponding physical address based on a first virtual address in a first request, and the first request can be issued by an application in the first node, and is used for requesting to read data of the second node or requesting to write data to the second node. Then, the first node sends a second request corresponding to the first request to the second node based on a first mapping relationship, wherein the second request comprises a bus address, and the first mapping relationship is a mapping relationship between the physical address and the bus address. Since the bus address indicates a virtual address corresponding to an instance in the second node, the bus address can be accessed by the first node through the first request, and can also be accessed by the second node, or can be accessed by other nodes through a request, so that the sharing of the address can be realized in data access. On the other hand, the bus address is used instead of the semantic of network access, so that compared with the existing network communication technology, the time delay of accessing data of a remote device can be reduced, and the access rate can be improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to methods, apparatus and systems for accessing the memory of remote devices. Background Technology

[0002] With the development of technology, the use of distributed applications is becoming increasingly common. A distributed application refers to an application distributed across different physical nodes, typically computers. This means that when a distributed application executes a task or business function, it needs to exchange data between multiple physical nodes. During this process, data is usually stored in the memory of the physical nodes, and when needed, it is loaded into memory by the processor of that physical node. Thus, remote memory access—that is, a computer (the local device) accessing the memory of another computer (the remote device) to manipulate the data within it—is a very basic function. Technically, accessing data essentially means accessing the storage medium associated with that data, including at least two scenarios: reading data and writing data.

[0003] Typically, local devices access memory via a bus, while remote devices access memory via a network; their semantic rules differ. Specifically, accessing the memory of another device requires network communication technologies, such as Transmission Control Protocol / Internet Protocol (TCP / IP) or Remote Direct Memory Access (RDMA). This results in longer latency when accessing the memory of a remote device.

[0004] To reduce latency caused by network communication technologies, the semantics used for accessing the local device's memory can be used when accessing the remote device's memory. This requires On-Chip Interconnect (OCI) technology. Essentially, this technology allows a segment of memory on a remote device to be managed and used as memory on the local device. Therefore, once a segment of memory on one device is allocated to another, other devices cannot access that memory; that is, "memory sharing" on remote devices is not possible. This approach severely limits its application scenarios and cannot meet complex memory access requirements.

[0005] In summary, existing methods for accessing the memory of remote devices cannot balance various performance aspects (such as latency and access permission sharing) in data transmission, resulting in poor transmission performance. Summary of the Invention

[0006] This application provides a method, apparatus, and system for accessing the memory of a remote device, which can take into account various performance aspects of data transmission, such as latency and access permission sharing, thereby improving the efficiency of data transmission.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, embodiments of this application provide a method for processing a request. This method is executed by a first node, as described below. The first node is a device sending the request, a component within that device (such as a chip), or other components that support the function of sending a request. Specifically, the first node obtains a corresponding physical address based on a first virtual address, which is the virtual address in a first request. The first request is used to request reading data from a second node or to request writing data to the second node. The first node sends a second request to the second node based on a first mapping relationship, which is a mapping relationship between the physical address and a bus address. The second request corresponds to the first request and includes the bus address, which indicates the virtual address corresponding to an instance within the second node.

[0009] In this application, the term "bus" is used not only for the transmission path or data link of signals and data within the same device or node, but also to indicate the transmission path or data link of signals and data between different nodes. It can be considered that the "bus" in this application can cover the functions of the terms "bus" and "network" in the prior art; that is, this application expands the usage scenarios of the term "bus." This is to extend the use of instructions (such as read and write instructions) for accessing data from a local device to accessing data from a remote device, thus eliminating the need to distinguish between local and remote device data access in terms of request format and processing flow, and eliminating the need to encapsulate requests and data through remote network communication protocols when accessing remote devices. To distinguish it from traditional buses, the bus used for communication between different nodes in this application is also called a High Performance Interconnect Bus (HPIB).

[0010] Therefore, the bus address is a novel concept proposed in this application. The bus address can indicate the virtual address corresponding to an instance in another node (i.e., a remote device, such as the second node) and is carried in data access requests sent to other nodes (such as the second node). In some scenarios, each bus address is globally unique. "Global" may refer to the entire network or a defined area within the network, such as a domain, a building, an industrial park, or a city. Setting a globally unique bus address allows for unambiguous indication of the virtual address of an instance within this "global" scope, thereby simplifying address translation and addressing, and improving the efficiency of data access.

[0011] It should be understood that the above process can access the storage medium of the second node to read or write data. This storage medium is a medium that the instance of the second node can use, such as memory, cache, and other storage devices.

[0012] It should be understood that the virtual address corresponding to an instance, also known as the instance's virtual address, is the virtual address within the virtual address space allocated to the instance by the operating system. The virtual address space consists of one or more virtual address segments. Through this virtual address, the instance can use the physical address corresponding to that virtual address, also known as the instance's physical address, which means using real hardware resources. The process of obtaining the corresponding physical address based on the first virtual address in the above method is the address translation process performed by an instance in the first node.

[0013] It should be understood that accessing the storage medium in the second node means reading data from the second node or writing data to the second node. Of course, it's also possible to both read and write, that is, to request to read data from one location in the second node and to write data to another location in the second node. Specifically, a single second request could include both read and write instructions. The storage medium in the second node could be, for example, the memory within the second node, or other devices within the second node that have data storage capabilities.

[0014] It should be understood that, in cases where the first request is used to write data to the second node, the second request sent to the second node should at least carry the data to be written. This data may be issued by the application on the first node, or it may be obtained by the operating system of the first node from the storage medium of the first node. The data in the second request may come from the first request, or it may be added during the process of obtaining the second request based on the first request.

[0015] In summary, the first request can be triggered by a service, application, or user operation running on the first node, carrying a first virtual address. Based on the physical address corresponding to the first virtual address and the first mapping relationship, the first node obtains a second request corresponding to the first request. Since the bus address corresponds to an instance in the second node, the first node can send this second request to the second node. That is, the second request at least changes the physical address in the first request to the corresponding bus address. The bus address indicates the virtual address corresponding to the instance in the second node, not the physical address of the instance.

[0016] It should be understood that a node's physical address can only be managed or accessed by one node. Since the bus address is a virtual address, it can be accessed by the first node through a first request, and similarly by a second node or other nodes through requests. This means address sharing can be achieved during data access. Furthermore, using the bus address without relying on network access semantics reduces latency and increases access speed compared to existing network communication technologies. In other words, it balances performance in terms of both latency and access permission sharing during data transmission.

[0017] In one implementation, the first node includes a bus-side device, which is used to communicate with the second node using the first mapping relationship.

[0018] Through the bus-side device, the first node can access data from other nodes via the bus used for inter-node communication. This bus, also referred to in this application as a "high-performance bus," can be understood as the physical line used for communication between nodes. The bus-side device is used to use the first mapping relationship and the first mapping table containing the first mapping relationship, but it does not edit or manage the first mapping relationship (table), meaning it does not change the information recorded in the first mapping relationship (table) during use. The driver of the bus-side device manages the first mapping relationship table, specifically managing the entries in the first mapping relationship table, such as initialization, assignment, modification, and updating. It should be understood that the driver of the bus-side device is a software module that is installed and runs in the operating system of the first node so that the operating system of the first node can use the bus-side device.

[0019] Correspondingly, the physical address is an address within the physical address space of the bus-side device of the first node. This means that the physical address space (which is simply a segment of physical addresses) belongs to the bus-side device of the first node, meaning it is managed by the bus-side device of the first node, or in other words, is accessible to the bus-side device of the first node. In existing technologies, the physical address of an instance is generally the physical address space corresponding to the Dynamic Random Access Memory (DRAM) in the node, or the physical address space of an input / output (I / O) device, managed by the operating system. This is because the instance is launched by the operating system and is naturally assigned a physical address that the operating system can manage. However, this method is different; the physical address of the instance belongs to the physical address space corresponding to the bus-side device. In other words, the virtual address carried in the first request must be able to be mapped to the physical address space corresponding to the bus-side device in order to be processed by the bus-side device and sent to other nodes. Specifically, these physical address spaces can be determined by the Basic Input / Output System (BIOS) in consultation with these devices before the operating system is installed, and then reported to the operating system by the BIOS after the operating system is running.

[0020] In one implementation, the bus address includes the identifier of the bus-end device in the second node and a second virtual address. The bus-end device in the second node is used for communication between the second node and the first node. The second virtual address is related to the instance. The second virtual address is mapped to a physical address in the instance's physical address space, and a bus address should be uniquely mapped to one or more physical addresses, thereby implementing the address mapping described in this application. This application does not limit the implementation of the second virtual address. In one implementation, the second virtual address is the address in the instance's virtual address space (in this case, the bus address usually also includes the instance's identifier); in another implementation, the assignment of the second virtual address is custom-defined, for example, each second virtual address is different and corresponds to a different physical address. Furthermore, while the second virtual address is related to the instance, it requires other information about the bus address, such as the identifier of the bus-end device in the second node, together with the second virtual address, to indicate the virtual address corresponding to the instance in the second node.

[0021] For ease of management, the identifiers of bus-side devices and their multiple custom secondary virtual addresses are all unique within a domain (either a global domain or a domain composed of one or more local domains). For example, a building, a residential community, a data center, or a city can all be considered a domain.

[0022] In other words, to complete the above method, the second node must also include a bus-side device, and the data processing method described above is performed through the bus-side device in the first node. This allows requests to be sent to the second node via the bus address, and the second node can also execute the request based on the bus address. Furthermore, both the first and second nodes can include multiple bus-side devices.

[0023] In another implementation, the bus address also includes the instance's identifier. Therefore, an instance's virtual address can be directly indicated by a single virtual address. For example, this virtual address could be globally unique within the second node. Alternatively, an instance's virtual address can be indicated by combining the instance identifier with the virtual address; in this case, different instances within the second node might have the same virtual address value.

[0024] In some implementations, the instance identifier also indicates the virtual address space corresponding to the instance. That is, this application does not restrict the implementation method of the instance identifier, as long as it can distinguish different instances within a node. Since different instances within a node typically correspond to different virtual address spaces, the name or value of the virtual address space corresponding to the instance can also be directly used as the instance identifier.

[0025] In one implementation, the first node stores a first mapping table, which indicates multiple mapping relationships, including the first mapping relationship, wherein each of the multiple mapping relationships is a mapping between a physical address and a bus address.

[0026] This application does not limit the implementation form of the first mapping table, nor the way in which multiple mapping relationships, including the first mapping relationship, are carried in the first mapping table. The mapping table can be a single table or a multi-level table, such as a multi-level linked list. Thus, the first mapping relationship can be recorded in a row or column of a single table, or it can be recorded in an entry of a multi-level linked list. This entry can span multiple levels, and the physical address and the corresponding bus address may be at different levels. That is to say, the implementation method of an entry in the first mapping table is also not limited; an entry is used to represent a mapping relationship between a physical address and a bus address.

[0027] The first mapping table can also be a page table. Since page tables are segmented and layered according to physical addresses, their contents simply record the corresponding bus addresses. This facilitates management and use. The first mapping table can be stored in the memory of the first node, with a portion cached in the bus-side devices, similar to the Translation Lookaside Buffer (TLB) in a Memory Management Unit (MMU). This reduces the number of memory accesses by the bus-side devices.

[0028] In one implementation, the method further includes: obtaining the address space in the second node, the address space indicating at least one bus address; and updating the first mapping table based on the obtained address space in the second node, so that the updated first mapping table includes at least one entry corresponding to the at least one bus address indicated by the address space. It is evident that obtaining the shared address space in the second node (sharing means allowing access by nodes other than the second node) and maintaining the shared address space in the first mapping table ensures that the first node can access its storage space through the first mapping table and the bus address, and that updating the first mapping table allows the first node to synchronize information provided by the second node.

[0029] This describes a method for updating the first mapping table, which is updated by the driver of the bus-side device. It should be understood that any addition or replacement of content in the first mapping table can be considered an update. For example, filling an empty first mapping table with the content of an entry, adding one or more new entries to an existing first mapping table (e.g., one that already contains several entries with content), or replacing the content of one or more entries that were originally stored in the first mapping table.

[0030] The address space acquired from the second node is the address space accessible to other nodes within that second node. This space can be obtained by the second node notifying the first node, or by the first node actively querying the second node or the management node in the communication system that includes both the first and second nodes. The representation of the acquired address space is not limited in this application. For example, it can be represented by two addresses (i.e., a start address and an end address), or by one address and an address offset.

[0031] Accordingly, in a second aspect, embodiments of this application provide a method for processing a request. This method is executed by a second node, which is a device for processing the request, a component within that device (such as a chip), or other component capable of processing the request to access a corresponding storage medium. The method includes: receiving a request from a first node, the request being for reading data from the second node or for writing data to the second node, the request including a bus address indicating a virtual address corresponding to an instance in the second node; and obtaining, based on the bus address and a second mapping relationship, the physical address in the storage medium of the second node corresponding to the request, to execute the operation indicated by the request, wherein the second mapping relationship is a mapping between the bus address and the physical address corresponding to the request.

[0032] As can be seen, the second aspect corresponds to the first aspect, supplementing the description of the first aspect from the perspective of the second node. Many terms in the second aspect correspond to those in the first aspect. For example, "request from the first node" corresponds to "second request sent by the first node" in the first aspect. Therefore, the explanations of various words or sentences in the first aspect (such as "second request" in the first aspect being "request from the first node" in the second aspect), as well as the descriptions of technical effects, if they are mentioned in the second aspect, are equally applicable and will not be elaborated further.

[0033] The physical address corresponding to the request is the physical address where the data to be read or written, as indicated by the request, is located. The physical address corresponding to the request belongs to the physical address space of the instance in the second node, which is why it can be determined through the virtual address of the instance.

[0034] As can be seen from the method flow described in the second aspect, although the bus address in the request indicates the virtual address corresponding to the instance in the second node, the instance in this second node is unaware of the request processing process. Thus, the main purpose of this instance is to share its corresponding address space (physical address space and corresponding virtual address space), allowing the first node to send requests to read or write data in the address space corresponding to this instance.

[0035] In one implementation, the second node includes a bus-side device for processing requests from the first node based on the second mapping relationship. Therefore, the second node receiving the request also needs to include a bus-side device in order to connect to the bus, receive the request from the first node, and process it.

[0036] In one implementation, the bus address includes the identifier of the bus-end device and a second virtual address, which is related to the instance.

[0037] For ease of management, the identifier of a bus-end device can be unique within a certain domain (global or local).

[0038] In this case, the second mapping relationship is the mapping relationship between the second virtual address and the physical address corresponding to the request. The physical address corresponding to the request is the physical address that the request wants to access to read or write data. For example, the physical address and the second virtual address may correspond to the same instance; the second virtual address could be the virtual address corresponding to that instance, while the physical address belongs to the physical address space corresponding to that instance.

[0039] In one implementation, the second node stores a second mapping table, which indicates multiple mapping relationships, including the second mapping relationship. Each of the multiple mapping relationships is a mapping between a virtual address in the second node and the physical address corresponding to the virtual address in the second node.

[0040] As can be seen, in order to complete the communication between the first node and the second node, the second mapping relationship stored in the second node should match the bus address in the request from the first node, so that the physical address that needs to be accessed can be obtained. In the second node, the second mapping table containing the second mapping relationship also maintains multiple entries indicating the mapping between the virtual address in the second node and the physical address in the second node.

[0041] In one implementation, the second mapping table is updated by the driver of the bus-side device.

[0042] In one implementation, the method further includes: obtaining an address allocation request for the instance, the address allocation request indicating that the instance provides the physical address space corresponding to the instance; and updating the second mapping table based on the address allocation request, so that the updated second mapping table includes at least one entry corresponding to the physical address space corresponding to the instance.

[0043] This instance can provide all or part of its corresponding physical address space. In other words, updating the second mapping table based on the address allocation request aims to demonstrate that the instance can share address segments within its corresponding physical address space in this manner. This application does not restrict which segment(s) are shared, or the length of an address segment.

[0044] As can be seen, the second device obtains the address allocation request from the instance within the second device. This address allocation request can be actively sent by the instance, such as by the driver of the bus-side device, or it can be actively obtained by the second device itself. Therefore, the second node can share an address range within the second device through instances running on the second node or devices accessible by those instances, presenting it in the form of a second mapping table for other nodes to access one or more address ranges within this range. This address range represents the physical address space corresponding to the instance, typically residing in the second node's memory, but it can also reside in other storage devices on the second node.

[0045] The implementation of the second mapping table is similar to that of the first mapping table; please refer to the description of the first mapping table in the first aspect for details. Therefore, the updated second mapping table includes at least one entry corresponding to the physical address space of the instance. This entry may contain a virtual address recorded in a portion of the entries in the second mapping table, which is the virtual address corresponding to the instance. In other words, the entries in the second mapping table may not record one or a segment of addresses in the physical address space corresponding to the instance, but they may record the virtual address corresponding to the physical address in that physical address space.

[0046] The second aspect also describes another implementation of the bus address, and correspondingly, the way the second node uses and manages the bus address is different from the implementation described above.

[0047] Specifically, the bus address also includes the instance's identifier. Typically, the instance identifier is the instance's name or number; however, other quantities can also be used as the instance identifier, as long as they can distinguish different instances. In one implementation, the instance identifier also indicates the virtual address space corresponding to the instance, and the physical address corresponding to the request belongs to the physical address space corresponding to that instance.

[0048] In one implementation, the second mapping relationship includes a mapping between the instance's identifier and the instance's page table base address, and a mapping between the second virtual address and the physical address corresponding to the request. The mapping between the second virtual address and the physical address corresponding to the request is recorded in the instance's page table. The page table base address is the starting address of the page table, i.e., the starting location where a page table is stored. By adding an offset to the base address, an address segment can be indicated, and the page table can be stored in the storage space indicated by this address segment. When the instance is a process, the instance's page table base address is the starting storage location of the process's page table in memory, and can be used to refer to the physical address of the process's page table.

[0049] As can be seen, when the bus address includes the instance identifier, the second mapping relationship comprises two parts. This allows the instance's page table base address to be retrieved using the instance identifier, thus locating the instance's page table. Within the instance's page table, based on the second virtual address, the physical address required to respond to a request from the first node can be found—that is, the physical address corresponding to the request from the first node. When the instance is a process, the existing process page table can be reused to maintain the mapping between virtual and physical addresses, which is more convenient. Process page tables are typically used by the Input / Output Memory Management Unit (I / O Memory Management Unit) and the Memory Management Unit (MMU). Of course, in some implementations, they can also be used by bus-side devices.

[0050] In one implementation, the second node stores a third mapping table, which includes multiple entries. The mapping between the instance's identifier and the instance's page table base address is recorded in one of the multiple entries. Each of the multiple entries is used to record information about the instance in the second node, including the instance's identifier and the instance's page table base address.

[0051] As can be seen, when the bus address includes the instance identifier, in some implementations, the two tables maintained in the second node—namely, the third mapping table and the instance's page table—will participate in the above method. This application does not limit the implementation of the third mapping table; for example, the third mapping table can be a mapping table in the second node used to record and manage instances in the second node. This application also does not limit the format of the entries in the third mapping table; for example, the entries may include information other than the instance identifier and the instance's page table base address.

[0052] Similar to the second mapping table, this third mapping table is updated by the driver of the bus-side device.

[0053] In one implementation, the second aspect of the method further includes: updating the third mapping table based on the information of the instance in the second node, so that the updated third mapping table includes an entry corresponding to the information, the information including the instance identifier and the instance's page table base address.

[0054] The update method for the third mapping table is similar to that of the second mapping table, and will not be elaborated here. Information about instances in the second node is typically collected by modules within the second node's operating system, and the drivers for bus-side devices also run within the operating system. Information about instances in the second node can also be proactively reported by the instance to the bus-side device driver when the instance is created or put into use.

[0055] The address translation process described in the second aspect can be performed entirely by the bus-side device or entirely by the input / output memory management unit when the bus address does not include the instance identifier. Similarly, when the bus address does not include the instance identifier, it can be performed entirely by the bus-side device, entirely by the input / output memory management unit, or, as mentioned above, by the bus-side device querying the third mapping table and the input / output memory management unit querying the instance's page table in coordination. This application does not limit the devices or specific processing procedures involved in the address translation process.

[0056] Thirdly, embodiments of this application provide a system for processing requests, characterized in that the system includes a first processor, a memory management unit (MMU), a first bus terminal device, a second processor, a storage medium, and a second bus terminal device. The second processor runs an instance, and the physical address space of the instance points to the storage medium. The MMU is used to obtain a physical address corresponding to a first virtual address based on a first request from the first processor. The first request is used to request to read data or to request to write data, and the first request includes the first virtual address. The first bus terminal device is used to send a second request to the second bus terminal device based on a first mapping relationship, where the first mapping relationship is a mapping relationship between the physical address and the bus address. The second request corresponds to the first request and includes the bus address, which indicates a virtual address corresponding to the instance. The second bus terminal device is used to receive the second request. The second bus terminal device is also used to process the second request based on the bus address and the second mapping relationship to obtain a result corresponding to the request. The second mapping relationship is a mapping relationship between the bus address and the physical address corresponding to the second request, and the physical address corresponding to the second request belongs to the physical address space of the instance.

[0057] As can be seen, the third aspect corresponds to the first and second aspects, describing the solution from a system perspective. In one implementation, the system in the third aspect can be considered to include two nodes. One node includes a first processor, a memory management unit (MMU), and a first bus-side device, corresponding to the first node mentioned earlier. The other node includes a second processor, storage media, and a second bus-side device, corresponding to the second node mentioned earlier. The first and second processors run different operating systems. Many terms in the third aspect correspond to those in the first and second aspects. Therefore, the explanations of various words or sentences, descriptions of various implementation methods, and descriptions of technical effects in the first and second aspects, if they are relevant to the third aspect, are equally applicable and will not be repeated here.

[0058] It should be noted that when an instance's physical address space points to the storage medium, it means that the physical address space that the instance can use belongs to the storage medium, or in other words, the physical storage resources that the instance can use are a part of the storage medium.

[0059] In the above system, when the bus address does not include the instance identifier, the second bus end device is specifically used to access the physical address in the storage medium corresponding to the request through the second virtual address in the bus address and the second mapping relationship, so as to perform the operation indicated by the request, such as reading the data stored in the physical address, or writing the data in the second request into the physical address.

[0060] In the case where the bus address does not include the instance identifier, the system also includes an Input / Output Memory Management Unit (IOMMU). The IOMMU is used to find the physical address corresponding to the request through the instance's page table, to perform the operation corresponding to the second request, and to return the result of the operation to the second bus end device. Correspondingly, the second bus end device is used to find the instance's page table base address based on the bus address and the mapping between the instance identifier and the instance's page table base address, and to pass the instance's page table base address to the IOMMU.

[0061] Of course, the system can always include an IOMMU while being compatible with both of the above implementations.

[0062] Fourthly, embodiments of this application provide an apparatus for processing requests, the apparatus being located at a first node, characterized in that the apparatus includes: a processing module, the processing module being configured to send a first request to an address translation module, the first request being configured to request reading data from a second node, or request writing data to the second node;

[0063] The address translation module is used to obtain the corresponding physical address based on the first virtual address, which is the virtual address in the first request; the bus communication module is used to send a second request to the second node based on the first mapping relationship, which is the mapping relationship between the physical address and the bus address, the second request corresponds to the first request, the second request includes the bus address, which indicates the virtual address corresponding to the instance in the second node.

[0064] The address translation module in the fourth aspect is equivalent to the bus-side device described above.

[0065] The fourth aspect is an apparatus corresponding to the method of the first aspect, which has the function of implementing the request processing method in any implementation of the first aspect. This function can be implemented by hardware or by a combination of software and hardware. The hardware or software includes one or more modules corresponding to the above-described function. Many terms in the fourth aspect correspond to those in the first aspect, and are also related to the method of the second aspect and the system of the third aspect. Therefore, the descriptions of various words or sentences, the descriptions of various implementation methods, and the descriptions of technical effects in the first, second, and third aspects, if they are relevant to the fourth aspect, are equally applicable therewith and will not be repeated here.

[0066] Fifthly, embodiments of this application provide an apparatus for processing requests, the apparatus being located at a second node, characterized in that the apparatus includes: a processing module and a storage medium, the processing module being used to run an instance, the physical address space of the instance pointing to the storage medium; a bus communication module being used to receive a request from a first node, the request being used to read data or to write data, the request including a bus address, the bus address indicating a virtual address corresponding to the instance, and also being used to process the second request based on the bus address and a second mapping relationship to obtain a result corresponding to the request, the second mapping relationship being a mapping relationship between the bus address and the physical address corresponding to the request, the physical address corresponding to the request belonging to the physical address space of the instance.

[0067] The address translation module in the fifth aspect is equivalent to the bus-side device described above.

[0068] The fifth aspect is an apparatus corresponding to the method of the second aspect, which has the function of implementing the request processing method in any implementation of the second aspect. This function can be implemented by hardware, or by a combination of software and hardware. The hardware or software includes one or more modules corresponding to the above-described function. Many terms in the fifth aspect correspond to those in the second aspect, and are also related to the method of the first aspect and the system of the third aspect. Therefore, the descriptions of various words or sentences, various implementation methods, and descriptions of technical effects in the first, second, and third aspects, if they are mentioned in the fifth aspect, are equally applicable and will not be repeated here.

[0069] In a sixth aspect, embodiments of this application provide a chip, which includes a processing circuit and a storage medium storing instructions; when the instructions are executed by the processing circuit, the chip performs a processing request method as described in any of the preceding aspects.

[0070] In a seventh aspect, embodiments of this application provide an apparatus for processing requests. The apparatus includes: a storage medium, a processing circuit, a memory management unit (MMU), and a bus-side device. The storage medium is coupled to the processing circuit and is used to store computer program code, which includes computer instructions. When the computer instructions are executed by the processing circuit, the following method is performed: the memory management unit (MMU) obtains a corresponding physical address based on a first virtual address, the first virtual address being a virtual address in a first request, the first request being used to request reading data from another device or to request writing data to the other device; the bus-side device sends a second request to the other device based on a first mapping relationship, the first mapping relationship being a mapping relationship between the physical address and a bus address, the second request corresponding to the first request, the second request including the bus address, the bus address indicating the virtual address corresponding to an instance in the other device.

[0071] The seventh aspect is an apparatus corresponding to the method of the first aspect, which has the function of implementing the method for processing requests in any implementation of the first aspect. Many terms in the seventh aspect correspond to those in the first aspect, and are also related to the method of the second aspect and the system of the third aspect. Therefore, the descriptions of various words or sentences, the descriptions of various implementation methods, and the descriptions of technical effects in the first, second, and third aspects, if they are relevant to the seventh aspect, are equally applicable and will not be repeated here.

[0072] Eighthly, embodiments of this application provide an apparatus for processing requests. The apparatus includes: a storage medium, a processing circuit, and a bus-side device. The storage medium is coupled to the processing circuit and stores computer program code, which includes computer instructions. When the processing circuit executes the computer instructions, it instructs the bus-side device to perform the following methods: receiving a request from another device for reading data from the device or writing data to the device, the request including a bus address indicating a virtual address corresponding to an instance in the device; and obtaining, based on the bus address and a second mapping relationship, a physical address in the storage medium of the device corresponding to the request, to perform the operation indicated by the request, wherein the second mapping relationship is a mapping relationship between the bus address and the physical address corresponding to the request.

[0073] The eighth aspect is an apparatus corresponding to the method of the second aspect, which has the function of implementing the request processing method in any implementation of the second aspect. Many terms in the seventh aspect correspond to those in the second aspect, and are also related to the method of the first aspect and the system of the third aspect. Therefore, the descriptions of various words or sentences, the descriptions of various implementation methods, and the descriptions of technical effects in the first, second, and third aspects, if they are mentioned in the eighth aspect, are equally applicable and will not be repeated here.

[0074] The ninth to fourteenth aspects below correspond to the first, second or third aspects. The descriptions of various words or sentences, the descriptions of various implementation methods and the descriptions of technical effects in the first, second and third aspects shall also apply to the following aspects if they are involved, and will not be repeated here.

[0075] A ninth aspect provides a communication device, comprising: a processor; the processor being configured to be coupled to a memory, and after reading instructions from the memory, to execute a processing request as described in any of the preceding aspects according to the instructions.

[0076] In a tenth aspect, embodiments of this application provide a communication device, which can be a chip system including a processor and a memory, for implementing the functions of the methods described in any of the preceding aspects. The chip system can be composed of chips or may include chips and other discrete devices.

[0077] Eleventhly, a communication device is provided, which may be a circuit system including a processing circuit configured to perform the method as described in any of the preceding aspects.

[0078] In a twelfth aspect, embodiments of this application also provide a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the methods described above.

[0079] In a thirteenth aspect, embodiments of this application also provide a computer program product, including instructions that, when run on a computer, cause the computer to perform the methods described above.

[0080] In a fourteenth aspect, embodiments of this application provide a system including means for processing requests according to any of the fourth aspects and means for processing requests according to any of the fifth aspects. Attached Figure Description

[0081] Figure 1 A schematic diagram of an architecture for processing requests provided in an embodiment of this application;

[0082] Figure 2This is a schematic diagram illustrating a process by which a source accesses the memory of a destination via a bus address, as provided in an embodiment of this application.

[0083] Figure 3 A schematic diagram of the shared memory management architecture provided in an embodiment of this application;

[0084] Figure 4 This is a schematic diagram of the device provided in the embodiments of this application;

[0085] Figure 5a A schematic diagram of the architecture of a system for processing requests provided in an embodiment of this application;

[0086] Figure 5b A schematic diagram of the architecture of another system for processing requests provided in an embodiment of this application;

[0087] Figure 6 A schematic diagram of an apparatus (corresponding to the first node) for processing requests provided in an embodiment of this application;

[0088] Figure 7 A schematic diagram of another apparatus for processing requests (corresponding to the second node) provided in an embodiment of this application;

[0089] Figure 8 A schematic diagram of a device (corresponding to the first node) for processing requests, provided as an embodiment of this application;

[0090] Figure 9 This is a schematic diagram of another device (corresponding to the second node) for processing requests, provided in an embodiment of this application. Detailed Implementation

[0091] First, some expressions that may appear in this application will be explained.

[0092] "First" and "second" are used to distinguish different objects or to differentiate different treatments of the same object, rather than to describe a specific order of objects.

[0093] "At least one" means one or more, while "more" means two or more.

[0094] "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone. A and B can be singular or plural.

[0095] The character " / " generally indicates that the objects before and after it are in an "or" relationship. For example, A / B can mean A or B.

[0096] Furthermore, the terms "comprising," "including," and "having" used in the description of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0097] It should be noted that in this application, the terms "exemplary" or "for example" are used to indicate that something is being described or illustrated. Any implementation or design scheme described as "exemplary" or "for example" (such as the embodiments in this application) should not be construed as being more preferred or advantageous than other implementations or design schemes. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0098] In the specification and drawings of this application, the terms "of", "relevant", and "corresponding" may sometimes be used interchangeably. It should be noted that when the distinction is not emphasized, they have the same meaning.

[0099] Below is a brief description of some of the terms used in this application.

[0100] An instance is a software module that can run applications or system programs. A software module is only considered an instance when it is run by the operating system; otherwise, it is just a piece of code. Instances can take many forms; for example, processes and threads can both be understood as types of instances. Instances run on nodes.

[0101] Node: A node is a device that has at least one of the functions of processing and storing data. Nodes run an operating system, and nodes can be distinguished by their operating systems; that is, different nodes run different operating systems. Alternatively, the hardware and software used to run an operating system can be considered to belong to the same node. In this application, a node can be a complete physical machine, such as a terminal or a network device like a server or server proxy. A node can also be a component within a physical machine, such as a processor, memory, or storage device. When a physical machine includes two nodes running different operating systems, for example, a physical machine including a Central Processing Unit (CPU) running Operating System 1 and a Graphics Processing Unit (GPU) running Operating System 2, then the CPU and GPU can be considered to belong to different nodes. When a node is a component, it is a relatively independent entity in terms of hardware. "Independent entity" can be understood as a circuit or module with a specific function, and this component is packaged or assembled on a physical machine. Data access in this application can be understood as one node accessing data maintained by another node through an instance. Devices within a node refer to components or parts within that node. For example, when a node is a physical machine, the CPU and memory are devices within that node. A physical machine refers to a computer packaged as a product, such as a server, desktop computer, all-in-one PC (AIO), laptop, or smartphone.

[0102] Terminals can include desktop, laptop, handheld, and vehicle-mounted user equipment (UE) devices, such as smartphones, cellular phones, desktop computers, tablets, smart TVs, smart TV boxes, ultra-mobile personal computers (UMPCs), laptops, personal digital assistants (PDAs), portable multimedia players (PMPs), dedicated media players, consumer communication devices, wearable devices (such as smartwatches), AR (augmented reality) / VR (virtual reality) devices, and other types of communication devices.

[0103] Local: For an instance, the node running that instance is local. For example, local memory, in full, should be "the local memory of an instance," which refers to the memory of the node running that instance. The node running an instance can be described at different granularities. For example, it can be just a processor, such as a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU), or it can be a complete physical machine, including processing circuitry and storage media. The specific description used depends on whether the data access process involves crosses physical machines.

[0104] Remote: Remote is a concept relative to "local". That is, for an instance, all nodes other than the node running the instance are remote. Remote can be a device with computing power or a device used to store data.

[0105] Global: The scope of "global" refers to a group of nodes that are equipped with the bus-side devices described in this application and can read and write data to each other using the methods described in this application. This application does not limit the location and scope of this group of nodes in the actual space. For example, this group of nodes can be within a data center, across data centers, within a corporate campus, or across cities or countries.

[0106] An identifier is used to distinguish one thing from others of the same or different categories. Examples include node identifiers, network identifiers, and network interface card (NIC) identifiers. An identifier can be a name, a number, or a distinctive characteristic, such as a category identifier. This application does not limit the implementation of various identifiers, as long as they can make a distinction. For example, in some implementations of this application, the identifier of the instance's virtual address space is used as the instance identifier, instead of the more common method of using the instance's name or number.

[0107] Address space, also called storage space, refers to one or more segments of addresses that can be used by a device or instance. For example, the virtual address space of a device or instance is the segment or more virtual addresses that can be used by that device or instance. The virtual address space of a device or instance is allocated by the operating system running that device or instance. Similarly, the physical address space of a device or instance is the segment or more physical addresses allocated to that device or instance. When a device or instance uses this physical address space, other devices or instances cannot use addresses within that physical address space. An instance's physical address space is allocated by the operating system running that instance. This allocation may be dynamic; for example, as the instance runs, the physical address space it occupies may increase, but there is an upper limit. The size and range of a device's physical address space are usually fixed.

[0108] Page table: A data structure used to record the mapping relationship between two types of data. It is typically used to translate virtual addresses into physical addresses. Hierarchical page tables are also a type of page table. Page tables are stored in storage media. The base address of the page table, also simply called the page table base address, refers to the starting address of the physical address that stores the page table. The size of the page table determines the range of virtual addresses corresponding to it. The virtual address in the page table is the virtual address of the instance or device using the page table, indicating the offset of the physical address of a certain location (or entry) in the page table relative to the page table base address. The data stored at a certain location in the page table is the physical address in the physical address space of the instance or device using the page table. A page table includes multiple entries, each indicating a mapping relationship between a virtual address and a physical address of the instance or device using the page table. It should be understood that the entry here is a functional description; the specific implementation of the entry is not limited in this application. For example, the mapping relationship between a virtual address and a physical address may be hierarchical, or it may be indirect. This application does not limit the specific implementation of the page table; for example, it can be a multi-level page table, a hash table, etc.

[0109] Process page table: also known as process page table, records the mapping relationship between virtual addresses in a process's virtual address space and physical addresses in the process's physical address space.

[0110] Bus: In existing technologies, a bus is an internal structure of a computer, serving as a common communication trunk for transmitting information between various functional components. A computer bus can be divided into a data bus, an address bus, and a control bus, used to transmit data, data addresses, and control signals, respectively. In this application, "bus" is short for High Performance Interconnect Bus (HPIB), which can connect various components within a single computer and can also replace a network, laying infrastructure between different computers to connect them. Each computer accesses the HPIB through a bus-end device, which is equivalent to a network interface card (NIC) or baseband antenna in network technology. This application describes how, after the hardware is deployed, the bus's functions are used to process requests for reading or writing data, i.e., accessing remote storage media. This application does not provide a detailed description of the specific structure of HPIB and bus-end devices.

[0111] Memory semantics refers to the communication instructions used when various devices connected via a bus in a physical machine communicate with each other. This communication, also known as bus communication, is between different instances or devices belonging to the same operating system and therefore does not require network communication technology. Load / store instructions are typical examples of memory semantics.

[0112] Existing communication technologies can be divided into network communication and bus communication. Communication involves the exchange of information, which can be the transmission of data or commands. Network communication is used between local and remote devices. Transmitted messages are typically encapsulated by the operating system's protocol stack and use network communication protocols. Network communication typically uses send / receive commands or read / write commands from Remote Direct Memory Access (RDMA) to transmit information. These semantics require establishing a connection before use, a process known as "connection establishment." As the cluster size increases, the overhead of connection establishment becomes very large. Furthermore, while RDMA's network semantics bypass the protocol stack located in the operating system kernel and can effectively reduce end-to-end network latency, its asynchronous notification mechanism and the lengthy transmission process of the network card still limit further latency reduction.

[0113] Bus communication is used for communication between various devices connected via a bus within a single device. Bus communication uses memory semantics (such as load / store instructions) to transmit information. This memory semantics does not have the aforementioned limitations, and bus communication is faster than network communication. Existing technologies using memory semantics allow a local device to take over the memory of a remote device, essentially treating the remote device's memory as an extension of the local device's memory—a kind of external storage module. The remote device then has no right to use or manage this memory, nor can it be used by other devices. This is because in existing solutions, the remote device reads and writes data through the physical address of the memory in the shared device. Thus, the memory indicated by that physical address is effectively allocated to the remote device, and the shared device has no right to manage that memory.

[0114] This application proposes a method for processing requests based on virtual address addressing, realizing remote memory semantics. This addresses the issues of connection establishment overhead and high latency inherent in traditional network semantics while providing the foundation for sharing storage media (e.g., memory). The technical solution of this application also supports the sharing of remote storage media. For example, through configuration, processes on multiple nodes can map the same remote memory block to their local address space, thus achieving both remote memory sharing and unifying local and remote memory access behavior. In other words, using the technical solution described in this application, remote data can be accessed as if it were local data. Furthermore, the new communication technology described in this application unifies the bus technology used for communication between devices locally (i.e., within a single device) and the network technology used for communication between local and remote devices. That is, it no longer distinguishes between these two communication scenarios but uses the same communication method in both scenarios.

[0115] The following is based on Figure 1 This describes an architecture diagram applicable to this application. In the diagram, the controller 1001 can reside on the same node as other components or on different nodes, while the remaining components can be understood as belonging to a single node. It should be understood that... Figure 1 The described architecture includes node 100 and controller 1001, which is schematically shown not to be included in node 100. It should be understood that... Figure 1 The architecture described is merely an illustration for ease of understanding and is not intended to limit the architecture that can be used for the nodes mentioned in this application. Other software components of the node 100, such as the operating system and other hardware components, such as the display, are not shown.

[0116] The architecture comprises both hardware and software. Specifically, the hardware includes:

[0117] The Central Processing Unit (CPU) 1004 and the Memory Management Unit (MMU) 1005 are typically packaged into a single chip. When the CPU runs an application, it initiates requests to read or write data, hereinafter referred to as memory access requests, which are requests to access storage media, as reading or writing data requires locating an address in the storage medium (e.g., RAM). The MMU is responsible for translating the address of the memory access requests initiated by the CPU, that is, converting the virtual address in the memory access request into a physical address.

[0118] Memory (1006): Figure 1 The diagram uses memory as an example to illustrate the storage medium on this node. The physical form of this memory can be a memory module. In the method of this application, the memory is not only provided for use by local instances (e.g., processes), but can also be used by instances of other nodes. Instances of other nodes use this memory by requesting and following the method described in this application to write data to this memory or request to read data from this memory.

[0119] Input / Output Memory Management Unit (IOMMU) 1007: Similar in function to MMU 1005, but the IOMMU is responsible for translating the addresses of memory access requests from hardware other than the CPU. For example, if the hardware is memory, the memory access request is used to request writing data to memory or to request reading data from memory. The hardware other than the CPU can also be other devices with Direct Memory Access (DMA).

[0120] Bus End Device 1008: Also known as an End Point (EP), it is used to connect the node to the high-performance interconnect bus, acting similarly to a network interface card (NIC). A bus end device is typically a hardware module with address translation capabilities. Similar to a network interface card (NIC), a driver for the bus end device needs to be installed in the node's operating system for the system to use it. A node can include multiple bus end devices, just as a node can have multiple NICs. A node can contain both bus end devices and NICs. Figure 1 The network interface card (NIC) is not shown; only the bus-side devices are schematically indicated. If all remote communication of this node is conducted through the high-performance interconnect bus, meaning all information is exchanged using memory semantics, then this node can also consist only of bus-side devices. In actual cabling, the bus-side devices can be connected to the CPU, memory, or MMU at one end, and to the high-performance bus or a high-performance bus switch at the other end.

[0121] In one implementation, other devices in the node that involve data reading and writing (such as CPU and memory) can also have bus-side devices integrated as interfaces or communication modules, which are encapsulated together with these devices.

[0122] In one implementation, the functions of IOMMU1007 and bus-side device 1008 can be integrated onto a single chip, meaning they are deployed as a single hardware device. In this case, the bus-side device can also be considered to have the functions of IOMMU.

[0123] It should be understood that the address translation process in the destination or second node in this application can be performed entirely by the bus-side device, entirely by the input / output memory management unit, or jointly by the bus-side device and the input / output memory management unit. This application only illustrates this (see the examples from a system perspective below for details), but does not limit the specific implementation.

[0124] In this architecture, the controller 1001, a software module, maintains the global address space shared by instances across all nodes. "Shared" means that not only the node running the instance can access this address space, but other nodes can also access it. Specifically, the controller stores information about the globally shared address space and has management authority over this information. Logically, these global address spaces can be centrally managed by a single controller. In actual deployment, this logically centralized controller can be a dedicated server or server cluster, or it can be deployed directly on one or more nodes. A communication system involving multiple nodes can include one or more controllers, depending on the scale of the system. If multiple controllers are included, they can communicate using the techniques described in this application or existing network communication technologies, such as Transmission Control Protocol / Internet Protocol (TCP / IP). Therefore, the controller 1001 in the diagram may not belong to any of the nodes containing other components.

[0125] The software modules deployed on the same node as the aforementioned hardware include:

[0126] The bus-side device driver (EP driver) 1002 is a software module within the kernel of the operating system (OS) running on this node, used to drive the bus-side device hardware module. This driver has the same capability as other hardware drivers, enabling the operating system to sense and use the corresponding hardware. Additionally, this driver is used to configure, or rather update, the tables used by the bus-side device for translating bus addresses, such as the first and second mapping tables mentioned earlier.

[0127] Agent 1003: Used to manage the shared memory in the local node and communicate with controller 1001. Communication between Agent 1003 and controller 1001 can use the high-performance interconnect bus described in this application or via Ethernet. In one implementation, the driver of the bus-side device can also perform the function of managing the shared memory in the local node in the agent; that is, the above two modules are only a schematic division from a functional perspective.

[0128] The first virtual address mentioned above can be an address within the address range indicated by the virtual address space of an instance on the source side (i.e., the first node described above). This instance is the one executing the first request operation. From the perspective of the instance on the source side, the entire method implements the following: the instance runs the first request and obtains the result after running the first request. For example, if the first request is to read the storage medium of the second node, that is, to read data, then the result is that the requested data is obtained from the storage medium; as another example, if the first request is to write to the storage medium of the second node, that is, to write data, then the result is that the data is successfully written to the storage medium of the second node (e.g., memory). This process that the first instance can perceive is the same as reading / writing local storage medium. Therefore, from the perspective of the software on the source side, that is, for the processor running the instance on the source side, the process of reading local memory data and the process of reading remote memory data are unified. And if we further explore what kind of processing process is carried out to obtain the result corresponding to the first request, that is the method flow described in this application. This application describes the specific process of the above code implementation, which involves the hardware of the first node and the second node. However, from the perspective of software code, this instance can be considered as the executor of the first request, or in other words, the instance is the initiator of the first request.

[0129] Therefore, this application focuses on describing the process of the first node sending a request to the second node, and the second node performing the operation corresponding to the request, i.e., the request processing process. However, it does not describe in detail how the second node is notified after reading or writing data. This is because the implementation of subsequent parts can refer to the description of the request processing process. For example, the subsequent part involves sending feedback information from the second node back to the first node, where the address translation involved is equivalent to the reverse process of address translation described below. To save space, this application will not elaborate further. It should be understood that in the above scenario, the first node is the source node (also called the source end), and the second node is the destination node (also called the destination end). In other scenarios, the first node can be the destination node. Furthermore, since a node can communicate with multiple nodes simultaneously, or multiple devices within a single node, a node can be both a source node and a destination node.

[0130] The method for processing requests described in this application is described below. This description uses the example of a process in one node accessing the memory of another node. This method can also be called a multi-stage address translation mechanism based on virtual address addressing. This mechanism can be used in scenarios involving node interaction in the cloud, interaction between terminals, and interaction between terminal and cloud devices. In other words, either of these two nodes can be a terminal or a device in the network that can initiate memory access requests or share storage resources, such as a server.

[0131] In a scenario where a process accesses local storage within a node, address translation involves converting the virtual address (VA) used by the process into a physical address (PA), which is the address within the process's physical address space. Both the virtual and physical addresses are assigned to the process by the node's operating system. This address translation process is performed by the hardware MMU. In non-virtualized scenarios, there is a direct conversion between the virtual and physical addresses used by the process. However, in virtualized scenarios, two conversions are required: translating the process's virtual address to the virtual machine's physical address (Guest Physical Address, GPA), and then translating the GPA to the host physical address (HPA). The method described in this application does not address virtualized scenarios.

[0132] Similarly, when a process on one node (the source) needs to read or write memory on another node (the destination), the virtual address used by the process on the source node, referred to as the source virtual address (SVA), needs to be translated into the physical address on the destination node, referred to as the destination physical address (DPA). In this application, the source node communicates with the destination node via a High Performance Interconnect Bus (HPIB). Due to the cross-node nature, the address translation involves multiple stages: Source Virtual Address (SVA) -> Tagged Physical Address (TPA) on the source node -> Addressable Virtual Address (AVA) -> Destination Physical Address (DPA). The following describes each process in detail:

[0133] SVA->TPA: SVA is equivalent to the first virtual address in the first request mentioned earlier. Here, the first request is initiated by the process running in the source CPU, and TPA is equivalent to the physical address corresponding to the first virtual address. This part of the address translation can be performed by the MMU. For example, an existing MMU and process page table can be reused, that is, the process's virtual address is translated into the process's physical address. In this way, the source CPU, or the process, will not be aware that it is about to access the remote (i.e., the destination) memory, because this process is the same as the address translation for accessing local memory from the perspective of the source CPU and the process. For example, SVA is stored in the CPU's register, and the MMU uses it as the input for this address translation. The physical address recorded in the process page table is also stored in the register. The process page table can be multi-level. Therefore, when the process page table is reused to implement the address translation from SVA to TPA, the value of SVA is the offset relative to the base address of the process page table.

[0134] In reality, the SVA->TPA process differs from existing technologies, specifically in the TPA. The TPA belongs to the physical address space of the bus-side device, while existing local address translation processes translate physical addresses into the physical address space of Dynamic Random Access Memory (DRAM) or Input / Output (I / O). Specifically, the physical address space of the bus-side device to which the TPA belongs does not overlap with the aforementioned DRAM and I / O physical address spaces, because a single physical address space can only be assigned to one hardware module. Typically, this is determined through negotiation between the device and the BIOS during the node's Basic Input / Output System (BIOS) startup phase. Once the node's operating system boots, the BIOS notifies the operating system, preventing the OS from taking over the address space allocated to the bus-side device. The page table entries used in this process are configured by the bus-side device driver (EP driver). The page table entries include the physical address (TPA) belonging to the physical address space of the bus-side device. Other contents of the process page table can be found in the description of the process page table in the prior art.

[0135] TPA->AVA: This address translation is handled by the source hardware, specifically the source bus-side device. Here, AVA is equivalent to the aforementioned bus address, and the mapping relationship used in the translation is equivalent to the aforementioned first mapping relationship, which can be carried in the aforementioned first mapping table. After this address translation, a request that can be sent to the destination can be obtained, such as the second request in the preceding claims. The first mapping table can be a page table, because this address translation essentially translates the physical address into a virtual address, similar to the common function of a page table. This first mapping table is configured by the bus-side device's driver and is dedicated to the bus-side device's use; it is a different table from the process page table used in SVA->TPA. When the first mapping table is a page table, it can be understood as the page table of the bus-side device, because when the bus-side device receives a request or instruction including the bus address from other nodes, it also needs to use the first mapping table to find the corresponding physical address.

[0136] An AVA (Addressable Virtual Address) is called an addressable virtual address because it indicates a virtual address. Functionally, an AVA can find its corresponding physical address through subsequent operations or the mapping relationship stored in the second node. The information contained in the AVA should enable it to have addressing capabilities, that is, to send the second request to the destination via a high-performance interconnect bus. In other words, the AVA is equivalent to the destination address in network communication. The destination address in network communication ensures that the message is transmitted to the correct destination through the network.

[0137] In one implementation, the AVA consists of the End Point Identifier (EP ID) and the Destination Virtual Address (DVA).

[0138] A bus-end device identifier (EP ID) indicates a bus-end device and is unique within a domain. Therefore, a bus-end device identifier within a domain can also be called a Global Identifier (GID) for that domain. In some implementations, the bus-end device identifier can be configured to be globally unique. This effectively specifies which bus-end device should receive the second request. Since a node can include multiple bus-end devices, a node identifier is not used. The EP ID can be uniformly assigned within a domain by the controller (e.g., controller 1001).

[0139] A Virtual Address (DVA) is used to indicate the virtual address associated with a process running on the destination node (i.e., the process that shares the physical address corresponding to the DVA). This allows other nodes to access the physical memory on the destination node corresponding to that DVA as source nodes. The DVA can be registered by the destination process through the destination agent, so that the destination agent can synchronize this DVA to other nodes via the controller. This process is also known as the destination process sharing this DVA. Thus, other nodes can use this DVA as source nodes.

[0140] The DVA should be unique within the target operating system; that is, the value of each virtual address should be different within an operating system.

[0141] In one implementation, the DVA in the second node can be customized, and the virtual address space where the DVA resides can also be considered custom. In this implementation, the DVA is equivalent to the second virtual address in the bus address mentioned earlier. As long as the value of each custom DVA is different, and the mapping relationship between the multiple custom DVAs and multiple readable and / or writable physical addresses is stored in the second node, the method of this application can be executed. These multiple physical addresses can belong to the memory of the destination end or to other storage media of the destination end.

[0142] In another implementation, the DVA consists of an instance identifier and a Virtual Address (VA). In this implementation, the second virtual address in the bus address mentioned earlier is the virtual address (VA) within the DVA. The instance identifier is used to distinguish different instances within a node. The instance identifier included in a DVA also indicates which instance the virtual address (VA) belongs to. Therefore, within a node, different DVAs can carry the same VA value, and these identical VA values ​​should belong to different instances. This way, even if the VA carried in a DVA cannot be globally unique within a node, it will not cause confusion; different DVAs can still correspond to different virtual addresses in a second node.

[0143] The implementation method of instance identification is not limited; it can be the instance's own identifier or an address space identifier (ASID), where the instance's address space refers to the instance's virtual address space. For a DVA of an instance, if the instance is a process and the instance's identifier uses an ASID, then the VA in that DVA can use the virtual address indicated by the process's page table. In this way, the VA record can reuse the process page table. Thus, based on the page table base address of the process page table and the VA in the DVA, the physical address corresponding to the DVA can be obtained, and the page table base address of the process page table can be obtained through the ASID in the DVA.

[0144] In some implementations, the second request may include the following fields in addition to the fields corresponding to AVA:

[0145] The Read / Write field is used to identify whether the source process has read and / or write permissions to the destination memory.

[0146] The Cacheable field identifies whether the source CPU can cache data from the destination.

[0147] Optionally, you can also choose to include some of the following fields:

[0148] The Privilege field identifies the level of privilege required to access the memory of the destination, such as whether user-mode memory or kernel-mode memory can be accessed.

[0149] The identity verification field is used by the destination for security checks.

[0150] The above process occurs at the source end. After the second message is received by the bus-side device at the destination end, address translation is also required.

[0151] AVA->DPA: DVA in AVA has different implementations, and the corresponding address translation process is also different.

[0152] When the DVA does not include the instance identifier, the address translation at this stage is handled by the EP (Entity Transfer) of the second node. Alternatively, it may be handled by the IOMMU (In-Memory Management Unit) of the second node, in which case the EP reads the DVA from the request. The second node maintains the mapping relationship between DVA and DPA, which can be stored in a mapping table, such as the second mapping table described earlier. Since this is also a translation from virtual address to physical address, this second mapping table can also be a page table, which can be considered the page table of the second node's EP. The second mapping table requires the EP's driver to be configured in advance.

[0153] When a Data Address Translation (DVA) consists of an instance identifier and a virtual address, the address translation at this stage involves two sub-processes. First, based on the instance identifier, the table containing the virtual address—that is, the mapping table used by the instance—is located. The second node stores the mapping relationship between the instance identifier and the instance's address mapping table. Next, based on the instance's address mapping table, such as the third mapping table described earlier, the physical address (DPA) corresponding to this virtual address can be found, completing the address translation at this stage. The third mapping table stores the mapping relationships between multiple virtual addresses and multiple physical addresses. These multiple virtual addresses are all virtual addresses that can be carried in the Application Address Translation (AVA). When the instance is a process, the process page table can be used. In this case, the instance identifier can be the identifier of the process's address space, and the virtual address is the address in the process's virtual address space, which is also the offset of the process's page table base address. In this case, two mapping relationships are needed for the AVA to be translated into the DPA.

[0154] The above process can involve the destination end's EP (Executive Processor) first obtaining the base address of the process's page table based on the process's address space identifier, and then the destination end's IOMMU (In-Memory Management Unit) looking up the corresponding page table based on the VA (Version Availability) in the DVA (Application Value) to obtain the DPA (Device Page Address) corresponding to the AVA. Alternatively, the destination end's EP can be responsible for resolving the DVA from the request, while the destination end's IOMMU performs the process of obtaining the corresponding DPA from the DVA. Furthermore, the destination end's EP can handle both resolving the DVA from the request and obtaining the corresponding DPA from the DVA, without requiring the destination end's IOMMU. This application does not restrict how this process is specifically allocated at the destination end.

[0155] In summary, accessing the destination memory from the source requires at least three address translations. The virtual address-based addressing method described in this application, as reflected in the AVA, carries the destination virtual address (DVA) instead of the destination physical address (DPA). Furthermore, this application does not limit the specific implementation of the first, second, and third mapping tables, as long as they achieve their corresponding functions. The examples in this application are for illustrative purposes only and do not constitute a limitation.

[0156] In one implementation, the process of the source end accessing the memory of the destination end via the bus address is as follows: Figure 2 As shown. In simple terms, the source CPU initiates a memory access request, carrying the SVA (Server Entity Address). The source MMU performs address translation based on the SVA, checking if the physical address corresponding to the SVA is a TPA (TPA), i.e., whether it belongs to the physical address space of the source bus-side device. If it is not a TPA, the request is sent to the local memory controller, allowing access to local memory; if it is a TPA, the request is sent to the source bus-side device for processing. The source bus-side device sends the address-translated memory access request (carrying the AVA) to the high-performance interconnect bus. The high-performance interconnect bus, based on the bus-side device identifier carried in the received memory access request, transmits it to the destination bus-side device. The destination bus-side device parses the received memory access request, finds the corresponding page table base address based on the instance identifier in the DVA (Device Entity Address Address) of the AVA, and sends this page table base address to the destination IOMMU. Based on the page table base address and the VA in the memory access request, IOMMU finds the corresponding DPA. The local memory controller at the destination can then access the destination's memory based on this DPA to read data or write the data carried in the memory access request to the address indicated by the DPA. It should be understood that both the "yes" and "no" branches in the diagram ultimately point to the local memory controller, but in the "yes" branch, "local" refers to the destination, and in the "no" branch, "local" refers to the source.

[0157] The address translation process described above enables cross-node memory access. The destination's memory can be accessed by the source via a high-performance interconnect bus. This allows for the use of single-node memory access instructions even in cross-node scenarios, unifying cross-node and single-node access scenarios, improving memory access speed in cross-node scenarios, and reducing read / write latency. Furthermore, because the request carries a virtual address rather than a physical address, the destination's memory can not only be accessed through address translation, allowing the request from the source to reach the actual physical address to be read or written after a series of processing steps, but the destination's operating system also retains control over this memory. In addition, nodes other than the source and destination can also read and write this memory, achieving true memory sharing—a single memory segment can be accessed by multiple nodes.

[0158] The following is combined with Figure 3 Taking memory access as an example, this application briefly describes how shared memory within a domain is managed through controllers and agents. Figure 3 In this context, physical memory 3011 refers to the destination memory, while virtual memory 3005 is merely an illustration. A domain is a group of nodes that can access each other's memory using the scheme described in this application. Specifically, this management process can be described using two logical concepts: memory region (MR) and memory segment (MS). These concepts are logical, meaning they are created for ease of textual and code description, but the actual forms of their corresponding entities may not necessarily conform to the descriptions below.

[0159] MR3104: This is a logical or code-level concept representing a contiguous virtual address space composed of multiple MSs (e.g., 3101-3103 in the diagram). MR creation can be initiated by any process on a node within a domain; that is, processes on both the source and destination ends can initiate it. An MR can be a segment (including multiple virtual addresses) within the virtual address space of the process that initiated its creation, or it can be from other address spaces within the operating system. The controller maintains a directory of MRs, including, for example, the starting addresses and lengths of multiple MRs. The MR directory records multiple MRs within the domain where the controller resides, allowing the controller to manage MRs within that domain uniformly.

[0160] MS (e.g., 3101-3103 in the diagram): Belongs to a MR (Memory Registry). Within an MR's address space, an MS is identified by its offset and length. The offset is the distance from the starting address of the MR, and the length is the size of the MS, i.e., the size of a memory segment. Each MS is created by a process and corresponds to a physical memory segment with a length equal to that MS. The DVA (Device Variable Access) or VA within DVA described earlier is related to the MS's offset.

[0161] Based on the memory model described above, a process at the destination end (3008 in the figure) can share its own physical memory (3011 in the figure), allowing a process at the source end (3002 in the figure) to read and write to it, thus implementing the multi-segment address translation process described earlier. The fragmented virtual addresses shared by the destination process, i.e., MS, can be managed in the form of contiguous addresses, i.e., MR, making management and use more convenient and concise. The three semantics described below can realize the creation of MR, the creation of MS, and the mapping of MS, containing three independent semantics. These can all be understood as an implementation required to realize the multi-segment address translation process described earlier.

[0162] Semantic 1: Create MR (can be used on either the source or destination to create an MR)

[0163] The implementation of semantic one includes the following steps:

[0164] a) The process (3002 in the figure) sends a request to the local agent (3003 in the figure) to create an MR (3104 in the figure).

[0165] b) The agent (3003 in the figure) passes the request to the controller (3001 in the figure).

[0166] c) The controller (3001 in the figure) approves or rejects the request and returns the result to the agent (3003 in the figure).

[0167] d) The agent (3003 in the figure) returns the result to the process (3002 in the figure). If the controller approves the request, the MR is created successfully.

[0168] Semantic 2: Create MS (The destination is used to create an MS, which belongs to the previously created MR, taking the process identifier, i.e., ASID, in AVA as an example)

[0169] The implementation of semantic 2 includes the following steps:

[0170] a) The process at the destination (3008 in the figure) takes a segment of virtual address, which is indicated by DVA and length, and allocates a segment of physical address corresponding to the segment of virtual address in the memory of the destination (3011 in the figure).

[0171] b) The process at the destination end (3008 in the figure) sends a request to the agent at the destination end (3007 in the figure) to create memory segment m (3102 in the figure), and attaches the identifier of MR (3104 in the figure) and the information of the aforementioned virtual address segment, namely DVA and length, in the request.

[0172] c) The destination agent (3007 in the figure) passes the request to the controller (3001 in the figure).

[0173] d) The controller (3001 in the figure) approves or rejects the request and returns the result to the agent at the destination (3007 in the figure).

[0174] e) If the controller approves, the destination agent (3007 in the figure) notifies the destination EP driver (3009 in the figure) to add the corresponding entry in the mapping table between ASID and page table base address, such as the third mapping table mentioned above; if the reported DVA is not the virtual address of the process (3008 in the figure), but a user-defined virtual address, then the agent (3007 in the figure) notifies the EP driver (3009 in the figure) to add the corresponding entry in the page table of the destination EP (3010 in the figure), that is, the second mapping table mentioned above. This entry indicates the mapping relationship between DVA and DPA.

[0175] f) The destination agent (3007 in the figure) returns the completed addition result to the destination process that initiated the request (3008 in the figure).

[0176] Semantic 3: Mapping MS

[0177] Mapping the MS (MS) refers to notifying the source process of the MS information registered by the destination process, enabling the source process to map this information to a segment of physical addresses in its physical address space. This allows the source process to access the physical address segment of the destination process corresponding to the MS. The physical address space of this process belongs to the bus-side device, not to memory. Therefore, Figure 3The source process (3002 in the diagram) is mapped to virtual memory 3005 in the hardware (represented by a dashed line) simply for visual symmetry with the destination process. It also serves to illustrate that the physical address space corresponding to the source process 3002 is not located in the source's physical memory.

[0178] The implementation of Semantic 3 includes the following steps:

[0179] a) The source process (3002 in the figure) allocates a virtual address space within its own virtual address space, identified by the SVA and length. This virtual address also corresponds to a physical address space in the destination's physical memory (3011 in the figure). The correspondence between the two can be represented by the address translation process from SVA to DPA described earlier.

[0180] b) The source process (3002 in the figure) initiates a request to the source agent (3003 in the figure) to map the memory segment m in MS (3102 in the figure). This request is to map the virtual address segment allocated in step a) to memory segment m (i.e. 3102 in the figure).

[0181] c) The agent at the source end (3003 in the figure) passes the request to the controller (3001 in the figure).

[0182] d) The controller (3001 in the figure) approves or rejects the request and returns the result to the agent on the source side (3003 in the figure).

[0183] e) If approved, the agent on the source side (3003 in the figure) notifies the EP driver on the source side (3004 in the figure) to configure the mapping table on the source side (i.e. the table used for the two address translations SVA->TPA and TPA->AVA), and sends the configuration result to the process in step b) where the source side initiates the process of mapping memory segment m in MS (3002 in the figure).

[0184] Specifically, the process for configuring the source-side tables is as follows:

[0185] 1. The source-side EP driver (3004 in the figure) fills the physical address (i.e., TPA) corresponding to a segment of length in the physical address space of the bus-side device into the page table entry of the corresponding source-side process (3002 in the figure).

[0186] 2. The source EP driver (3004 in the figure) updates the TPA->AVA table (that is, the first mapping table mentioned above) and fills in the corresponding table entries.

[0187] In this way, the destination process (3008 in the figure) shares the memory (3011 in the figure) by creating a memory storage object (MS in the figure) (3102 in the figure); the source process (3002 in the figure) enables access to the remote memory (3011 in the figure) by mapping the MS (3102 in the figure). The MS (3102 in the figure) can be mapped by processes of multiple nodes at the same time, so that the physical memory (3011 in the figure) can be accessed by multiple nodes at the same time, achieving true memory sharing.

[0188] The following is combined with Figure 4 This document describes one embodiment of a method for processing requests according to this application. This embodiment includes a process A 4002 in a first node accessing physical memory 4108 provided by a process B 4007 in a second node via a high-performance interconnect bus 4105, using memory semantics. In this access process, the first node can be referred to as the source, and the second node as the destination. This embodiment also uses communication between the first and second nodes as an example; other nodes may also communicate with the first or second node through a process similar to that described below. The first and second nodes belong to the same domain, which may also include several other nodes. Within this domain, each bus-end device has a unique EPID identifier. For brevity, this embodiment provides a brief description of the overall execution process of the method; for detailed explanations of the terms and sub-procedures involved, please refer to the corresponding content above.

[0189] Before process A4002 sends a read or write request, the shared memory needs to be registered by software, which means configuring the relevant mapping table. This embodiment uses the configuration of process A 4002 and process B 4007 as an example to illustrate a process of configuring the relevant mapping table (corresponding to DVA, including ASID and VA). This process is also applicable to other instances involving this process. It should be understood that during the configuration process before implementing cross-node memory access, neither of these processes nor their respective nodes have source or destination identities. This initialization process may include:

[0190] 1. Initialize process B4007.

[0191] a) Agent B4005 assigns a unique identifier within the second node to process B4007, namely the ASID of process B.

[0192] b) Agent B4005 notifies driver B4006 of the bus-side device to add the corresponding entry to the mapping table of ASID and page table base address (e.g., the third mapping table mentioned above). In this embodiment, the page table base address corresponding to ASID is the process page table base address of process B4007.

[0193] 2. Using semantic one, process B4007 completes the creation of memory region 4205.

[0194] 3. Process B4007 creates a memory segment based on memory region 4205 using semantic 2, specifically memory segment 34203.

[0195] 4. Using semantics 3, complete the process of mapping memory segment 34203 for process A4002. This process involves virtual memory 4102 (represented by a dashed box) in the diagram.

[0196] The above process requires the use of controller 4001, agent A 4003, and agent B 4005. Please refer to the preceding descriptions of the three semantics for details. Figure 3 and Figure 4 This will be understood in more detail here. Furthermore, through semantic two, processes on other nodes in this cluster, or other processes on the second node, can also create other memory segments belonging to memory region 4205, such as memory segment 1 4201 or memory segment n 4204.

[0197] After the above configuration, the process running on CPU 4101 of the first node can use the configured table entries to access the address segment in the physical memory 4108 of the second node. The following explanation uses an example where the bus address AVA consists of the bus-end device identifier EPID, the process's address space identifier ASID, and the virtual address VA within the process's virtual space, and the request is for reading data. Figure 4 In the diagram, the hardware section uses arrows to indicate the request processing flow. The request is issued by the central processing unit 4101 and continues until the corresponding read instruction reaches the physical memory 4108 and the corresponding data is read. This access process includes:

[0198] 1. In the central processing unit A4101 of the first node, process A4002 generates a read request (e.g., the first request mentioned above) and sends it to the memory management unit 4103. This read request includes an address in the virtual address space of process A4002, i.e., SVA.

[0199] 2. The memory management unit 4103 of the first node converts the SVA into the corresponding physical address, i.e., TPA, according to the process page table of process A4002.

[0200] 3. The bus-side device 4104 of the first node converts the TPA into the corresponding AVA according to the mapping relationship between TPA and AVA. For example, this mapping relationship is carried in the first mapping table described above.

[0201] 4. The bus-side device 4104 of the first node sends a request including the AVA (such as the second request mentioned above) to the high-performance interconnect bus 4105.

[0202] 5. The high-performance interconnect bus 4105 sends the request containing the AVA to the bus end device 4106 of the second node based on the bus end device identifier EPD in the AVA (the EPD in the second request indicates the bus end device 4106 of the second node).

[0203] 6. Bus-side device 4106 receives the request and parses the ASID from AVA (this ASID corresponds to process B 4007). Based on the correspondence between ASID and process page table base address, it obtains the process page table base address of process B 4007. Specifically, the correspondence between ASID and process page table base address is carried in a mapping table, such as the third mapping table mentioned above. This mapping table can also be a page table.

[0204] 7. Bus-side device 4106 sends the requested read instruction and the obtained process page table base address of process B 4007 to input / output memory management unit 4107.

[0205] 8. The input / output memory management unit 4107 obtains the physical address corresponding to the virtual address VA based on the process page table base address of process B 4007 and the virtual address VA in AVA, and accesses the physical memory 4108 based on the physical address and the read instruction to read the data indicated by the request sent by the first node.

[0206] 9. After the second node reads the corresponding data, the bus-side device 4106 sends the data to the first node through the bus (specifically, the high-performance interconnect bus 4105).

[0207] The above process completes cross-node memory access. The memory of the second node can be accessed by the first node via the bus. In cross-node scenarios, instructions for accessing memory within a single node can also be used. This process unifies the scenarios of cross-node and single-node access, improving the speed of memory access in cross-node scenarios and reducing latency for reading and writing data. On the other hand, because read and write requests carry virtual addresses rather than physical addresses, the memory of the second node can not only be accessed through address translation, allowing read and write requests issued by processes on the first node to reach the physical address to be read or written in the memory of the second node after a series of processing, but the operating system of the second node also does not lose management rights over this memory. In other words, when the first node can read and write this memory, process B 4007 in the second node can also read and write this memory. In addition, nodes other than the first and second nodes can also read and write this memory at this time, realizing true memory sharing.

[0208] The following describes, from a system perspective, how a request to read or write data, generated by the processor, is processed by multiple devices in the system to ultimately obtain the result. Explanations of various terms and phrases given earlier also apply below and will not be repeated. Figure 5a and Figure 5b These are schematic diagrams of two system architectures. This system is used to process requests. Figure 5a and Figure 5b The illustrated system includes a first processor 5001, a memory management unit 5002, a first bus-side device 5003, a second processor 5004, a storage medium 5005, and a second bus-side device 5006. The second processor runs an instance 5007, and the physical address space of instance 5007 points to the storage medium 5005. Of course, Figure 5a and Figure 5b The systems described are two illustrative examples, while in reality, Figure 5a and Figure 5b The various devices in the application can be independent devices as shown in the figure, or two or more devices can be integrated together. This application does not limit the specific implementation and layout of each device. For example, the second bus terminal device 5006 and the input / output memory management unit 5008 can be packaged in one device. As another example, the first processor 5001, the memory management unit 5002, and the first bus terminal device 5003 can be integrated on a single chip.

[0209] The first processor 5001 and the second processor 5004 may be composed of one or more processing units. The first processor 5001 may be a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits for performing the functions of the first processor 5001 in the embodiments of this application. This application does not impose any limitations. The second processor 5004 may also be a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits for performing the functions of the second processor 5004 in the embodiments of this application. This application does not impose any limitations.

[0210] The first bus terminal device 5003 and the second bus terminal device 5006 are used to communicate with other bus terminal devices. In this embodiment, the first bus terminal device 5003 and the second bus terminal device 5006 can be modules, circuits, interfaces, or other devices capable of implementing communication functions. Optionally, a bus terminal device may include an independently configured transmitter for transmitting information on a high-performance interconnect bus and an independently configured receiver for receiving information from the high-performance interconnect bus. A bus terminal device may also be a component that integrates the functions of transmitting and receiving information, and may even include simple processing and storage resources to support the use of mapping tables. This embodiment does not limit the specific implementation of the bus terminal device.

[0211] Storage medium 5005 can be classified as a read-only memory (ROM) or other type of storage module capable of storing static information and instructions, or random access memory (RAM) or other type of storage module capable of dynamically storing information and instructions, or electrically erasable programmable read-only memory (EEPROM) or other magnetic storage devices. The device containing storage medium 5005 can exist independently and be connected to the aforementioned second processor 5004 via an internal bus, specifically a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. Storage medium 5005 can also be integrated with the aforementioned second processor 5004.

[0212] It should be noted that when an instance's physical address space points to a storage medium, it means that the physical address space that the instance can use belongs to that storage medium, or in other words, the physical storage resources that the instance can use are a part of that storage medium.

[0213] The memory management unit 5002 is used to obtain a physical address corresponding to a first virtual address based on a first request from the first processor 5001. The first request is used to request to read data or to request to write data, and the first request includes the first virtual address. The first bus terminal device 5003 is used to send a second request to the second bus terminal device 5006 based on a first mapping relationship. The first mapping relationship is a mapping relationship between the physical address and the bus address. The second request corresponds to the first request and includes the bus address, which indicates the virtual address corresponding to the instance 5007. The second bus terminal device 5006 is used to receive the second request. The second bus terminal device 5006 is also used to process the second request based on the bus address and the second mapping relationship to obtain a result corresponding to the request. The second mapping relationship is a mapping relationship between the bus address and the physical address corresponding to the second request. The physical address corresponding to the second request belongs to the physical address space of the instance 5007.

[0214] The connection relationships between the various devices can be seen from the request processing procedure described in the previous section. Figure 5a The diagram schematically illustrates the processing direction of the request (from 5001 to 5007). This system does not limit the combination of the aforementioned devices. For example, in one implementation, the aforementioned devices (5001-5006) can be considered to be packaged in the same physical machine, with the first processor 5001 and the second processor 5004 running different operating systems. The first processor 5001 and the second processor 5004 can be different types of processors. In another implementation, the first processor 5001, the memory management unit 5002, and the first bus terminal device 5003 are located in one physical machine, while the second processor 5004, the storage medium 5005, and the second bus terminal device 5006 are located in another physical machine. The first bus terminal device 5003 and the second bus terminal device 5006 are connected via a bus.

[0215] In this way, the storage medium 5005 used by the second processor 5004 can be accessed by the first processor 5001, and the operating system's memory access instructions can be used, resulting in lower latency for reading and writing data. On the other hand, because the request carries a virtual address rather than a physical address, address translation allows the request issued by the first processor 5001 to access the physical address in the storage medium 5005 used by the second processor 5004 after a series of processing steps. Furthermore, the second processor 5004 does not lose its management and usage rights over this physical address. In other words, when the first processor 5001 can access a certain physical address in the storage medium 5005, the second processor 5004 can also read and write to that physical address. Even processors other than the first and second processors 5004 can read and write to this physical address, achieving true storage medium sharing.

[0216] The aforementioned physical address is the address in the physical address space corresponding to the first bus terminal device 5003.

[0217] In one implementation, the first processor 5001 is further configured to run a driver for the first bus-side device 5003, which is used to update the first mapping table containing the first mapping relationship.

[0218] The driver for the first bus-side device 5003 is used to obtain at least one bus address corresponding to the storage medium 5005; and based on the obtained at least one bus address corresponding to the storage medium 5005, to update the first mapping table, so that the updated first mapping table includes at least one entry corresponding to the at least one bus address corresponding to the storage medium 5005. The driver for the first bus-side device 5003 is also used to configure (including updating) the correspondence between a first virtual address and the physical address corresponding to the first virtual address. This correspondence can be stored in a mapping table, which can be a page table. Figure 5a In this context, the mapping table is indicated as Table 1. It can be seen that the memory management unit 5002 uses Table 1 to translate the first virtual address in the first request into the corresponding physical address.

[0219] In one implementation, the bus address includes the identifier of the second bus-side device 5006 and a second virtual address, which is related to instance 5007. The second mapping relationship is then the mapping relationship between the second virtual address and the physical address corresponding to the request. For example, this second virtual address is the custom DVA mentioned earlier, or the VA in the DVA described earlier, belonging to the virtual address space of instance 5007.

[0220] In one implementation, the second processor 5004 is further configured to run a driver for a second bus-side device 5006. The driver for the second bus-side device 5006 is configured to obtain an address allocation request from instance 5007, indicating that instance 5007 provides its corresponding physical address space. Based on the address allocation request, the mapping table containing the second mapping relationship is updated so that the updated mapping table includes at least one entry corresponding to the physical address space of instance 5007. It should be understood that instance 5007 can provide all or part of the physical address space.

[0221] Figure 5a This illustrates the case where the bus address (AVA mentioned earlier) consists of the identifier of the second bus terminal device 5006 and the second virtual address. In other words, the AVA consists of EPID and a virtual address, namely DVA. The DVA can be globally unique within the second node. Figure 5a This also illustrates the multiple address translation processes described earlier. For example,

[0222] Figure 5b This illustrates another implementation method, where the bus address also includes the identifier of instance 5007. Correspondingly, the second mapping relationship is... Figure 5a The corresponding implementation methods differ. The second mapping relationship includes the mapping between the identifier of instance 5007 and the page table base address of instance 5007, and the mapping between the second virtual address and the physical address corresponding to the request. The mapping between the second virtual address and the physical address corresponding to the second request is recorded in the page table of instance 5007. The page table of instance 5007 is in... Figure 5b The diagram is shown in Table 2.

[0223] Correspondingly, the address translation process in the second node is also similar to... Figure 5a Different from China. Figure 5b The illustrated system also includes an input / output memory management unit 5008, which is used to manage memory through the page table of this instance 5007. Figure 5b As illustrated in Table 2, the physical address corresponding to the second request is located to perform the operation corresponding to the second request, and the result of the operation (e.g., the data read, or feedback indicating successful data writing) is returned to the second bus-side device. Correspondingly, the second bus-side device 506, based on the bus address and the mapping between the identifier of instance 5007 and the page table base address of instance 5007, locates the page table of instance 5007 and passes the page table information (e.g., the page table base address) of instance 5007 to the input / output memory management unit 5008. Of course, the system can always include the input / output memory management unit 5008, thus being compatible with both implementations described above. Figure 5a and Figure 5bThis only illustrates two possible implementation methods. In practical applications, some implementation details may differ from those in the original text. Figure 5a and Figure 5b The illustrations may differ slightly, but this application does not impose any limitations. For example, Figure 5a The illustration shows that the second bus-side device 5006 uses a second mapping table to translate the second virtual address into the physical address corresponding to the second request. In actual implementation, the input / output memory management unit 5008 can use the second mapping table to translate the second virtual address into the physical address corresponding to the second request, while the second bus-side device 5006 is only used to receive the second request and read the second virtual address from the second request. For example... Figure 5b The illustration shows that the second bus-side device 5006 uses the third mapping table to find the page table base address corresponding to the instance identifier in the bus address of the second request. Then, it passes the page table base address and the second virtual address from the bus address to the input / output memory management unit 5008, which looks up Table 2 to obtain the corresponding physical address. In actual implementation, both address translations can be performed by the second bus-side device 5006, meaning the second bus-side device 5006 looks up both the third mapping table and Table 2, without needing to use the input / output memory management unit 5008. Alternatively, both address translations can be performed by the input / output memory management unit 5008. That is, the second bus-side device 5006 only receives the second request, reads the instance identifier and the second virtual address from it, and the input / output memory management unit 5008 looks up the page table base address based on the instance identifier in the third mapping table, then looks up Table 2 to obtain the physical address corresponding to the second request.

[0224] Figure 6 This is a schematic diagram of an architecture for an apparatus used to execute the aforementioned request processing method. Figure 6 Corresponding to the aforementioned source end, it can also be called Figure 6 The described device 600 is located at the aforementioned first node. The device 600 includes: a processing module 6001, configured to send a first request to an address translation module 6002, the first request being for requesting to read data from a second node, or requesting to write data to the second node; an address translation module 6002, configured to obtain a corresponding physical address based on a first virtual address, the first virtual address being the virtual address in the first request; and a bus communication module 6003, configured to send a second request to the second node based on a first mapping relationship, the first mapping relationship being a mapping relationship between the physical address and a bus address, the second request corresponding to the first request, the second request including the bus address, the bus address indicating the virtual address corresponding to an instance in the second node.

[0225] The aforementioned device 600 is used to execute the aforementioned processing request method, particularly the method executed at the source or at the first node. Therefore, the specific implementation, description, and technical effects can be referred to the corresponding paragraphs above, and will not be repeated here. The device 600 can be the first node or a part of the first node. This application does not limit the specific implementation of the various modules described above. For example, the modules can be integrated into one module. For another example, the processing module 6001 can be a processor or controller, such as a CPU, general-purpose processor, DSP, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0226] For example, the address translation module 6002 may be the memory management unit (MMU) described above.

[0227] For example, the bus communication module 6003 may be the bus end device described above, which is used to enable the device to connect to a high-performance interconnect bus and send and receive information.

[0228] Figure 7 This is a schematic diagram of an architecture for an apparatus used to execute the aforementioned request processing method. Figure 7 Corresponding to the aforementioned destination, it can also be called Figure 7 The described device 700 is located at the aforementioned second node. The device includes: a processing module 7001 and a storage medium 7002. The processing module 7001 is used to run an instance whose physical address space points to the storage medium 7002; and a bus communication module 7003, used to receive a request from the first node for reading or writing data. The request includes a bus address indicating the virtual address corresponding to the instance. The module is also used to process the second request based on the bus address and a second mapping relationship to obtain a result corresponding to the request. The second mapping relationship is a mapping between the bus address and the physical address corresponding to the request, where the physical address belongs to the physical address space of the instance.

[0229] It should be noted that when an instance's physical address space points to the storage medium, it means that the physical address space that the instance can use belongs to the storage medium, or in other words, the physical storage resources that the instance can use are a part of the storage medium.

[0230] The aforementioned device 700 is used to execute the aforementioned processing request method, particularly the method executed at the destination or on the second node. Therefore, the specific implementation, description, and technical effects can be referred to the corresponding paragraphs above, and will not be repeated here. This device can be a second node or a part of a second node. This application does not limit the specific implementation of the various modules described above; for example, the modules can be integrated into one module. Some specific implementations of processing module 7001 can be referred to the preceding description of processing module 6001.

[0231] For example, storage medium 7002 can be classified as memory or other types of storage.

[0232] For example, the bus communication module 7003 may be the bus end device described above, which is used to enable the device to connect to a high-performance interconnect bus and send and receive information.

[0233] Of course, in conjunction with the foregoing description, in some implementations, device 700 may also include an address translation module (not shown in the figure) for using the page table of the instance to translate virtual addresses into physical addresses. The address translation module may be the input / output memory management unit described above.

[0234] Figure 8 The diagram shown illustrates a possible logical structure of a device for processing requests according to an embodiment of this application. The device 800 includes: a storage medium 8001, a processing circuit 8002, a memory management unit 8003, and a bus terminal device 8004. The storage medium 8001 is coupled to the processing circuit 8002. The storage medium 8001 stores computer program code and data. The computer program code includes computer instructions. When the computer instructions are executed by the processing circuit 8002, the aforementioned methods can be performed together with the memory management unit 8003 and the bus terminal device 8004. The processing circuit 8002 controls and manages the operation of the computer device 800. The bus terminal device 8004 supports communication between the device 800 and other devices via a bus (e.g., a high-performance interconnect bus). Specifically, the memory management unit 8003 is used to obtain the corresponding physical address based on the first virtual address, which is the virtual address in the first request. The first request is used to request to read data from another device or to request to write data to the other device. The bus end device 8004 is used to send a second request to the other device based on a first mapping relationship, which is the mapping relationship between the physical address and the bus address. The second request corresponds to the first request and includes the bus address, which indicates the virtual address corresponding to the instance in the other device.

[0235] The processing circuit 8002 can be a central processing unit, graph processor, general-purpose processor, digital signal processor, application-specific integrated circuit, field-programmable gate array, or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processing circuit 8002 can also be a combination that implements computational functions, such as including one or more microprocessor combinations, digital signal processors and microprocessors, etc. The storage medium 8001 can be classified as read-only memory (ROM) or other types of storage modules capable of storing static information and instructions, or random access memory (RAM) or other types of storage modules capable of dynamically storing information and instructions, or electrically erasable programmable read-only memory (EEPROM) or other magnetic storage devices.

[0236] The storage medium 8001, the processing circuit 8002, and the bus terminal device 8004 can be connected via a bus. Figure 8 In the diagram, the memory management unit 8003 and the processing circuit 8002 are packaged together and electrically connected. The memory management unit 8003 is directly connected to the bus, and the processing circuit 8002 is connected through the memory management unit 8003. However, in actual devices, the memory management unit 8003 may be a separate device, or the processing circuit 8002 and the memory management unit 8003 may be packaged together, with the processing circuit 8002 directly connected to the bus. This application does not limit the layout of the various components in device 800. The bus here refers to the bus within the device, specifically a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, Figure 8 The symbol is represented by a single thick line, but this does not mean that there is only one bus or one type of bus in device 800.

[0237] Figure 8The corresponding device 800 can be the device where the aforementioned source end or first node is located, or the aforementioned source end or first node, used to execute the method executed by the aforementioned source end or first node. Therefore, the specific implementation, description, and technical effects can be referred to the corresponding paragraphs of the methods, devices, and systems above, and will not be repeated here. For example, in one implementation, the storage medium 8001 can be the memory 1006 mentioned above, the processing circuit 8002 can be the central processing unit 1004 mentioned above, the memory management unit 8003 corresponds to the memory management unit 1005, and the bus end device 8004 corresponds to the bus end device 1008.

[0238] Figure 9 The diagram shown illustrates a possible logical structure of a device for processing requests according to an embodiment of this application. The device 900 includes a storage medium 9001, a processing circuit 9002, and a bus-end device 9003. The storage medium 9001 is coupled to the processing circuit 9002. The storage medium 9001 stores computer program code, which includes computer instructions. When the computer instructions are executed by the processing circuit 9002, the bus-end device 9003 is instructed to perform the following methods: receiving a request from another device, the request being used to read data from that device or to write data to that device, the request including a bus address indicating a virtual address corresponding to an instance in that device; and obtaining the physical address corresponding to the request in the storage medium of the device based on the bus address and a second mapping relationship, to execute the operation indicated by the request. The second mapping relationship is the mapping relationship between the bus address and the physical address corresponding to the request.

[0239] For some specific implementation details of the processing circuit 9002, please refer to the previous description of the processing circuit 8002. The processing circuit 9002 is used to run instances, which can share one or more segments of physical memory available to them with other devices. For some specific implementation details of the storage medium 9001, please refer to the previous description of the storage medium 8001.

[0240] The storage medium 9001, processing circuitry 9002, and bus-side device 9003 can be connected via a bus. This bus is an internal device bus, specifically a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be categorized as an address bus, data bus, control bus, etc. For ease of representation, Figure 9 The symbol is represented by a single thick line, but this does not mean that there is only one bus or one type of bus in device 900.

[0241] Figure 9 The corresponding device 900 can be the device where the aforementioned destination or second node is located, or the aforementioned source or second node, used to execute the method executed by the aforementioned source or second node. Therefore, the specific implementation, description, and technical effects can be referred to the corresponding paragraphs of the methods, devices, and systems above, and will not be repeated here. For example, the storage medium 9001 can be the memory 1006 mentioned above, the processing circuit 9002 can be the central processing unit 1004 mentioned above, and the bus end device 9004 can be the bus end device 1008 described above. In addition, the device 900 can also include an input / output memory management unit. Specifically, the input / output memory management unit is the input / output memory management unit 1007 described above. In this way, when the bus address includes the instance identifier, the input / output memory management unit 1007 can be used to perform address lookup to find the requested physical address. Figure 9 This diagram illustrates the layout where the Input / Output Memory Management Unit (I / O Memory Management Unit) is connected to other devices (such as the processing circuit 9002) via a bus. In reality, the I / O Memory Management Unit may also be connected to... Figure 9 This application does not impose any restrictions on the encapsulation of certain components together and their electrical connection via circuitry.

[0242] As one embodiment, device 800 and / or device 900 may include multiple processors. Each of these processors may be a single-core processor or a multi-core processor. Here, "processor" may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions). Furthermore, the computer program code in this embodiment may also be simply referred to as a computer program or code, or other names, and the computer instructions may be simply referred to as instructions or commands; this embodiment does not specifically limit the terminology used in this application.

[0243] Furthermore, those skilled in the art will understand that device 800 may include, but is not limited to, components that are more complex or complex than those that are less complex or complex than those that are more ... Figure 8 The components shown are fewer or more components. Figure 8 Only components more relevant to the various implementations disclosed in the embodiments of the present invention are shown. Similarly, device 900 may also include more... Figure 9 The components shown are fewer or more components. Figure 9Only components more relevant to the various implementations disclosed in the embodiments of the present invention are shown. As one embodiment, device 800 and / or device 900 may further include output devices and input devices. The output device communicates with the aforementioned processing circuitry (such as processing circuitry 8002 or the processing circuitry itself) and can display information in various ways. For example, the output device may be a liquid crystal display (LCD), a light-emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device communicates with the processor and can receive user input in various ways. For example, the input device may be a mouse, keyboard, touchscreen device, or sensing device, etc. Additionally, Figure 8 and Figure 9 The high-performance interconnect bus, which is used for communication between devices and is accessed through bus-end devices, is not shown. It functions similarly to a wireless network.

[0244] It is understood that, in order to achieve the aforementioned functions, the above-described devices or apparatuses include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in a hardware-driven or software-driven manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0245] This application embodiment can divide the above-mentioned devices (such as 800 and 900) or apparatuses (such as 600 and 700) into functional modules according to the above method examples. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware or as software functional modules. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0246] This application also provides a chip system applied to the aforementioned device. The chip system includes one or more interface circuits and one or more processors. The interface circuits and the processors are interconnected via lines. The interface circuits are used to receive signals from the device's memory and send the signals to the processors. The signals include computer instructions stored in the memory. When the processor executes the computer instructions, the device executes any of the methods executed in the first node of the above method embodiments, or executes any of the methods executed in the second node of the above method embodiments.

[0247] This application also provides a computer storage medium including computer instructions that, when executed on a device, cause the device to perform any of the methods executed by the first node in the above method embodiments, or to perform any of the methods executed by the second node in the above method embodiments.

[0248] This application also provides a computer program product that, when run on a computer, causes a device to execute any of the methods executed by the first node in the above method embodiments, or to execute any of the methods executed by the second node in the above method embodiments.

[0249] The devices, chip systems, computer storage media, or computer program products provided in this application are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0250] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0251] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0252] The unit described as a separate component may or may not be physically separate. The component shown as a unit can be one physical unit or multiple physical units, that is, it can be located in one place or distributed in multiple different places. Some or all of the units can be selected to achieve the purpose of the solution in this embodiment, depending on actual needs.

[0253] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0254] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0255] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for processing requests, characterized in that, The method includes: The first node obtains the corresponding physical address based on the first virtual address, which is the virtual address in the first request. The first request is used to request to read data from the second node or to request to write data to the second node. The first node sends a second request to the second node based on a first mapping relationship, wherein the first mapping relationship is the mapping relationship between the physical address and the bus address, and the second request corresponds to the first request, and the second request includes the bus address; The bus address is composed of the bus end device identifier, instance identifier, and second virtual address of the second node; the instance identifier indicates the virtual address space corresponding to an instance in the second node, and the second virtual address is the address within the virtual address space of the instance indicated by the instance identifier; The first node sends a second request to the second node based on the first mapping relationship, including: The first node translates the physical address into the bus address according to the first mapping relationship; and sends the second request to the second node through the high-performance interconnect bus.

2. The method according to claim 1, characterized in that, The bus-side device in the first node is used to communicate with the second node using the first mapping relationship.

3. The method according to claim 2, characterized in that, The physical address is the address in the physical address space corresponding to the bus-side device of the first node.

4. The method according to any one of claims 1-3, characterized in that, The first node stores a first mapping table, which indicates multiple mapping relationships, including the first mapping relationship, wherein each of the multiple mapping relationships is a mapping between a physical address and a bus address.

5. The method according to claim 4, characterized in that, The method further includes: Obtain the address space in the second node, the address space indicating at least one bus address; Based on the obtained address space in the second node, the first mapping table is updated so that the updated first mapping table includes at least one entry corresponding to the at least one bus address indicated by the address space.

6. The method according to claim 5, characterized in that, The first mapping table is updated by the driver of the bus-side device.

7. A method for processing requests, characterized in that, The method is used for the second node, and the method includes: Receive a request from a first node, the request being used to read data from the second node or to write data to the second node, the request including a bus address; The bus address is composed of the identifier of the bus end device of the second node, the instance identifier, and the second virtual address; the instance identifier indicates the virtual address space corresponding to an instance in the second node, and the second virtual address is the address within the virtual address space of the instance indicated by the instance identifier; Based on the bus address and the second mapping relationship, the physical address in the storage medium of the second node corresponding to the request is obtained to execute the operation indicated by the request. The second mapping relationship is the mapping relationship between the bus address and the physical address corresponding to the request. The step of obtaining the physical address corresponding to the request in the storage medium of the second node based on the bus address and the second mapping relationship includes: Based on the instance identifier, determine the page table base address of the instance indicated by the instance identifier; and based on the page table base address and the second virtual address, translate to obtain the physical address in the second node where read and write operations are performed.

8. The method according to claim 7, characterized in that, The bus terminal device is used to process requests from the first node based on the second mapping relationship.

9. The method according to claim 8, characterized in that, The physical address corresponding to the request belongs to the physical address space of the instance.

10. The method according to any one of claims 7-9, characterized in that, The second mapping relationship includes the mapping between the instance's identifier and the instance's page table base address, and the mapping between the second virtual address and the physical address corresponding to the request. The mapping between the second virtual address and the physical address corresponding to the request is recorded in the instance's page table.

11. The method according to claim 10, characterized in that, The second node stores a third mapping table, which includes multiple entries. The mapping between the instance identifier and the page table base address of the instance is recorded in one of the multiple entries. Each of the multiple entries is used to record information about the instance in the second node, including the instance identifier and the page table base address of the instance.

12. The method according to claim 11, characterized in that, The third mapping table is updated by the driver of the bus-side device.

13. The method according to claim 11 or 12, characterized in that, The method further includes: Based on the information of the instance in the second node, the third mapping table is updated so that the updated third mapping table includes entries corresponding to the information, the information including the instance identifier and the instance's page table base address.

14. A system for processing requests, characterized in that, The system includes a first processor, a memory management unit (MMU), a first bus terminal device, a second processor, a storage medium, and a second bus terminal device. The second processor runs an instance, and the physical address space of the instance points to the storage medium. The MMU is used to obtain a physical address corresponding to a first virtual address based on a first request from the first processor. The first request is used to request to read data or to request to write data, and the first request includes the first virtual address. The first bus-side device is used to send a second request to the second bus-side device based on a first mapping relationship. The first mapping relationship is the mapping relationship between the physical address and the bus address. The second request corresponds to the first request and includes the bus address. The bus address is composed of the bus-side device identifier, the instance identifier, and the second virtual address of the second node. The instance identifier indicates the virtual address space corresponding to an instance in the second node, and the second virtual address is the address within the virtual address space of the instance indicated by the instance identifier. Specifically, the first bus terminal device is used to translate the physical address corresponding to the first virtual address into the bus address according to the first mapping relationship, and send the second request to the second bus terminal device through the high-performance interconnect bus; The second bus terminal device is used to receive the second request; The second bus terminal device is further configured to process the second request based on the bus address and the second mapping relationship to obtain the result corresponding to the request, wherein the second mapping relationship is the mapping relationship between the bus address and the physical address corresponding to the second request; Specifically, the second bus terminal device is used to determine the page table base address of the instance indicated by the instance identifier based on the instance identifier; and to translate the physical address in the second node that performs read and write operations based on the page table base address and the second virtual address.

15. The system according to claim 14, characterized in that, The physical address is the address in the physical address space corresponding to the first bus-side device.

16. The system according to claim 15, characterized in that, The first processor is also configured to run the driver of the first bus-side device, which is used to update the first mapping table containing the first mapping relationship.

17. The system according to claim 16, characterized in that, The driver of the first bus terminal device is used to obtain at least one bus address corresponding to the storage medium; and based on the obtained at least one bus address corresponding to the storage medium, update the first mapping table so that the updated first mapping table includes at least one entry corresponding to at least one bus address corresponding to the storage medium.

18. The system according to any one of claims 14-17, characterized in that, The second processor is also configured to run the driver of the second bus-side device, the driver of the second bus-side device being configured to obtain the address allocation request of the instance, the address allocation request indicating that the instance provides the physical address space corresponding to the instance; Based on the address allocation request, the mapping table containing the second mapping relationship is updated so that the updated mapping table containing the second mapping relationship includes at least one entry corresponding to the physical address space corresponding to the instance.

19. The system according to any one of claims 14-17, characterized in that, The second mapping relationship includes the mapping between the instance identifier and the page table base address of the instance, and the mapping between the second virtual address and the physical address corresponding to the second request. The mapping between the second virtual address and the physical address corresponding to the second request is recorded in the page table of the instance.

20. The system according to claim 19, characterized in that, The system further includes an Input / Output Memory Management Unit (IOMMU). The IOMMU is used to find the physical address corresponding to the second request through the page table of the instance, to perform the operation corresponding to the second request, and to return the result of the operation to the second bus-side device. Correspondingly, the second bus-side device is used to find the page table base address of the instance based on the bus address and the mapping between the instance's identifier and the instance's page table base address, and to pass the instance's page table base address to the IOMMU.

21. An apparatus for processing requests, the apparatus being located at a first node, characterized in that, The device includes: The processing module is used to send a first request to the address translation module, the first request being used to request to read data from the second node, or to request to write data to the second node; The address translation module is used to obtain the corresponding physical address based on the first virtual address, where the first virtual address is the virtual address in the first request. A bus communication module is used to send a second request to the second node based on a first mapping relationship, wherein the first mapping relationship is a mapping relationship between the physical address and the bus address, the second request corresponds to the first request, and the second request includes the bus address; wherein the bus address is composed of the bus end device identifier, instance identifier, and second virtual address of the second node; the instance identifier indicates the virtual address space corresponding to an instance in the second node, and the second virtual address is an address within the virtual address space of the instance indicated by the instance identifier; The bus communication module is specifically used to translate the physical address into the bus address according to the first mapping relationship; and to send the second request to the second node through the high-performance interconnect bus.

22. The apparatus according to claim 21, characterized in that, The physical address is the address in the physical address space corresponding to the bus communication module.

23. The apparatus according to claim 22, characterized in that, The bus communication module is used to use a first mapping table, which indicates multiple mapping relationships including the first mapping relationship, wherein each of the multiple mapping relationships is a mapping between a physical address and a bus address.

24. The apparatus according to any one of claims 21-23, characterized in that, The driver module also runs a driver for the bus communication module, which is used to obtain the address space in the second node, the address space indicating at least one bus address; and based on the obtained address space in the second node, update the first mapping table so that the updated first mapping table includes at least one entry corresponding to the at least one bus address indicated by the address space.

25. An apparatus for processing requests, the apparatus being located at a second node, characterized in that, The device includes: A processing module and a storage medium, wherein the processing module is used to run an instance, and the physical address space of the instance points to the storage medium; A bus communication module is used to receive a request from a first node, the request being used to read data or write data, the request including a bus address, wherein the bus address is composed of the identifier of the bus end device of the second node, an instance identifier, and a second virtual address; the instance identifier indicates the virtual address space corresponding to an instance in the second node, and the second virtual address is an address within the virtual address space of the instance indicated by the instance identifier; The bus communication module is further configured to process a second request based on the bus address and a second mapping relationship to obtain a result corresponding to the request. The second mapping relationship is a mapping relationship between the bus address and the physical address corresponding to the request, and the physical address corresponding to the request belongs to the physical address space of the instance. Specifically, the bus communication module is used to determine the page table base address of the instance indicated by the instance identifier based on the instance identifier; and to translate the physical address of the second node that performs read and write operations based on the page table base address and the second virtual address.

26. The apparatus according to claim 25, characterized in that, The processing module is also used to run the driver of the bus communication module, the driver of the bus communication module is used to obtain the address allocation request of the instance, the address allocation request indicating that the instance provides the physical address space corresponding to the instance; Based on the address allocation request, the mapping table containing the second mapping relationship is updated so that the updated mapping table containing the second mapping relationship includes at least one entry corresponding to the physical address space corresponding to the instance.

27. The apparatus according to claim 25 or 26, characterized in that, The second mapping relationship includes the mapping between the instance's identifier and the instance's page table base address, and the mapping between the second virtual address and the physical address corresponding to the request. The mapping between the second virtual address and the physical address corresponding to the request is recorded in the instance's page table.

28. The apparatus according to claim 27, characterized in that, The device further includes an address translation module, which is used to find the physical address corresponding to the request through the page table of the instance, to perform the operation corresponding to the second request, and to return the result of the operation to the bus communication module; Accordingly, in processing the second request based on the bus address and the second mapping relationship to obtain the result corresponding to the request, the bus communication module is used to find the page table base address of the instance based on the identifier of the instance in the bus address and the mapping between the identifier of the instance and the page table base address of the instance, and to pass the page table base address of the instance to the input / output memory management unit (IOMMU).

29. A chip, characterized in that, The chip includes a processing circuit and an interface circuit, the interface circuit being interconnected with the processing circuit via a line, the interface circuit being used to receive signals from a storage medium and send the signals to a processor, the signals including computer instructions stored in the storage medium; when the computer instructions are executed by the processing circuit, the chip performs the method of the processing request as described in any one of claims 1-6.

30. A chip, characterized in that, The chip includes a processing circuit and an interface circuit, the interface circuit being interconnected with the processing circuit via a line, the interface circuit being used to receive signals from a storage medium and send the signals to a processor, the signals including computer instructions stored in the storage medium; when the computer instructions are executed by the processing circuit, the chip is used to perform the method of the processing request as described in any one of claims 7-13.

31. An apparatus for processing requests, characterized in that, The device includes: a storage medium, a processing circuit, a memory management unit (MMU), and a bus terminal device. The storage medium is coupled to the processing circuit and is used to store computer program code. The computer program code includes computer instructions. When the computer instructions are executed by the processing circuit, the following method is performed: The memory management unit (MMU) obtains the corresponding physical address based on the first virtual address, which is the virtual address in the first request. The first request is used to request to read data from another device or to request to write data to the other device. The bus-side device sends a second request to the other device based on a first mapping relationship, where the first mapping relationship is the mapping relationship between the physical address and the bus address. The second request corresponds to the first request and includes the bus address. The bus address consists of the bus-side device identifier, the instance identifier, and the second virtual address of the other device. The instance identifier indicates the virtual address space corresponding to an instance in the other device, and the second virtual address is the address within the virtual address space of the instance indicated by the instance identifier. Specifically, the bus-side device translates the physical address into the bus address according to the first mapping relationship; and sends the second request to the other device through the high-performance interconnect bus.

32. An apparatus for processing requests, characterized in that, The device includes: a storage medium, a processing circuit, and a bus terminal device. The storage medium is coupled to the processing circuit and is used to store computer program code. The computer program code includes computer instructions, which, when executed by the processing circuit, instruct the bus terminal device to perform the following method: A request is received from another device, the request being used to read data from the device or to write data to the device, the request including a bus address; the bus address is composed of an identifier of the bus-end device, an instance identifier, and a second virtual address; the instance identifier indicates the virtual address space corresponding to an instance in the device, and the second virtual address is an address within the virtual address space of the instance indicated by the instance identifier; Based on the bus address and the second mapping relationship, the physical address in the storage medium of the device corresponding to the request is obtained to execute the operation indicated by the request. The second mapping relationship is the mapping relationship between the bus address and the physical address corresponding to the request. Based on the bus address and the second mapping relationship, the physical address corresponding to the request in the storage medium of the device is obtained, including: Based on the instance identifier, determine the page table base address of the instance indicated by the instance identifier; and based on the page table base address and the second virtual address, translate to obtain the physical address in the storage medium for which read and write operations are performed.

33. A computer storage medium, characterized in that, Includes computer instructions that, when executed on a computer, cause the computer to perform the method for processing a request as described in any one of claims 1-6.

34. A computer storage medium, characterized in that, Includes computer instructions that, when executed on a computer, cause the computer to perform the method for processing a request as described in any one of claims 7-13.

35. A computer program product, characterized in that, Includes a computer program, which, when executed by one or more processors, is used to implement the method as described in any one of claims 1-6.

36. A computer program product, characterized in that, Includes a computer program, which, when executed by one or more processors, is used to implement the method as described in any one of claims 7-13.

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