Integrated circuit control method and integrated circuit
Patent Information
- Application Number
- CN202211643839.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-20
- Publication Date
- 2026-10-09
- Estimated Expiration
- 2042-12-20
Smart Images
Figure CN116010325B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to an integrated circuit control method and an integrated circuit. Background Technology
[0002] In non-automotive-grade battery management systems (BMS), the bidirectional two-wire synchronous serial bus (I2C bus) is a common solution for communication between the microcontroller unit (MCU) and the analog front-end (AFE). However, the harsh operating environment of BMS systems, such as the noise and interference from motor starting and stopping, makes ensuring the reliability of I2C communication crucial. Furthermore, a trade-off exists between the power consumption of the battery management system itself and the reliability of I2C communication, which has become a pressing issue requiring a solution. Summary of the Invention
[0003] This application provides an integrated circuit control method and an integrated circuit.
[0004] The integrated circuit control method of this application includes:
[0005] Obtain the read / write error rate of a bidirectional two-wire synchronous serial bus;
[0006] The read / write error rate is compared with a preset threshold, and a control strategy is determined based on the comparison result to optimize the operation of the integrated circuit.
[0007] Thus, this application determines the current operating status of the I2C bus based on the error rate during the read and write processes at both ends of the I2C bus connection in the integrated circuit, and decides on further optimization strategies for the integrated circuit operation based on the operating status. This includes reducing the error rate when the read / write error rate is too high, or optimizing the power consumption of the integrated circuit when the read / write error rate meets certain conditions. Compared with the related technologies that simply repeatedly acquire and adjust data, this application can achieve a balance between read / write error rate and circuit power consumption based on certain conditions, improving the flexibility of integrated circuit control.
[0008] In some implementations, comparing the read / write error rate with a preset threshold and determining a control strategy based on the comparison result includes:
[0009] The read / write error rate of the bidirectional two-wire synchronous serial bus is obtained when the read / write error rate is greater than or equal to a preset lower threshold and less than or equal to a preset upper threshold.
[0010] Thus, this application provides a control strategy when the I2C read / write error rate is within the normal range.
[0011] In some implementations, comparing the read / write error rate with a preset threshold and determining a control strategy based on the comparison result further includes:
[0012] When the read / write error rate is less than a preset lower threshold,
[0013] Determine whether the first condition is met. The first condition is: the integrated circuit requires to increase the clock rate of the bidirectional two-wire synchronous serial bus, and the clock rate of the bidirectional two-wire synchronous serial bus is not set to the highest level according to the preset clock rate level bit.
[0014] Based on whether the first condition is met, the control strategy is determined to optimize the operation of the integrated circuit.
[0015] Thus, this application provides a control strategy when the read / write error rate is lower than expected.
[0016] In some implementations, determining the control strategy based on the fulfillment of the first condition includes:
[0017] If the first condition is met...
[0018] According to the preset clock rate level setting, the clock rate of the bidirectional two-wire synchronous serial bus is increased by one level;
[0019] Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
[0020] Thus, this application provides a control strategy for optimizing integrated circuits when the first condition is met.
[0021] In some implementations, determining the control strategy based on the fulfillment of the first condition further includes:
[0022] If the first condition is not met.
[0023] Determine whether the second condition is met. The second condition is: the integrated circuit requires a reduction in the voltage of the bidirectional two-wire synchronous serial bus, and the voltage of the bidirectional two-wire synchronous serial bus is not set to the lowest level according to the preset voltage level.
[0024] The control strategy is determined based on whether the second condition is met.
[0025] Thus, this application provides a control strategy for optimizing integrated circuits when the first condition is not met.
[0026] In some implementations, determining the control strategy based on the fulfillment of the second condition includes:
[0027] If the second condition is met...
[0028] According to the preset voltage level setting, the voltage of the bidirectional two-wire synchronous serial bus is reduced by one level;
[0029] Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
[0030] Thus, this application provides a control strategy for optimizing integrated circuits when the second condition is met.
[0031] In some implementations, determining the control strategy based on the fulfillment of the second condition includes:
[0032] If the second condition is not met.
[0033] Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
[0034] Thus, this application provides a control strategy for optimizing integrated circuits when the second condition is not met.
[0035] In some implementations, comparing the read / write error rate with a preset threshold and determining a control strategy based on the comparison result includes:
[0036] When the read / write error rate exceeds a preset upper limit threshold,
[0037] Determine whether the third condition is met. The third condition is: the clock rate of the bidirectional two-wire synchronous serial bus is set to the lowest level according to the preset clock rate level.
[0038] Based on the fulfillment of the third condition, the control strategy is determined to reduce the read / write error rate of the bidirectional two-wire synchronous serial bus.
[0039] Thus, this application provides a control strategy when the read / write error rate is higher than expected.
[0040] In some implementations, determining the control strategy based on the fulfillment of the third condition includes:
[0041] If the third condition is not met,
[0042] According to the preset clock rate level setting, the clock rate of the bidirectional two-wire synchronous serial bus is reduced by one level.
[0043] Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
[0044] Thus, this application provides a control strategy for optimizing integrated circuits when the third condition is not met.
[0045] In some implementations, determining the control strategy based on the fulfillment of the third condition includes:
[0046] If the third condition is met,
[0047] Determine whether the fourth condition is met. The fourth condition is: the voltage of the bidirectional two-wire synchronous serial bus is set to the highest level according to the preset voltage level bit.
[0048] The control strategy is determined based on whether the fourth condition is met.
[0049] Thus, this application provides a control strategy for optimizing integrated circuits when the third condition is met.
[0050] In some implementations, determining the control strategy based on the fulfillment of the fourth condition includes:
[0051] If the fourth condition is not met,
[0052] According to the preset voltage level setting, the voltage of the bidirectional two-wire synchronous serial bus is increased by one level;
[0053] Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
[0054] Thus, this application provides a control strategy for optimizing integrated circuits when the fourth condition is not met.
[0055] In some implementations, determining the control strategy based on the fulfillment of the fourth condition includes:
[0056] If the fourth condition is met,
[0057] An adjustment failure report is sent to the controller in the integrated circuit, the adjustment failure report describing that the read / write error rate of the bidirectional two-wire synchronous serial bus cannot be adjusted;
[0058] Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
[0059] Thus, this application provides a control strategy for optimizing integrated circuits when the fourth condition is met.
[0060] This application also provides an integrated circuit, including a control module and an execution module, wherein the control module and the execution module are connected via a bidirectional two-wire synchronous serial bus, and the control module includes:
[0061] A controller for controlling the operation of the integrated circuit; and
[0062] An error counter is used to implement the integrated circuit control method described above.
[0063] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description
[0064] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:
[0065] Figure 1 This is a flowchart illustrating the integrated circuit control method provided in this application;
[0066] Figure 2 This is a schematic diagram of the integrated circuit structure provided in this application;
[0067] Figure 3 This is a flowchart illustrating the integrated circuit control method provided in this application;
[0068] Figure 4 This is a flowchart illustrating the integrated circuit control method provided in this application;
[0069] Figure 5 This is a flowchart illustrating the integrated circuit control method provided in this application;
[0070] Figure 6 This is a flowchart illustrating the integrated circuit control method provided in this application;
[0071] Figure 7 This is a flowchart illustrating the integrated circuit control method provided in this application;
[0072] Figure 8 This is a flowchart illustrating the integrated circuit control method provided in this application. Detailed Implementation
[0073] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.
[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.
[0075] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.
[0076] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0077] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0078] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).
[0079] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.
[0080] Currently, the common approach to address read / write errors in bidirectional two-wire synchronous serial buses (I2C) is to add a CRC checksum. If an error is found during a read / write operation, the operation is discarded, and the host side re-initiates the operation, performing the CRC check again until the result is correct. Throughout this process, the I2C bus voltage and clock rate remain constant. However, this simple, repetitive loop method for correcting read / write errors is inefficient. Furthermore, the I2C bus typically operates in harsh environments, where simple loops may fail to correct errors, leading to infinite loops and ultimately causing I2C to malfunction.
[0081] In response to the above problems, such as Figure 1 As shown, this application provides an integrated circuit control method, including:
[0082] 01: Obtain the read / write error rate of a bidirectional two-wire synchronous serial bus;
[0083] 02: Compare the read / write error rate with a preset threshold, and determine a control strategy based on the comparison result to optimize the operation of the integrated circuit.
[0084] like Figure 2 As shown, this application also provides an integrated circuit 10, including a control module 11 and an execution module 12, which are connected via a bidirectional two-wire synchronous serial bus. The control module 11 includes:
[0085] Controller 111 is used to control the operation of integrated circuit 10; and
[0086] Error counter 112 is used to obtain the read / write error rate of the bidirectional two-wire synchronous serial bus, and to compare the read / write error rate with a preset threshold. Based on the comparison result, a control strategy is determined to optimize the operation of integrated circuit 10.
[0087] Specifically, this application differs from related technologies in its approach to correcting read / write error rates. This application focuses on the read / write error rate of the I2C bus over a given period. Regarding the monitoring method for the read / write error rate, methods specific to the I2C bus in related technologies can be used, or other methods can be employed as needed; this application does not impose any limitations. In some examples, the component in the error statistician 112 used for line monitoring constantly monitors the operation of the I2C bus and obtains its read / write error rate. When the read / write error rate over a preset period is compared with a predetermined threshold or threshold range to establish a magnitude relationship or inclusion relationship, the operating state of the I2C bus at that time is determined, and different control strategies are adopted based on this operating state to optimize the operating state of the I2C and even the entire integrated circuit. The aforementioned optimization generally refers to reducing the I2C read / write error rate when it is too high, or appropriately reducing the operating power consumption of the integrated circuit when the read / write error rate is lower than expected.
[0088] In addition, such as Figure 2As shown, this application also provides an integrated circuit 10 capable of implementing the aforementioned integrated circuit control method. The integrated circuit 10 is divided into a control module 11 and an execution module 12, which are connected via an I2C bus. The control module 11 includes a controller 111 for controlling the operation of the integrated circuit, and the controller 111 acts as the I2C master in the I2C connection relationship. For example, a microcontroller chip (MCU) in a battery management system circuit can act as the controller 111. The control module 11 also includes an external power supply 113 for I2C and an error counter 112 for implementing the aforementioned integrated circuit control method. The execution module 12 includes an actuator 121 of the integrated circuit 10, and the actuator 121 acts as the I2C slave in the I2C connection relationship. For example, an analog front-end (AFE) in a battery management system circuit can act as the actuator 121.
[0089] Thus, compared with the solution in related technologies that simply acquires and adjusts data repeatedly, the solution provided in this application can achieve a balance between read / write error rate and circuit power consumption under certain conditions, thereby improving the flexibility of integrated circuit 10 control.
[0090] like Figure 3 As shown, in some embodiments, step 02 includes:
[0091] 021: Determine the relationship between the read / write error rate of the bidirectional two-wire synchronous serial bus and the preset threshold. If the read / write error rate is not less than the preset lower threshold and not greater than the preset upper threshold, return to step 01.
[0092] In some implementations, the error counter 112 is used to determine the relationship between the read / write error rate of the bidirectional two-wire synchronous serial bus and the preset upper limit threshold and the preset lower limit threshold. If the read / write error rate is not less than the preset lower limit threshold and not greater than the preset upper limit threshold, the process returns to step 01.
[0093] Specifically, to achieve a balance between read / write error rate correction and the power consumption of integrated circuit 10, the preset threshold for read / write error rate is divided into an upper threshold and a lower threshold. The upper threshold describes the maximum tolerable read / write error rate. When the I2C read / write error rate is higher than the upper threshold, it indicates that integrated circuit 10 needs to adjust the I2C operating state to reduce the current read / write error rate. The lower threshold describes the expected minimum read / write error rate and serves as a reference value. When the I2C read / write error rate is lower than the lower threshold, it means that the current operating state of integrated circuit 10 is better than expected. Given that integrated circuit 10 still has room for adjustment and adjustment needs, the operating state of I2C can be adjusted to reduce the current power consumption of integrated circuit 10 and further optimize the operating performance.
[0094] In some examples, the lower threshold is 10.-8 Represented by EL, with an upper limit threshold of 10. -7 Let EU represent the error rate. The component in error statistician 112 used for line monitoring observes the I2C operation and finds that within the 30 seconds prior to the current moment, the I2C read / write error rate η satisfies η∈[EL,EU], meaning the I2C read / write error rate is between the lower and upper thresholds. This indicates that the current operating state of integrated circuit 10 is normal and no adjustments are needed; maintaining the status quo is sufficient. At this time, the component in error statistician 112 used for line monitoring continues to monitor the I2C read / write error rate.
[0095] Thus, this application provides a control strategy when the I2C read / write error rate is within the normal range.
[0096] like Figure 3 As shown, in some embodiments, step 02 includes:
[0097] 021: Determine the relationship between the read / write error rate of the bidirectional two-wire synchronous serial bus and the preset threshold. If the read / write error rate is less than the preset lower threshold, proceed to step 022.
[0098] 022: Determine whether the first condition is met. The first condition is: Integrated circuit 10 requires increasing the clock rate of the bidirectional two-wire synchronous serial bus, and the clock rate of the bidirectional two-wire synchronous serial bus is not set to the highest level according to the preset clock rate level bit.
[0099] 023: Based on the fulfillment of the first condition, determine the control strategy to optimize the operation of integrated circuit 10.
[0100] In some examples, the error statistician 112 is used to determine the relationship between the read / write error rate of the bidirectional two-wire synchronous serial bus and a preset threshold, and to determine whether a first condition is met, and to determine the control strategy based on the meeting of the first condition, so as to optimize the operation of the integrated circuit 10.
[0101] Specifically, based on the above implementation method, the component in the error statistician 112 used for line monitoring monitors the operation of I2C. If the I2C read / write error rate is lower than a preset lower threshold for a period of time, it indicates that the current operating state of integrated circuit 10 and the current operating state of I2C are better than expected, and no adjustment is needed regarding the read / write error rate. Since the operating state of integrated circuit 10 is better than expected, the operating state of the circuit can be adjusted by adjusting specific operating parameters when there is a demand for integrated circuit 10, thereby optimizing the operation of integrated circuit 10. For I2C, parameters that can affect the read / write error rate and the operating state of integrated circuit 10 include clock rate and voltage. Generally, the two ends of I2C connect the I2C master and the I2C slave, and an external power supply is also required on the two lines of I2C. The aforementioned clock rate refers to the clock rate of the I2C master, and the aforementioned voltage is the voltage of the external power supply. Generally, the higher the clock rate or the lower the voltage, the higher the read / write error rate will be; conversely, the lower the clock rate or the higher the voltage, the lower the read / write error rate will be. During the process of adjusting the operating state to optimize the operation of integrated circuit 10, one of the clock rate and voltage can be adjusted, or both can be adjusted. For the sake of stable operation of integrated circuit 10, the clock rate can be evaluated and adjusted. If the operating state of integrated circuit 10 determines that the clock rate does not need adjustment or that the clock rate has reached its limit and cannot be adjusted, then the voltage is further evaluated and adjusted to achieve the purpose of optimized operation. Regarding the first condition mentioned above, this condition consists of two propositions, both of which must be true simultaneously for the first condition to be considered valid. The first proposition indicates that integrated circuit 10, based on its current operating state, determines whether there is a need to increase the clock rate, while the second proposition indicates whether the current clock rate has reached its limit. Only when integrated circuit 10, based on its current operating state, determines that there is a need to increase the clock rate and the clock rate has not reached its limit will the error counter 112 adjust the clock rate of the I2C host.
[0102] Based on the above parameter characteristics, in some examples, the component for line monitoring in the error counter 112 monitors the operation of the I2C and finds that within 30 seconds before the current moment, the read / write error rate η of I2C satisfies η<EL, that is, the read / write error rate of I2C is lower than the lower threshold, indicating that the current operating state of the integrated circuit 10 and the current operating state of I2C are better than expected, and no adjustment is required for the read / write error rate. Next, it is determined whether the operation of the integrated circuit 10 is optimized by adjusting the clock rate. According to the first condition, the error counter 112 acquires the current operating state of the integrated circuit 10 from the controller 111, determines the current requirement of the integrated circuit 10 for the clock rate of the I2C host, and simultaneously detects which level the current clock rate of the I2C host is at in the preset clock rate level setting. The preset clock rate level setting is a set of data settings for presetting and fixing the clock rate value of the I2C host in the integrated circuit 10. In some examples, the clock rate levels in the preset clock rate level setting are divided into six levels from low to high: 10kHz, 100kHz, 200kHz, 400kHz, 800kHz and 1MHz. The first condition is satisfied when the integrated circuit 10 currently needs to increase the clock rate of the I2C host and the current clock rate of the I2C host is not 1MHz, otherwise the first condition is not satisfied.
[0103] Thus, the present application provides a control strategy when the read / write error rate is lower than expected.
[0104] As Figure 4 shown, in some embodiments, step 02 includes:
[0105] 022: determine whether the first condition is satisfied, if yes, proceed to step 0231;
[0106] Based on the above, step 023 includes:
[0107] 0231: increase the clock rate of the two-wire bidirectional synchronous serial bus by one level according to the preset clock rate level setting, and return to step 01.
[0108] In some embodiments, the error counter 112 is configured to determine whether the first condition is satisfied, and increase the clock rate of the two-wire bidirectional synchronous serial bus by one level according to the preset clock rate level setting, and return to step 01.
[0109] Specifically, the adjustment method of integrated circuit 10 when the first condition is met will be explained below. According to the above implementation, the first condition is met when integrated circuit 10 needs to increase the clock rate of the I2C host, and the current clock rate of the I2C host is not 1MHz. In some examples, the error statistician 112 learns through data acquisition and processing that integrated circuit 10 needs to increase the clock rate of the I2C host, and the current clock rate of the I2C host is 400kHz, thus satisfying the first condition. At this time, the error statistician 112 increases the clock rate of the I2C host by one level to 800kHz, and then considers the adjustment process complete, returning to the state where the error statistician 112 monitors the read / write error rate. At this time, because the I2C clock rate is increased, the overall communication bandwidth of integrated circuit 10 is increased, that is, the information exchange capability inside integrated circuit 10 is increased. This also means that the read / write error rate will increase accordingly, so the read / write error rate is monitored again to achieve a balance between the read / write error rate and the communication bandwidth.
[0110] Thus, this application provides a control strategy for optimizing integrated circuit 10 when the first condition is met.
[0111] like Figure 4 As shown, in some embodiments, step 02 includes:
[0112] 022: Determine if the first condition is true. If not, proceed to step 0232.
[0113] Based on the above, step 023 includes:
[0114] 0232: Determine whether the second condition is met. The second condition is: Integrated circuit 10 requires a reduction in the voltage of the bidirectional two-wire synchronous serial bus, and the voltage of the bidirectional two-wire synchronous serial bus is not set to the lowest level according to the preset voltage level.
[0115] 0233: Determine the control strategy based on whether the second condition is met.
[0116] In some implementations, the error statistician 112 is used to determine whether a first condition is met, and to determine whether a second condition is met, and to determine a control strategy based on whether the second condition is met.
[0117] Specifically, the adjustment method of integrated circuit 10 when the first condition is not met will be explained next. According to the above implementation, the first condition is met when integrated circuit 10 needs to increase the clock rate of the I2C host and the current clock rate of the I2C host is not 1MHz. When one or both of the above two propositions are not met, the first condition is not met. When the first condition is not met, that is, when the clock rate is not adjusted, in order to reduce circuit power consumption, it is determined whether the I2C voltage needs to be adjusted, specifically by judging whether the second condition is met. Regarding the above second condition, this condition consists of two propositions, and both propositions must be met simultaneously for the second condition to be considered met. The first proposition indicates that integrated circuit 10 determines whether there is a need to reduce the voltage based on the current operating state, and the second proposition indicates whether the current voltage has reached its limit. Only when integrated circuit 10 determines that there is a need to reduce the voltage based on the current operating state and the voltage has not reached its limit will the error counter 112 adjust the voltage of the I2C host.
[0118] Based on the aforementioned parameter characteristics, in some examples, when the first condition is not met, i.e., when the clock rate of the I2C host is not adjusted, the next step is to determine whether to reduce the operating power consumption of integrated circuit 10 by adjusting the voltage. According to the second condition, the error statistician 112 obtains the current operating status of integrated circuit 10 from controller 111, determines the current voltage requirement of integrated circuit 10 for I2C, and simultaneously detects the current I2C voltage level in the preset voltage level setting. The preset voltage level setting is a set of data settings in integrated circuit 10 that pre-determines and fixes the I2C voltage value. In some examples, the preset voltage level setting has four levels from low to high: 1.8V, 2.5V, 3.3V, and 5V. The second condition is met when integrated circuit 10 needs to reduce the I2C voltage and the current I2C voltage is not 1.8V; otherwise, the second condition is not met.
[0119] Thus, this application provides a control strategy for optimizing integrated circuit 10 when the first condition is not met.
[0120] like Figure 5 As shown, in some embodiments, step 023 includes:
[0121] 0232: Determine if the second condition is true. If yes, proceed to step 02331.
[0122] Under the above conditions, step 0233 includes:
[0123] 02331: According to the preset voltage level setting, reduce the voltage of the bidirectional two-wire synchronous serial bus by one level and return to step 01.
[0124] In some implementations, the error counter 112 is used to determine whether the second condition is met, and to reduce the voltage of the bidirectional two-wire synchronous serial bus by one level according to the preset voltage level setting, and return to step 01.
[0125] Specifically, the adjustment method of integrated circuit 10 when the second condition is met will be explained below. According to the above implementation method, the second condition is met when integrated circuit 10 needs to reduce the I2C voltage and the current I2C voltage is not 1.8V. In some examples, the error statistician 112 learns from data acquisition and processing that integrated circuit 10 needs to reduce the I2C voltage and the current I2C voltage is 3.3V, thus satisfying the second condition. At this time, the error statistician 112 controls the external power supply to lower the I2C voltage by one level to 2.5V, and then considers the adjustment process complete, returning to the state where the error statistician 112 monitors the read / write error rate. At this time, because the I2C voltage is reduced, the overall power consumption of integrated circuit 10 decreases, which also means that the read / write error rate will increase accordingly. Therefore, the read / write error rate is monitored again to achieve a balance between the read / write error rate and the operating power consumption.
[0126] Thus, this application provides a control strategy for optimizing integrated circuit 10 when the second condition is met.
[0127] like Figure 5 As shown, in some embodiments, step 023 includes:
[0128] 0232: Determine if the second condition is true. If not, return to step 01.
[0129] Specifically, the following explains the situation when the second condition is not met. According to the above implementation, the second condition is met when integrated circuit 10 needs to adjust the I2C voltage to a lower level, and the current I2C voltage is not 1.8V. When one or both of the above conditions are not met, the second condition is not met. In the case where the second condition is not met, that is, when the I2C voltage is not adjusted, it can be known that neither the clock rate of the I2C host nor the I2C voltage is adjusted. In other words, the operation of integrated circuit 10 does not need further optimization or cannot be further optimized. In this case, it is sufficient to continue operating and continue monitoring the I2C read / write error rate.
[0130] Thus, this application provides a control strategy for optimizing integrated circuit 10 when the second condition is not met.
[0131] like Figure 3 As shown, in some embodiments, step 02 includes:
[0132] 021: Determine the relationship between the read / write error rate of the bidirectional two-wire synchronous serial bus and the preset threshold. If the read / write error rate is greater than the upper limit threshold, proceed to step 024.
[0133] 024: Determine whether the third condition is met. The third condition is: the clock rate of the bidirectional two-wire synchronous serial bus is set to the lowest level according to the preset clock rate level.
[0134] 025: Based on the fulfillment of the third condition, determine the control strategy to reduce the read / write error rate of the bidirectional two-wire synchronous serial bus.
[0135] In some implementations, the error statistician 112 is used to determine the relationship between the read / write error rate of the bidirectional two-wire synchronous serial bus and a preset threshold, and to determine whether a third condition is met, and to determine a control strategy based on the meeting of the third condition, so as to reduce the read / write error rate of the bidirectional two-wire synchronous serial bus.
[0136] Specifically, if the error statistician 112, used for line monitoring, detects that the I2C read / write error rate exceeds a preset upper limit threshold for a period of time, it indicates a problem with the current operating state of integrated circuit 10 and the I2C, resulting in a high I2C read / write error rate. In this case, adjustments need to be made to the operating state of integrated circuit 10 to reduce the I2C read / write error rate. As explained above, a higher clock rate or lower voltage results in a higher read / write error rate, and vice versa. Therefore, to reduce the I2C read / write error rate, the clock rate of the I2C host needs to be reduced or the I2C voltage increased. For the sake of stable operation of integrated circuit 10, the clock rate is first evaluated and adjusted. If the clock rate has reached its limit and cannot be adjusted further, the voltage is then evaluated and adjusted to reduce the I2C read / write error rate. Regarding the third condition mentioned above, the third condition indicates whether the current clock rate has reached its limit. As long as the clock rate has not reached its limit, the error counter 112 will adjust the clock rate of the I2C host.
[0137] In some examples, the component in error counter 112 used for line monitoring monitors the operation of I2C and finds that within the 30 seconds prior to the current time, the I2C read / write error rate η satisfies η>EU, that is, the I2C read / write error rate is greater than the upper limit threshold. This indicates that the current operating state of integrated circuit 10 is abnormal, and the I2C read / write error rate is too high. At this time, error counter 112 needs to adjust the operating state of I2C to reduce the read / write error rate. Next, it determines whether to reduce the I2C read / write error rate by adjusting the clock rate. According to the third condition, error counter 112 obtains the current operating state of integrated circuit 10 from controller 111 and determines the current clock rate of the I2C host in the preset clock rate level setting. According to the above implementation method, in some examples, the clock rate level in the preset clock rate level setting is divided into six levels from low to high: 10kHz, 100kHz, 200kHz, 400kHz, 800kHz, and 1MHz. The validity of the third condition is determined based on whether the clock rate of the I2C host is at the lowest level, i.e., 10kHz, and then it is determined whether the read / write error rate can be reduced by adjusting the clock rate: when the clock rate of the I2C host is 10kHz, the third condition is valid, otherwise it is not valid.
[0138] Thus, this application provides a control strategy when the read / write error rate is higher than expected.
[0139] like Figure 6 As shown, in some examples, step 02 includes:
[0140] 024: Determine if the third condition is true. If not, proceed to step 0251.
[0141] Based on this, step 025 includes:
[0142] 0251: According to the preset clock rate level setting, reduce the clock rate of the bidirectional two-wire synchronous serial bus by one level and return to step 01.
[0143] In some implementations, the error counter 112 is used to determine whether the third condition is met, and to reduce the clock rate of the bidirectional two-wire synchronous serial bus by one level according to the preset clock rate level setting, and return to step 01.
[0144] Specifically, the adjustment method of integrated circuit 10 when the third condition is not met will be explained next. According to the above implementation method, the third condition is met when the clock rate of the I2C host is 10kHz. Conversely, when the clock rate of the I2C host is not the lowest level of 10kHz, the third condition is not met. At this time, the clock rate can continue to decrease. Therefore, the clock rate of the I2C host is reduced by one level according to the preset clock rate level setting. Since the clock rate is reduced, the communication bandwidth inside integrated circuit 10 will also decrease, and the read / write error rate will also decrease accordingly. Then, the error statistician 112 continues to monitor the read / write error rate to immediately check the effect of the adjustment and to decide whether further adjustments to the operating state of integrated circuit 10 are needed.
[0145] In some examples, the error statistician 112 learns from data acquisition and processing that the current clock rate of the I2C host is 400kHz. Since the third condition is not met, the error statistician 112 lowers the clock rate of the I2C host by one level to 200kHz, then considers the adjustment process complete and returns to the state where the error statistician 112 monitors the read / write error rate. At this point, because the I2C clock rate is reduced, the read / write error rate will decrease accordingly. Subsequently, the error statistician 112 re-monitors the read / write error rate to verify the effect of this adjustment and determine subsequent adjustment strategies.
[0146] Thus, this application provides a control strategy for optimizing integrated circuit 10 when the third condition is not met.
[0147] like Figure 6 As shown, in some embodiments, step 02 includes:
[0148] 024: Determine if the third condition is true. If yes, proceed to step 0252.
[0149] Based on this, step 025 includes:
[0150] 0252: Determine whether the fourth condition is met. The fourth condition is: set the voltage of the bidirectional two-wire synchronous serial bus to the highest level according to the preset voltage level bit.
[0151] 0253: Determine the control strategy based on whether the fourth condition is met.
[0152] In some implementations, the error statistician 112 is used to determine whether the third condition is met, and to determine whether the fourth condition is met, and to determine the control strategy based on whether the fourth condition is met.
[0153] Specifically, the adjustment method of integrated circuit 10 when the third condition is met will be explained next. According to the above implementation, the third condition is met when the clock rate of the I2C host is 10kHz. When the third condition is met, that is, when the clock rate has reached its limit and cannot be adjusted, in order to reduce the I2C read / write error rate, it is determined whether the I2C voltage can be adjusted, specifically by determining whether the fourth condition is met. The fourth condition mentioned above indicates whether the voltage has reached its limit. As long as the voltage has not reached its limit, the error counter 112 will adjust the voltage of the I2C host.
[0154] Based on the above parameter characteristics, in some examples, when the third condition is met, i.e., the clock rate of the I2C host has reached its limit and cannot be adjusted, the next step is to determine whether to reduce the read / write error rate of integrated circuit 10 by adjusting the voltage. According to the fourth condition, the error statistician 112 obtains the current operating status of integrated circuit 10 from controller 111 and detects the current I2C voltage level in the preset voltage level setting. In some examples, the clock rate levels in the preset voltage level setting are divided into four levels from low to high: 1.8V, 2.5V, 3.3V, and 5V. When integrated circuit 10 needs to increase the I2C voltage and the current I2C host voltage is not 5V, the fourth condition is not met; otherwise, the fourth condition is met.
[0155] Thus, this application provides a control strategy for optimizing integrated circuit 10 when the third condition is met.
[0156] like Figure 7 As shown, in some embodiments, step 025 includes:
[0157] 0252: Determine if the fourth condition is true. If not, proceed to 02531.
[0158] Based on this, step 0253 includes:
[0159] 02531: According to the preset voltage level setting, increase the voltage of the bidirectional two-wire synchronous serial bus by one level, and return to step 01.
[0160] In some implementations, the error counter 112 is used to determine whether the fourth condition is met, and to increase the voltage of the bidirectional two-wire synchronous serial bus by one level according to the preset voltage level setting, and return to step 01.
[0161] Specifically, the adjustment method of integrated circuit 10 when the fourth condition is not met will be explained next. According to the above implementation method, the fourth condition is met when the current I2C voltage is 5V, and conversely, the fourth condition is not met when the current I2C voltage is not 5V. In some examples, the error statistician 112 learns from data acquisition and processing that integrated circuit 10 needs to increase the I2C voltage, and the current I2C voltage is 3.3V, at which point the fourth condition is not met. At this time, the error statistician 112 controls the external power supply to increase the I2C voltage by one level to 5V, and then considers the adjustment process complete, returning to the state where the error statistician 112 monitors the read / write error rate. At this time, because the I2C voltage has increased, the read / write error rate will decrease accordingly. Subsequently, the read / write error rate is monitored again to verify the effect of this adjustment and determine the subsequent adjustment strategy.
[0162] Thus, this application provides a control strategy for optimizing integrated circuit 10 when the fourth condition is not met.
[0163] like Figure 7 As shown, in some embodiments, step 025 includes:
[0164] 0252: Determine if the fourth condition is true. If yes, proceed to step 02532.
[0165] Based on this, step 0253 includes:
[0166] 02532: Send an adjustment failure report to the controller 111 in integrated circuit 10 and return to step 01. The adjustment failure report describes that the read / write error rate of the bidirectional two-wire synchronous serial bus cannot be adjusted.
[0167] In some implementations, the error statistician 112 is used to determine whether the fourth condition is met, and to send an adjustment failure report to the controller 111 in the integrated circuit 10, and return to step 01.
[0168] Specifically, the following describes the situation when the fourth condition is met. According to the above implementation method, the fourth condition is met when the current I2C voltage is 5V. When the fourth condition is met, that is, when the I2C voltage has reached its limit and cannot be adjusted, it can be known that neither the clock rate of the I2C host nor the I2C voltage can be adjusted. In other words, the read / write error rate of the I2C in the integrated circuit 10 can be reduced. At this time, the error statistician 112 sends an adjustment failure report to the controller 111 to notify the controller 111 that the current I2C read / write error rate cannot be reduced, so that the controller 111 can take other actions in response to this situation and remind the technicians of the abnormal working state of the integrated circuit 10. At the same time, in this situation, the error statistician 112 should continue to monitor the I2C read / write error rate to obtain more basic data for subsequent maintenance work.
[0169] Thus, this application provides a control strategy for optimizing integrated circuit 10 when the fourth condition is met.
[0170] In summary, in some examples, the various embodiments of the integrated circuit control method provided in this application can be derived from, for example... Figure 8 The process shown is implemented.
[0171] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
Claims
1. An integrated circuit control method, characterized in that, The method includes: Obtain the read / write error rate of a bidirectional two-wire synchronous serial bus; The read / write error rate is compared with a preset threshold, and a control strategy is determined based on the comparison result to optimize the operation of the integrated circuit. The step of comparing the read / write error rate with a preset threshold and determining a control strategy based on the comparison result further includes: When the read / write error rate is less than a preset lower threshold, Determine whether the first condition is met. The first condition is: the integrated circuit requires to increase the clock rate of the bidirectional two-wire synchronous serial bus, and the clock rate of the bidirectional two-wire synchronous serial bus is not set to the highest level according to the preset clock rate level bit. Based on whether the first condition is met, the control strategy is determined to optimize the operation of the integrated circuit.
2. The method according to claim 1, characterized in that, The comparison of the read / write error rate with a preset threshold, and the determination of a control strategy based on the comparison result, includes: The read / write error rate of the bidirectional two-wire synchronous serial bus is obtained when the read / write error rate is greater than or equal to a preset lower threshold and less than or equal to a preset upper threshold.
3. The method according to claim 1, characterized in that, Determining the control strategy based on the fulfillment of the first condition includes: If the first condition is met... According to the preset clock rate level setting, the clock rate of the bidirectional two-wire synchronous serial bus is increased by one level; Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
4. The method according to claim 1, characterized in that, The step of determining the control strategy based on the fulfillment of the first condition further includes: If the first condition is not met. Determine whether the second condition is met. The second condition is: the integrated circuit requires a reduction in the voltage of the bidirectional two-wire synchronous serial bus, and the voltage of the bidirectional two-wire synchronous serial bus is not set to the lowest level according to the preset voltage level. The control strategy is determined based on whether the second condition is met.
5. The method according to claim 4, characterized in that, Determining the control strategy based on the fulfillment of the second condition includes: If the second condition is met... According to the preset voltage level setting, the voltage of the bidirectional two-wire synchronous serial bus is reduced by one level; Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
6. The method according to claim 4, characterized in that, Determining the control strategy based on the fulfillment of the second condition includes: If the second condition is not met. Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
7. The method according to claim 1, characterized in that, The comparison of the read / write error rate with a preset threshold, and the determination of a control strategy based on the comparison result, includes: When the read / write error rate exceeds a preset upper limit threshold, Determine whether the third condition is met. The third condition is: the clock rate of the bidirectional two-wire synchronous serial bus is set to the lowest level according to the preset clock rate level. Based on the fulfillment of the third condition, the control strategy is determined to reduce the read / write error rate of the bidirectional two-wire synchronous serial bus.
8. The method according to claim 7, characterized in that, Determining the control strategy based on the fulfillment of the third condition includes: If the third condition is not met, According to the preset clock rate level setting, the clock rate of the bidirectional two-wire synchronous serial bus is reduced by one level. Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
9. The method according to claim 7, characterized in that, Determining the control strategy based on the fulfillment of the third condition includes: If the third condition is met, Determine whether the fourth condition is met. The fourth condition is: the voltage of the bidirectional two-wire synchronous serial bus is set to the highest level according to the preset voltage level bit. The control strategy is determined based on whether the fourth condition is met.
10. The method according to claim 9, characterized in that, Determining the control strategy based on the fulfillment of the fourth condition includes: If the fourth condition is not met, According to the preset voltage level setting, the voltage of the bidirectional two-wire synchronous serial bus is increased by one level; Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
11. The method according to claim 9, characterized in that, Determining the control strategy based on the fulfillment of the fourth condition includes: If the fourth condition is met, An adjustment failure report is sent to the controller in the integrated circuit, the adjustment failure report describing that the read / write error rate of the bidirectional two-wire synchronous serial bus cannot be adjusted; Obtain the read / write error rate of the bidirectional two-wire synchronous serial bus.
12. An integrated circuit, characterized in that, The integrated circuit includes a control module and an execution module, the control module and the execution module being connected via a bidirectional two-wire synchronous serial bus, the control module comprising: A controller for controlling the operation of the integrated circuit; and An error counter is used to obtain the read / write error rate of a bidirectional two-wire synchronous serial bus, and to compare the read / write error rate with a preset threshold. Based on the comparison result, a control strategy is determined to optimize the operation of the integrated circuit. The step of comparing the read / write error rate with a preset threshold and determining a control strategy based on the comparison result further includes: When the read / write error rate is less than a preset lower threshold, Determine whether the first condition is met. The first condition is: the integrated circuit requires to increase the clock rate of the bidirectional two-wire synchronous serial bus, and the clock rate of the bidirectional two-wire synchronous serial bus is not set to the highest level according to the preset clock rate level bit. Based on whether the first condition is met, the control strategy is determined to optimize the operation of the integrated circuit.
Citation Information
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Method for improving data transmission quality, USB device and storage medium
CN115114217A