Authenticated reading of memory system data

Abstract

This application relates to authenticated reads of memory system data. In some examples, a host system and a memory system can exchange a key used to grant the host system permission to access one or more protected regions of the memory system. The key can be symmetric or asymmetric. In some cases, the host system can transmit a read command to access data stored in a protected region of the memory system, along with a signature generated using the key associated with the protected region. The memory system can verify the signature to determine whether the host is authorized to access the protected region, and can transmit the requested data to the host system. In some examples, the memory system can sign the returned data so that the host system can verify the origin of the data.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 664,354, filed May 20, 2022, entitled “Authenticated Reading of Memory System Data”, filed by Dover et al., and U.S. Provisional Patent Application No. 63 / 270,927, filed October 22, 2021, entitled “Authenticated Reading of Memory System Data”, both of which are assigned to the assignee and are expressly incorporated herein by reference in their entirety. Technical Field

[0003] This technical field relates to the authentication and reading of data in memory systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to typically correspond to one of two supported states, logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even without an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a controller configured to be coupled to a memory system, wherein the controller is configured to cause the apparatus to: transmit one or more keys associated with a host system, wherein each of the one or more transmitted keys is associated with a corresponding protected area among one or more protected areas at the memory system; transmit a signature command to read data from a first protected area among the one or more protected areas, wherein the signature command is signed at least in part based on a pairing key corresponding to the first transmitted key among the one or more transmitted keys, and wherein the first protected area is associated with the first transmitted key associated with the host system; and receive the data at least in part based on the transmission of the signature command.

[0007] Another device is described. The device may include a memory system; and a controller for the memory system and configured to cause the device to: receive one or more keys associated with a host system, wherein each of the one or more received keys corresponds to a corresponding paired key associated with the host system and is associated with a corresponding protected area among one or more protected areas at the memory system; receive a signed command to read data from a first protected area among the one or more protected areas, wherein the first protected area is associated with a first received key among the one or more received keys; determine whether to read the data from the first protected area based at least in part on an attempt to decrypt the signature of the signed command, wherein the attempt to decrypt the signature is at least in part based on the first received key associated with the host system; and transmit the data based at least in part on the successful decryption of the signature of the signed command.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium stores code, the code potentially containing instructions that, when executed by a processor of an electronic device, cause the electronic device to: transmit one or more keys associated with a host system, wherein each of the one or more transmitted keys is associated with a corresponding protected area among one or more protected areas at a memory system; transmit a signature command to read data from a first protected area among the one or more protected areas, wherein the signature command is signed at least in part based on a pairing key corresponding to the first transmitted key among the one or more transmitted keys, and wherein the first protected area is associated with the first transmitted key associated with the host system; and receive the data at least in part based on the transmission of the signature command.

[0009] Another non-transitory computer-readable medium is described. The non-transitory computer-readable medium stores code, which may contain instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive one or more keys associated with a host system, wherein each of the one or more received keys corresponds to a corresponding paired key associated with the host system and is associated with a corresponding protected area among one or more protected areas at a memory system; receive a signed command to read data from a first protected area among the one or more protected areas, wherein the first protected area is associated with a first received key among the one or more received keys; determine whether to read the data from the first protected area based at least in part on an attempt to decrypt the signature of the signed command, wherein the attempt to decrypt the signature is based at least in part on the first received key associated with the host system; and transmit the data based at least in part on the successful decryption of the signature of the signed command. Attached Figure Description

[0010] Figure 1 Examples of systems that support authenticated reading of memory system data, based on the examples disclosed herein, are shown.

[0011] Figure 2 Examples of systems that support authenticated reading of memory system data, based on the examples disclosed herein, are shown.

[0012] Figure 3 Examples of systems that support authenticated reading of memory system data, based on the examples disclosed herein, are shown.

[0013] Figure 4 This document illustrates an example of a process flow that supports authenticated reading of memory system data, based on the examples disclosed herein.

[0014] Figure 5 A block diagram of a host device that supports authenticated reading of memory system data according to the examples disclosed herein is shown.

[0015] Figure 6 A block diagram of a memory device that supports authenticated reading of memory system data according to the examples disclosed herein is shown.

[0016] Figure 7 and 8 The flowchart illustrates one or more methods for supporting authenticated reading of memory system data according to the examples disclosed herein. Detailed Implementation

[0017] Some computing platforms may involve one or more host systems that can communicate with one or more memory systems (e.g., directly or indirectly). For example, a host system may transmit access commands, such as read commands, to a memory system to access data stored in a secure location, such as a replay protected memory block (RPMB), using symmetric key pairs stored in both the host system and the memory system. In some cases, the memory system may sign the data associated with the access command to verify with the host system that the data originated from memory. However, some methods for executing read commands from a protected area of ​​a memory device may involve removing the protected state of the area when retrieving data, which could make the memory system vulnerable to attacks from malicious parties who might attempt to access data without protecting the area. Furthermore, some methods, such as protecting areas of a memory device using RPMBs, may not allow the use of more secure data protection schemes, such as signing and verifying data using asymmetric keys, or updating host system or memory system keys over time. Additionally, some methods may not allow for custom configuration or dynamic adjustment of protected area attributes, such as the size of the protected area or the address range associated with it. Therefore, efficient techniques for accessing protected areas of a memory device are needed.

[0018] As described in this disclosure, the host system and the memory system can exchange keys to grant the host system access to one or more protected areas of the memory system. The keys can be symmetric (e.g., the host system and the memory system can share the same key) or asymmetric (e.g., both the host system and the memory system can have unique private keys and can share corresponding public keys with each other), and can be updated periodically (e.g., according to an encryption period determined by the host system or the memory system). Alternatively, the host system and the memory system can exchange separate keys for different protected areas of the memory system.

[0019] In some scenarios, the host system can transmit read commands to access data stored in a protected area of ​​the memory system, and the host system can sign the read commands using a key associated with the protected area. Upon receiving the read command, the memory system can verify the signature to determine if the host is authorized to access the protected area, and can then transfer the requested data to the host system. In some instances, the memory system can sign the returned data, allowing the host system to verify the data's origin. In some cases, the protected area of ​​the memory system can be updated in response to commands from the host system by, for example, adjusting the size or address range of the protected area. The techniques described herein can, for example, improve the security of a computing platform by more thoroughly protecting data from malicious attacks and allowing verification of the data source transmitted between the host system and the memory system.

[0020] Firstly, in reference Figure 1 The features of this disclosure are described in the context of systems, apparatus, and circuits. (Referencing...) Figure 2-4 The features of this disclosure are described in the context of the system and process flow. Further details are provided by reference. Figure 5-8 Device diagrams and flowcharts relating to the authentication and reading of data from a memory system are shown and described in the context of the device diagrams and flowcharts. These and other features of this disclosure are described.

[0021] Figure 1 An example of a system 100 supporting authenticated reading of memory system data according to the examples disclosed herein is shown. System 100 includes a host system 105 coupled to a memory system 110.

[0022] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0023] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0024] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 A memory system 110 is shown, but the host system 105 can be coupled to any number of memory systems 110.

[0025] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0026] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0027] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or updating data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0028] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0029] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations described herein that pertain to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0030] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, it may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0031] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions belonging to memory system controller 115 herein. Generally, one or more functions belonging to memory system controller 115 herein may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0032] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0033] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135, which can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0034] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0035] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0036] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, a single block 170 may be referred to as a physical block, and virtual block 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0037] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0038] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0039] System 100 may include any number of non-transitory computer-readable media that support authenticated reading of memory system data. For example, host system 105, memory system controller 115, or memory device 130 (e.g., local controller 135) may include or otherwise access one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions described herein that pertain to host system 105, memory system controller 115, or memory device 130. For example, such instructions, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0040] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0041] In some instances, host system 105 and memory system 110 may exchange keys to grant host system 105 access to one or more protected areas of memory system 110 (e.g., one or more protected areas of memory device 130). The keys may be symmetric (e.g., host system 105 and memory system 110 may share the same key) or asymmetric (e.g., host system 105 and memory system 110 may each have a unique private key and may share a corresponding public key with each other), and may be updated periodically (e.g., according to an encryption period determined by host system 105 or memory system 110). Alternatively, host system 105 and memory system 110 may exchange separate keys for different protected areas of memory system 110. In some cases, host system 105 may transmit read commands to access data stored in protected areas of memory system 110, and host system 105 may sign the read commands using the key associated with the protected area. Upon receiving a read command, memory system 105 can verify the signature to determine whether host system 105 is authorized to access the protected area, and can transfer the requested data to host system 105. In some instances, memory system 110 can sign the returned data, allowing host system 105 to verify the data's origin. In some cases, the protected area of ​​memory system 110 can be updated in response to commands from the host system, such as by adjusting the size or address range of the protected area. The techniques described herein can improve the security of a computing platform, for example, by more thoroughly protecting data from malicious attacks and allowing verification of the data source transmitted between host system 105 and memory system 110.

[0042] Figure 2 An example of a system 200 supporting authenticated reading of memory system data according to the examples disclosed herein is shown. System 200 may include a host system 105-a and a memory system 110-a, which may be a reference system. Figure 1Examples of the corresponding systems described. Host system 105-a and memory system 110-a may implement various techniques for exchanging public keys to support signaling communication between the corresponding systems with identity authenticity (e.g., signature) and integrity (e.g., encryption), as well as other characteristics that may be based on the unique and private cryptographic identity of host system 105-a and memory system 110-a. Host system 105-a may include host system controller 106-a and memory system 110-a may include memory system controller 115-a, and in some instances, host system controller 106-a and memory system controller 115-a may be configured to perform one or more of the described operations at host system 105-a and memory system 110-a, respectively. Although the single host system 105-a and single memory system 110-a of the reference system 200 describe the technology, the described technology can be extended to support the implementation of host systems 105 coupled to any number of memory systems 110, or the implementation of memory systems 110 coupled to any number of host systems 105, or the implementation of a network of multiple host systems 105 coupled to multiple memory systems 110.

[0043] Host system 105-a may be an example of a system that uses at least a portion of memory system 110-a (e.g., storage device 240) for information storage, and may include various operations supporting host system 105-a writing information to memory system 110-a or host system 105-a reading information from memory system 110-a, or both. In some instances, host system 105-a may be characterized as “local,” referring to a relatively direct or near-end physical, electrical, or otherwise communicatively coupled connection. In some other instances, host system 105-a may be characterized as “remote,” referring to a relatively distant (e.g., not in the same location) communicatively coupled connection, which may involve one or more wired, wireless, optical, or otherwise relatively distant communicatively coupled connections, such as cloud applications or otherwise distributed computing systems.

[0044] In some instances, host system 105-a may include one or more host entities 210, which may be coupled to or otherwise associated with the one or more host entities. Host entity 210 may be implemented as a hardware entity, firmware entity, or software entity, and may include various serial, parallel, or hierarchical couplings or logical organizations with or via host system 105-a. In some instances, host entity 210 may request or otherwise execute signaling with memory system 110-a via a common controller or interface (e.g., via host system controller 106-a). In various instances, host entity 210 may be associated with different functions, different feature sets, different permissions, different storage attributes (e.g., data protection attributes), and other different characteristics.

[0045] In some instances, each of host entities 210 may be associated with a unique identifier (e.g., a secret identifier, a unique device secret, a unique entity secret), which may contain or support the generation of a corresponding private key for host entity 210. In some instances, the identifier of host entity 210 itself may not be private, but a private key for host entity 210 may be generated based on the identifier of host entity 210 (e.g., public or private) and the private identifier of host system 105-a (e.g., a private master identifier). Such techniques can support the unique identification and authentication (e.g., separation from other host entities 210) of each of host entities 210 according to the examples disclosed herein.

[0046] Instances of host system 105-a may be associated with original equipment manufacturer (OEM) host entity 210-a (e.g., a first host entity), operating system (OS) vendor host entity 210-b (e.g., a second host entity), and independent software vendor (ISV) host entity 210-c (e.g., a third host entity). In some other instances, host system 105 may include any number of one or more host entities 210 or otherwise associate with said any number of one or more host entities, including, but not limited to, one or more OEM host entities 210, OS vendor host entities 210, ISV host entities 210, or other types of host entities. In some instances, host entities 210 may be omitted or otherwise not considered separately, in which case a master private key may be implemented by host system 105-a (and any applicable host entities 210), which may be based on a single or shared unique identifier of host system 105-a (e.g., a secret identifier, a unique device secret, or a unique host secret associated with host system 105-a).

[0047] In some instances, host system 105-a may be associated with a location (e.g., key storage device 215) for storing authentication or encryption information (e.g., generated or received keys, certificates). For example, host system 105-a may use key storage device 215 to store one or more private keys or certificates associated with host system 105-a. In some instances, key storage device 215 may be part of host system 105-a, such as an implementation of a dedicated storage component of host system 105-a. Alternatively or additionally, one or more components of key storage device 215 may be located outside of host system 105-a but accessible by host system 105-a in other ways (e.g., securely). In various instances, key storage device 215 may include non-volatile storage locations (e.g., for static keys or keys maintained for a relatively long time), or volatile storage locations (e.g., for ephemeral keys or keys generated relatively frequently in other ways), or both. Although the key storage device 215 is shown as separate from the host system controller 106-a, in some instances, the key storage device 215 may be part of the host system controller 106-a or otherwise associated with the host system controller, for example, also containing the storage location of the firmware of the host system 105-a or the host system controller 106-a.

[0048] In some instances, host system 105-a may contain content 220, which may refer to various types of information stored at host system 105-a. In some instances, according to the examples disclosed herein, content 220 may be accessed or otherwise used to support various key generation (e.g., content-based key generation) or other cryptographic techniques. For example, content 220 may contain firmware of host system 105-a, such as boot code (e.g., Level 2 boot code, "L1" boot code), or firmware security descriptor (FSD), which can be used to establish the operational or cryptographic state of host system 105-a (e.g., firmware state). In some instances, information associated with content 220 may be transferred to memory system 110-a to support various authentication or cryptographic techniques (e.g., for memory system 110-a to generate keys or certificates for operation with memory system 110-a). Although content 220 is shown as separate from host system controller 106-a, in some instances, content 220 may be part of host system controller 106-a or otherwise associated with the host system controller, such as containing the storage location of firmware for host system 105-a or host system controller 106-a.

[0049] Memory system 110-a may include storage devices 240, which may refer to one or more instances of local memory 120 or a collection of storage capacity of one or more memory devices 130, or various combinations thereof included in or otherwise associated with memory system 110-a. In some instances, storage devices 240 may be partitioned or otherwise organized in partitions 245 (e.g., memory ranges, address ranges), which may refer to various subsets or ranges of logical or physical addresses of the associated local memory 120 or memory devices 130. In some instances, partition 245 may be assigned an initial address range and may be updated by assigning different address ranges, including adding additional new addresses, assigning to a subset of the initial address range (e.g., fine-tuning the range), or assigning to entirely new address ranges.

[0050] In some instances, partition 245, or portions thereof, may be assigned or allocated to different functions or attributes. For example, one or more partitions 245 may be associated with one or more corresponding host entities 210 or their corresponding public or private keys. In example implementations, partition 245-a may be associated with OEM host entity 210-c, partition 245-b may be associated with OS vendor host entity 210-b, and partition 245-c may be associated with ISV host entity 210-c. In some instances, partition 245-d may be unassigned (e.g., not dedicated to a particular purpose or entity, available space), or may be shared among multiple host entities 210, as well as other instances used to allocate partition 245. In some instances, partition 245 may be used to implement various hierarchical keying or authentication technologies. For example, each partition 245 or a portion of partition 245 may be assigned protection attributes or updated with protection attributes (e.g., enabling or disabling write protection attributes, enabling or disabling read protection attributes), which may be associated with various keys, authentication, or encryption specific to a given host entity 210, or in general, in other instances, with various keys, authentication, or encryption common to host system 105-a.

[0051] In some instances, memory system 110-a may be associated with a location (e.g., key storage device 250) for storing authentication or encryption information (e.g., generated or received keys, certificates). For example, memory system 110-a may use key storage device 250 to store one or more private keys associated with memory system 110-a, or one or more public keys or certificates generated by memory system 110-a, or one or more public keys or certificates received from host system 105-a (or other host system 105, not shown). In some instances, key storage device 250 may be part of memory system 110-a, such as an implementation of a dedicated storage component of memory system 110-a. Alternatively or additionally, key storage device 250 may be located external to memory system 110-a, but may be otherwise accessible by memory system 110-a (e.g., securely). In various instances, key storage device 250 may include non-volatile storage locations (e.g., for static keys or keys maintained for a relatively long time), or volatile storage locations (e.g., for ephemeral keys or keys generated relatively frequently in other ways), or both. While key storage device 250 is shown separate from storage device 240, in some instances, key storage device 250 may be included within a portion of storage device 240 (e.g., included in a separate or dedicated partition 245). Furthermore, while key storage device 250 is shown separate from memory system controller 115-a, in some instances, key storage device 250 may be part of or otherwise associated with memory system controller 115-a, for example, also including storage locations for firmware for memory system 110-a or memory system controller 115-a (e.g., local memory 120).

[0052] In some instances, memory system 110-a may include a Physically Unclonable Function (PUF) 255 that supports the assignment or generation of a unique identifier for memory system 110-a (e.g., a secret identifier or unique device secret for generating memory system 110-a). PUF 255 may include various components or circuit elements having inherent physical characteristics that make PUF 255 unique, which can be used to establish the inherent uniqueness of memory system 110-a. For example, PUF may include a set of one or more transistors, resistors, capacitors, memory cells (e.g., SRAM cells, which in some cases may be included in a reference...) Figure 1The PUF 255 may be located in the local memory 120 described herein, or other circuit elements or combinations thereof, which, when accessed, support the generation of a unique digital signature for memory system 110-a. In some instances, the controller of memory system 110-a (e.g., memory system controller 115-a) may access or otherwise interact with PUF 255 to generate one or more private keys for memory system 110-a, which may then be used to generate public keys for establishing authenticity or encryption between memory system 110-a and host system 105-a (e.g., or, where applicable, host entity 210). Although PUF 255 is shown as separate from key storage device 250, in some instances, PUF 255 may be included in key storage device 250 or otherwise interpreted as a portion of key storage device (e.g., a portion of memory system controller 115-a, a portion of local memory 120 of memory system 110-a).

[0053] In various implementations, PUF 255 itself, or the signaling generated by PUF 255, or both, is inaccessible from outside the memory system 110-a. In portions of the memory system 110-a, such inaccessibility may be supported by various implementations including PUF 255 and other components involved in the described cryptographic techniques, wherein an attempt to access such components would be destructive to the components, or wherein such components or associated signaling are otherwise shielded from destructive or non-destructive probing or eavesdropping techniques. For example, if not all components of the memory system 110-a, at least PUF 255 and other components involved in the described cryptographic techniques (e.g., components involved in processing private keys or unique device secrets, which may include at least a portion or at least a part of the memory system controller 115-a) may be implemented in a continuous semiconductor chip, such as a SoC implementation.

[0054] In some instances, storage system 110-a may include a public key table 260 (e.g., an elliptic curve cryptography public key table), which may be configured to store, organize, or distribute public keys, such as public keys received from host system 105-a or public keys generated at storage system 110-a, or both. In some instances (e.g., in embodiments where host entity 210 is associated with a corresponding public key transmitted by host system 105-a), public key table 260 may maintain a corresponding public key or its mapping for each of OEM host entity 210-a, OS vendor host entity 210-b, and ISV host entity 210-c (e.g., associated with partitions 245-a, 245-b, and 245-c, respectively). Although the public key table 260 is shown as separate from the key storage device 250, in some instances, the public key table 260 may be contained in the key storage device 250 or otherwise interpreted as a portion of the key storage device (e.g., a portion of the memory system controller 115-a, a portion of the local memory 120 of the memory system 110-a).

[0055] In some implementations, public key table 260 may be associated with mappings between public keys and device identifiers, or partitions 245, or protection attributes (e.g., write protection configuration, read protection configuration), or various combinations thereof, as well as other mappings between keys and associated configurations. For example, public key table 260 may provide specific public keys or symmetric keys to mappings of one or more host systems 105 (e.g., host system 105-a) or their host entities 210. Such mappings may also include mappings between such keys and one or more partitions 245, or mappings between such keys or partitions 245 and one or more protection attributes, such as whether partition 245 is configured with read protection, write protection, or both. In some instances, the mappings of public key table 260 may include mappings of keys, host systems 105, or host entities 210 to multiple partitions 245, which may use a common key but have unique protection attributes to support each partition 245. In some instances, the public key table may support a key hierarchy structure that allows the master host system 105 or its associated key to assign partition 245 to another host system 105 or to host entity 210 or its corresponding key.

[0056] In some instances, memory system 110-a may include a platform configuration register (PCR) 270, which may store or measure software state (e.g., version, update status), such as the state of software running on memory system 110-a, and configuration data used by such software (e.g., platform software state for representing memory system 110-a). In some instances, PCR 270 may contain information that can be evaluated to determine whether memory system 110-a has been compromised or may otherwise be untrustworthy. Although PCR 270 is shown as separate from memory system controller 115-a, in some instances, PCR 270 may be part of or otherwise associated with memory system controller 115-a, such as a location associated with firmware for memory system 110-a or memory system controller 115-a (e.g., local memory 120). Such techniques may enable PCR 270 to store or measure the state of such firmware, which can be used to assess whether such firmware has been adversely updated (e.g., to assess whether memory system 110-a is authenticable).

[0057] In some instances, memory system 110-a may include RPMB 265, which can be provided as a component for storing data in an authenticated and replay-protected manner, the data being read and written only via successfully authenticated read and write access. In some instances, RPMB 265 may contain information that can be evaluated to determine whether signaling exchanged with memory system 110-a has been intercepted and replayed, indicating whether one or more devices or connections of system 200 are untrusted. Although RPMB 265 is shown as separate from memory system controller 115-a, in some instances, RPMB 265 may be part of or otherwise associated with memory system controller 115-a, for example, containing a storage location (e.g., local memory 120) for firmware for memory system 110-a or memory system controller 115-a. In some instances, RPMB 265 may be associated with a fixed size, a fixed set of addresses, or both.

[0058] In some instances, memory system 110-a may contain content 280, which may refer to various types of information stored at memory system 110-a. In some instances, according to the examples disclosed herein, content 280 may be accessed or otherwise used to support various key generation (e.g., content-based key generation) or other cryptographic techniques. For example, content 280 may contain firmware of memory system 110-a, such as boot code (e.g., Level 1 boot code, "L0" boot code, Level 2 boot code, "L1" boot code), or FSD, which can establish the operational or cryptographic state of memory system 110-a. In some instances, information associated with content 280 may be available to memory system 110-a to support various authentication or cryptographic techniques (e.g., for generating certificates to operate with host system 105-a). Although content 280 is shown as separate from memory system controller 115-a, in some instances, content 280 may be a portion of memory system controller 115-a or otherwise associated with said memory system controller, for example, containing a storage location for firmware for memory system 110-a or memory system controller 115-a. Furthermore, although content 280 is shown as separate from storage device 240, in some instances, content 280 may refer to information contained in a portion of storage device 240 (e.g., contained in a separate or dedicated partition 245). In some embodiments, content 280 may receive information from or refer to one or more aspects of PCR 270.

[0059] One or more components of system 200 may be configured to implement asymmetric key distribution to establish authenticated signaling, encrypted signaling, or both (e.g., based on authenticated system identity) between host system 105-a and memory system 110-a. This may include implementing cryptographic security functionality directly within memory system 110-a (e.g., leveraging the capabilities of memory system controller 115-a to support various techniques for asymmetric cryptography). In some instances, such techniques may involve transmitting substantially public device identification information between host system 105-a and memory system 110-a, which supports private authentication for the respective system (e.g., device-specific or hardware-specific authentication without attempting to keep secret or avoid exposing the private or secret key material exchanged corresponding to the respective device). In some instances, such asymmetric cryptography can be used to derive equivalents or other symmetric keys on each side of the signaling exchange (e.g., at each of host system 105-a and memory system 110-a) using a common secret that is not transmitted between host system 105-a and memory system 110-a. This can take full advantage of the efficiency of symmetric key techniques used for authentication or encrypted signaling relative to asymmetric key techniques. In some instances, such techniques can be implemented to establish a virtual authentication channel 205 between host system 105-a and memory system 110-a, which can be used to transmit signaling (e.g., encrypted signaling, unencrypted signaling) and associated signatures (e.g., asymmetric signatures, such as Elliptic Curve Digital Signature Algorithm (ECDSA) signatures; symmetric signatures, such as Hash Message Authentication Code (HMAC) signatures) between host system 105-a and memory system 110-a.

[0060] In some instances, system 200 may be configured to support the signing and verification (e.g., authentication) of signaling between host system 105-a and memory system 110-a (e.g., based on signature command signaling, signature request signaling, signature data signaling, or signature response signaling). This can be implemented to authenticate the transport system carrying such signaling, or to ensure that the signaling has not been altered before being received by the receiving system, or both. According to such techniques, the receiving system may be able to evaluate the received signaling to determine whether the transmitted signaling was transmitted by an unverified or unauthorized transport system, or whether the transmitted signaling has been altered or otherwise compromised. In some instances, such techniques may support a one-to-many security arrangement because multiple receiving systems may be able to implement the same public key of the transport system (e.g., the same public key of an asymmetric key pair) associated with a single private key of the transport system (e.g., a single private key of an asymmetric key pair). A key contained in the same key pair as another key can be called the paired key of the other key (for example, the private key and public key in an asymmetric key pair can be paired parts of each other, and the two symmetric keys in a symmetric key pair can be paired parts of each other).

[0061] In some instances used for signing and verifying signaling between host system 105-a and memory system 110-a, the signature for a given instance of signaling (e.g., message, command, request, packet, response) can be derived from an instance of signaling that is hashed by a function (e.g., hash function, cryptographic hash algorithm) or otherwise processed, which receives the instance of signaling and a private key associated with the transport system as input. The output of such a function (e.g., signature, hash digest) can be recreated using the same function with the same signaling instance and the same private key associated with the transport system or an associated public key associated with the transport system (e.g., the public key of an asymmetric key pair). In one instance, for a signaling instance associated with 1 megabyte of program operation, the hash function based on 1 megabyte of data and the private key could be a 256-bit signature or hash digest.

[0062] To support verification of the authenticity of the transmission system, the transmission system may transmit a signaling instance and a corresponding signature that can be received by the receiving system. The receiving system may have received or otherwise generated the associated public key of the transmission system, and therefore, can generate a trial signature based on the received signaling instance and the associated public key of the transmission system. If the trial signature matches the received signature, the receiving system can determine that the transmission system is reliable (e.g., the signaling instance is a transmission from a trusted system) and can continue processing or otherwise perform a responsive action on the received signaling instance. In some implementations, signature generation can be configured such that the generated signatures will be different even when the signaling instances are the same. In such implementations, the signature generation and verification operations may further be based on random numbers, temporary values, or monotonic counters understood to be used by both the transmission and receiving systems.

[0063] In some instances, system 200 may be configured to support encryption and decryption processing of signaling between host system 105-a and memory system 110-a (e.g., based on encrypted signatures, encrypted command signaling, encrypted request signaling, encrypted data signaling, or encrypted responses), which may be implemented to ensure that the content of such signaling is not intercepted and decrypted or otherwise processed (e.g., to maintain the integrity of the signaling itself). According to such techniques, the transport system may encrypt the signaling instance for transmission using a key known to the transport system (e.g., the key of a symmetric key pair), and the receiving system may decrypt the received such signaling instance using a key known to the receiving system (e.g., the key of the same symmetric key pair), which may be the same as the symmetric key known to the transport system, or may otherwise be equivalent to or usable for such decryption. In some instances, such techniques may support a one-to-one security arrangement because the symmetric key pair can be understood as only a single transport system and a single receiving system (e.g., when the symmetric key pair is based on a unique identifier for each of the transport and receiving systems). However, some encryption techniques can support arrangements other than one-to-one security arrangements, such as when the symmetric key is based on a unique identifier from more than two systems.

[0064] Some implementations of the described technology can utilize asymmetric cryptography, where the public key associated with host system 105-a can be uploaded to one or more storage systems 110 (e.g., storage system 110-a) without exposing the private key of host system 105-a. This prevents malicious actors from stealing the key and impersonating the true key holder (e.g., impersonating host system 105-a). Such technologies can also allow for the replacement of public keys, which may differ from other technologies, such as those associated with RPMB or replay protected monotonic counters (RPMC). In some instances, such asymmetric cryptographic techniques can facilitate the use of public key infrastructure (PKI) technologies, where keys can be verified via a standardized chain of digital certificates.

[0065] In some implementations, the exchange of public keys can support the generation of symmetric keys at each of the host system 105-a and the memory system 110-a using techniques such as Diffie-Hellman key exchange or elliptic curve techniques, enabling the sharing of symmetric secrets between the device and the host without exposing the private keys of the respective systems. In some implementations, an asymmetric Diffie-Hellman key exchange can be performed between the host system 105-a and the memory system 110-a to generate symmetric keys, which are then used to achieve better performance at either the host system 105-a or the memory system 110-a for authentication, encryption, or both. Furthermore, the same algorithm shared by the host system 105-a and the memory system 110-a can be used to derive ephemeral symmetric keys, making it more difficult for adverse actors to extract or copy such keys; this is based on various techniques for generating ephemeral keys used for duration initiation or event initiation.

[0066] In some instances, the exchange of public keys may be associated with the creation of digital certificates, which may contain various signaling or other interactions with one or more certificate authorities or registration authorities, or may involve self-signed certificates or various combinations thereof. For example, host system 105-a, a cloud authority, or other centralized certification authority communicating with host system 105-a may generate a Certificate Signing Request (CSR), which may be an instance of a self-signed certificate proving that storage system 110-a has a private key associated with the public key in the CSR. In some instances, such CSRs may be transmitted from storage system 110-a to a centralized certification authority as part of a manufacturing operation (e.g., for manufacturing storage system 110-a). In some implementations, in response to the identity of storage system 110-a being verified (e.g., by a cloud authority), a manufacturer-approved certificate may be provided to host system 105-a, storage system 110-a, or both. In some instances, such techniques may support requesting the system to download a manufacturer-approved certificate (e.g., a certificate authority-approved certificate) or download a CSR.

[0067] Figure 3 An example of system 300 supporting authenticated reading of memory system data according to the examples disclosed herein is shown. System 300 may include one or more zones of the memory system, such as zone 305-a, zone 305-b, zone 305-c, zone 305-d, or zone 305-e. In some cases, the memory system may be an example of memory system 110 or aspects of memory system 110-a, as referenced in [reference]. Figure 1 and 2As described. In some cases, each of one or more regions 305 can be a different region, group, or memory cell, such as one or more blocks of memory cells, one or more memory dies, or other arrangements of memory cells. The memory cells contained in region 305 can be a contiguous region of memory cells or can be distributed throughout the memory system.

[0068] In some cases, zone 305 can be a protected zone, such as a read protected zone. For example, zone 305-a can be a read protected zone and can be associated with or correspond to key 310-a. Key 310-a can be associated with a host system or host entity (e.g., reference...). Figure 2 The key associated with the described host system 105-a or host entity 210. In some cases, different host entities may use different keys. For example, a first host entity may be authorized to access the read protection zone 305-a, and therefore, the first host entity may use key 310-a when accessing the read protection zone 305-a. Alternatively, a second host entity may be authorized to access the read protection zone 305-b, and therefore, the second host entity may use key 310-b when accessing the read protection zone 305-b.

[0069] In some instances, multiple host entities may be authorized to access the same area 305, such as read protection area 305-c. In such instances, a read protection area may be associated with multiple keys, such as key 310-c associated with a first host entity authorized to access read protection area 305-c, and key 310-d associated with a second host entity authorized to access read protection area 305-c. In some cases, a single host entity may be associated with or use multiple keys 310, and therefore may be authorized to access multiple read protection areas of the memory system.

[0070] In some cases, the host system and the memory system may use one or more symmetric key pairs. In such cases, both the host system and the memory system can store the shared key 310. For example, if the host entity is authorized to access the read protection zone 305-a, the host system can store key 310-a in key storage device 215. Therefore, the memory system can also store key 310-a in key storage device 250. In some cases, the memory system can associate key 310-a with the host entity, for example, in public key table 260, so that the memory system can verify commands sent from the host system.

[0071] Alternatively, the host system and the memory system may use asymmetric key pairs. In such cases, the host system may store the private key associated with the read protection zone, while the memory system may store the host system's public key. For example, if a host entity is authorized to access read protection zone 305-a, the host system may store the private key associated with read protection zone 305-a in key storage device 215 and transfer the corresponding public key to the memory system. Therefore, the memory system may store the public key in key storage device 250. In some cases, key 310-a may be a public key received from the host system.

[0072] Using this example, a host entity can request data stored in read protection zone 305-a by the memory system. Therefore, the host system can generate a read command 315 to access the data. The host system can sign or encrypt the read command 315 using a key associated with read protection zone 305-a (e.g., a shared key or a private key corresponding to a public key) (e.g., a key associated with the requesting host entity). In some cases, signing the read command 315 may involve performing a hashing process to generate a hash (e.g., a hash digest) using the key associated with read protection zone 305-a and the read command 315. In some cases, the host system's signature may be a hash or the result of a hashing process. In some cases, the host system may transmit the read command 315 and the signature to the memory system.

[0073] The memory system can receive a read command 315 and a signature from the host system. In some cases, the memory system can verify or authenticate the read command 315 and the signature to determine whether the host entity is authorized to access the read protection zone 305-a. For example, the memory system can perform a hashing process to generate a hash using the received read command 315 and key 310-a. If the hash generated by the memory system matches the signature transmitted by the host system, the memory system can determine that the host entity is authorized to access the read protection zone. Therefore, the memory system can retrieve data from the read protection zone 305-a and transfer the data to the host system. In some cases, the memory system can retrieve data without removing the read protection state of the read protection zone 305-a (e.g., the read operation may be atomic).

[0074] In some cases, the host system may request the memory system to sign the data associated with read command 315. For example, the host system may transmit additional commands or instructions along with read command 315 to request signed data. In such cases, upon receiving the read command, the memory system may perform a hashing process to generate a hash using a key associated with the memory system (e.g., the memory system's private key or a shared key between the host system and the memory system) and the retrieved data. The memory system may transmit the hash along with the data to the host system in response to read command 315. The signature of the memory device may be the generated hash. The host system can verify or authenticate the data by performing the hashing process using a key associated with the host system (e.g., the host system's private key or a shared key between the host system and the memory system) and the received data. If the result of the hashing process matches the received signature, the host system can determine that the data was received from the memory system (e.g., the host system can determine that the data was not received from a separate or different memory system).

[0075] In some cases, the host entity requesting data may not be authorized to access the read protection zone. For example, the host entity may be authorized to access data associated with key 310-b instead of key 310-a. In such cases, read command 315 can be signed using key 310-b. Therefore, after the memory system receives read command 315 and the signature, the memory system can determine that the signature generated using key 310-a does not match the received signature. Therefore, the memory system can return an indication that the host system is not authorized to access the read protection zone 305-a. In some cases, the indication may contain blank data (e.g., all zeros) or other invalid (e.g., garbage) data. In some instances (e.g., if the host system has requested the memory system to sign the data), the memory system can generate a signature for the requested data using the key associated with the memory system and transmit the signature to the host entity without transmitting the data to the host entity. Therefore, in some cases, a signature without any associated data can be an indication that the host system is not authorized to access the read protection zone 305-a.

[0076] Figure 4 An example of a process flow 400 supporting authenticated reading of memory system data, as disclosed herein, is shown. Process flow 400 can be implemented by a host system 405 (e.g., using a host system controller) and a memory system 410 (e.g., using a memory system controller), and can be a reference. Figure 1 and 2Examples of the corresponding devices described. Memory system 410 may be an example of an eMMC system. In the following description of process flow 400, operations may be performed in a different order than those shown. For example, specific operations may be omitted from process flow 400, or other operations may be added to process flow 400.

[0077] In some instances, process flow 400 may include generating a public key that can be transmitted between host system 405 and memory system 410, which may be referred to as an asymmetric key or asymmetric public key (e.g., a public key for an asymmetric key pair, and public keys for corresponding private keys of the asymmetric key pair). The generation of such a public key may be based on a private key maintained at the respective system, wherein such private key is not shared outside the respective system. This technique enables host system 405 and memory system 410 to sign various transmitted signaling (e.g., for authenticating the transmission system) or encrypt various transmitted signaling (e.g., for information integrity), or both, without exchanging private identification information unique to each system. Therefore, this technique can improve the authenticity and integrity of communications compared to other techniques that do not perform encryption hardware identification information distribution, or whose distribution may be more easily cloned or stolen (e.g., techniques that distribute symmetric keys in a potentially insecure manner).

[0078] For example, host system 405 can generate a host system public key, which may be at least partially based on the host system private key (e.g., calculated using the host system private key). In various instances, the host system private key may be stored at host system 405, or otherwise generated at the host system using a private identifier such as a fuse configuration, an identity stored in non-volatile memory, the PUF of host system 405, or some other unique identifier of host system 405, which prevents cloning or extraction. In some instances, the host system public key may be associated with a specific address range (e.g., partition 245 or a portion thereof) or memory protection attributes (e.g., read protection, write protection) or a combination thereof at a particular host entity 210 or memory system 410. In some instances, such public key attributes may not be associated with the generated host system public key, but may later be associated with one or more symmetric keys generated at least partially based on the host system public key, or may later be assigned by memory system 110-a.

[0079] In some instances, process flow 400 may include the exchange of one or more keys between host system 405 and memory system 410. For example, at 415, host system 405 may transmit one or more keys associated with a corresponding protected area of ​​memory system 410, which may be received by memory system 410. In some instances (e.g., when host system 405 and memory system 410 are configured to support symmetric keys, encryption, or both), at 420, memory system 410 may transmit one or more public keys for memory system 410, which may be received by host system 405. In some instances, the transmitted public keys may be stored at the corresponding receiving system (e.g., in key storage device 215, in key storage device 250), for example, in a non-volatile storage device of the corresponding receiving system or otherwise communicating with said corresponding receiving system. In some other instances, such transmitted or received public keys may not be stored, but keys generated based on such transmitted or received public keys may be stored after further processing. In some instances, such asymmetric public keys can be updatable, where such updates can be initiated based on timers or events, and subsequently generated updated or alternative asymmetric public keys can be transferred from the generating system to the receiving system accordingly.

[0080] In some instances, process flow 400 may include the generation of a symmetric key by host system 405 and memory system 410, the symmetric key being computed at least in part based on the respective received public key. Such a symmetric key may be generated between the two systems in an equivalent or otherwise equivalent manner (e.g., as a shared secret), or may be used in other ways to enable one system to authenticate information signed with the other, or one system to decode information encoded with the other, or both, while avoiding the transmission of private information. For example, at 425, host system 405 may generate a symmetric key that may be at least in part based on one or more keys transmitted by memory system 410 at 420 and one or more keys of host system 405 (e.g., computed using said keys). Furthermore, at 430, memory system 410 may also generate a symmetric key that may be at least in part based on one or more keys transmitted by host system 405 at 415 and one or more keys of memory system 410 (e.g., computed using said keys). In some instances, such symmetric keys can be generated using Diffie-Hellmann techniques or other exponential key exchange or generation protocols (including elliptic curve techniques). In some instances, the generated symmetric keys can be stored in the generation system (e.g., in key storage device 215, in key storage device 250), for example, in a non-volatile storage device of the respective generation system or otherwise communicating with said respective generation system.

[0081] Process flow 400 can describe the transfer of read commands from host system 405 to memory system 410 to access data stored in one or more protected areas of memory system 410. For example, at 435, the commands can be signed. For example, host system 405 can generate access to read protected areas stored in memory system 410 (e.g., refer to...). Figure 3 The description includes a signature command for data in the read protection zone 305, such as a read command. In some cases, generating a signature command may involve performing a hash process using a key associated with the read protection zone of memory system 410 and the read command, and including the signature in the command. Therefore, a signature command may include an access command (e.g., a command to read data stored in memory system 410) and a signature generated using a hash process.

[0082] At 440, the signing command can be transmitted to the memory system 410. For example, the host system 405 can transmit the signing command to the memory system 410. In some instances, the host system 405 can also transmit an indication that the signing command has been signed to the memory system 410. For example, the host system 405 can adjust the state of the channel between the host system 405 and the memory system 410 to indicate that the signing command has been signed.

[0083] At 445, the signature command can be authenticated. For example, memory system 410 can use the included signature to authenticate the signature command. In some cases, authenticating the signature command may involve performing a hashing process, or using a key associated with the read protection zone of memory system 410 to transform the signature contained in the signature command to determine the identity of host system 405. In some cases, the identity of host system 405 may include an indication of the host entity that initiated the read command, such as a reference. Figure 2 The host entity 210 is described.

[0084] In some cases, the key associated with the read-protected area of ​​the memory system may be stored in the host system 405 (e.g., stored in the key storage device 250, see reference 405). Figure 2 The key (described), such as the private key of host system 405, can be paired with the public key of host system 405 (e.g., the private key and public key can be part of an asymmetric key pair). The host system can, for example, refer to... Figure 2 The described virtual authentication channel 205 transmits the public key to the memory system 410. In this case, the host system 405 can encrypt the read command using its private key at 475. Therefore, the memory system 410 can authenticate the read command using the host system 405's public key at 445.

[0085] Alternatively or concurrently, the key is stored in the host system 405 (e.g., stored in the key storage device 250, see reference). Figure 2 The key associated with the read protection zone of the shared key (described) can be shared with the key of memory system 410 (e.g., the key of host system 405 and the key of memory system 410 can be part of a symmetric key pair). The host system can, for example, refer to... Figure 2 The described virtual authentication channel 205 transmits a shared key to the memory system 410. In this case, the host system 405 can encrypt read commands using the shared key at 440. Therefore, the memory system 410 can authenticate read commands using the shared key at 445.

[0086] At 450, it can be determined whether host system 405 is authorized to access the read-protected area of ​​memory system 410. For example, memory system 410 can determine whether the signature of a signature command matches the signature generated by the hashing process performed at 455. If the received signature matches the generated signature, memory system 410 can determine that host system 405 is authorized to access data stored in the read-protected area. In such a case, memory system 410 can retrieve the data requested in the read-protected area from the read-protected area and can transmit a response containing said data to host system 405 at 455.

[0087] Alternatively, at 450, the memory system may determine that the signature of the received signing command does not match the signature generated using the hashing process performed at 445. For example, the read command may have been signed using a key associated with a different read protection zone (e.g., a second read protection zone). In such a case, the memory system 410 may transmit a response at 460 to the host system 405 indicating that the host system 405 may not have been authorized to access the data.

[0088] In some cases, the signing command may include a command for the memory system 410 to sign the data associated with the signing command. In this case, the response may be signed at 455. For example, the memory system 410 may generate a signature using the data and a key associated with the memory system 410 (e.g., the memory system 410's private key, or a shared key between the host system 405 and the memory system 410). In some cases, the signature may be included in the response and transmitted to the host system at 470. In some cases, if the memory system 410 has determined that the host system 405 may not be authorized to access the data, the response may include a signature generated using a key associated with the read protection zone.

[0089] Therefore, at 465, the response can be authenticated. For example, host system 405 can use a key of host system 405 to decrypt or otherwise transform the signature contained in the response, such as host system 405's private key, a shared key between host system 405 and memory system 410, or a key associated with a read-protected area. By decrypting the response, host system 405 can determine the source of the data (e.g., host system 405 can determine whether the data originated from memory system 410).

[0090] In some cases, host system 405 can update the key associated with the read protection zone. For example, host system 405 can generate a second key associated with the read protection zone of memory system 410 and transmit the second key to memory system 410. Therefore, memory system 410 can, for example, update the reference... Figure 2 The described key storage device 250, public key table 260, or both update the key associated with the read protection zone. In some cases, the host system 405 may update the key associated with the read protection zone after a period of time (e.g., an encryption cycle).

[0091] In some cases, one or more read protection zones of memory system 410 may be updated. For example, memory system 410 may adjust the size of one or more read protection zones, for instance, by including more or fewer memory cells in the adjusted read protection zone. Alternatively, memory system 410 may adjust the address range of one or more read protection zones. For example, as part of adjusting a read protection zone from a first address range to a second address range, memory system 410 may transfer data stored in the first address range (e.g., read protection data) to the second address range. In some cases, the updated read protection zone may be associated with the same key before and after the update. In some cases, host system 405 may transmit a command to memory system 410 to update one or more read protection zones.

[0092] Various aspects of process flow 400 may be implemented by a controller and other components. Alternatively, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to memory system 410, host system 405, or both). For example, when executed by the controller, the instructions may cause the controller to perform the operations of process flow 400.

[0093] Figure 5 A block diagram 500 illustrates a host device 520 supporting authenticated reading of memory system data according to an example disclosed herein. The host device 520 may be a reference... Figures 1 to 4Examples of various aspects of the described host device. Host device 520 or its various components may be examples of the various aspects of the components described herein for performing authenticated readings of memory system data. For example, host device 520 may include key transmission component 525, signaling transmission component 530, response receiving component 535, key receiving component 540, key management component 545, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0094] Key transmission component 525 may be configured or otherwise support components for performing the following operations: transmitting one or more keys associated with the host system to the memory system, wherein each of the one or more transmitted keys is associated with a corresponding protected area among one or more protected areas at the memory system. Signaling transmission component 530 may be configured or otherwise support components for performing the following operations: transmitting a signed command from the host system to the memory system to read data from a first protected area among one or more protected areas, wherein the signed command is signed at least in part based on a pairing key corresponding to a first transmitted key among the one or more transmitted keys, and wherein the first protected area is associated with the first transmitted key associated with the host system. Response receiving component 535 may be configured or otherwise support components for performing the following operations: receiving data from the memory system at least in part based on the transmitted signed command.

[0095] In some instances, the key receiving component 540 may be configured or otherwise support components for performing the following operations: receiving at a host system one or more public keys associated with a memory system, wherein the paired keys contain a private key associated with the host system; each of the one or more received public keys associated with the memory system corresponds to a corresponding private key associated with the memory system and is different from each of the one or more transmitted keys associated with the host system; and the signing command is further signed at least in part based on the first received public key among the one or more received public keys associated with the memory system.

[0096] In some instances, the key management component 545 may be configured or otherwise support a component for performing the following operations: generating a symmetric key based at least in part on a private key associated with a host system and a first received public key associated with a memory system, wherein a signing command is signed at least in part on the generated symmetric key.

[0097] In some instances, the signaling transport component 530 may be configured or otherwise support components for performing the following operation: transmitting an indication that a signed command has been signed from the host system to the memory system.

[0098] In some instances, the response receiving component 535 may be configured or otherwise supported to perform the following operations: receive a signature of the memory system associated with data from the memory system. In some instances, the response receiving component 535 may be configured or otherwise supported to perform the following operations: determine whether data has been received from the memory system based at least in part on the received signature of the memory system.

[0099] In some instances, the signature of a memory system is at least in part based on a key associated with the memory system.

[0100] In some instances, the key associated with the memory system includes a private key associated with the memory system. In some instances, determining whether data has been received from the memory system is further based, at least in part, on a public key corresponding to the private key associated with the memory system.

[0101] In some instances, signaling transmission component 530 may be configured or otherwise supported to perform the following operation: transmitting from the host system to the memory system a second signed command to read second data from a second protected area in one or more protected areas at the memory system, wherein the second signed command is signed at least in part based on a pairing key corresponding to a first transmitted key associated with the host system. In some instances, response receiving component 535 may be configured or otherwise supported to perform the following operation: receiving from the memory system an indication that the host system is not authorized to access the second protected area, at least in part based on the second signed command.

[0102] In some instances, in order to support an indication that the receiving host system is not authorized to access the second protected area, the response receiving component 535 may be configured or otherwise supported to receive a signature based at least in part on the second data and, in the event that the second data is not received.

[0103] In some instances, signaling transmission component 530 may be configured or otherwise supported to perform the following operation: transmitting an unsigned command from the host system to the memory system to read second data from a first protected area at the memory system. In some instances, response receiving component 535 may be configured or otherwise supported to perform the following operation: receiving from the memory system an indication that the host system is not authorized to access the first protected area, at least in part based on the unsigned command.

[0104] In some instances, the key management component 545 may be configured or otherwise supported to generate an updated key associated with the host system and used to associate with a first protected area at the memory system after transmitting a signature command. In some instances, the key transmission component 525 may be configured or otherwise supported to transmit the updated key to the memory system. In some instances, the signaling transmission component 530 may be configured or otherwise supported to transmit a second signature command from the host system to the memory system to read second data from the first protected area, wherein the second signature command is at least partially based on a second pairing key corresponding to the updated key. In some instances, the response receiving component 535 may be configured or otherwise supported to receive second data from the memory system at least partially based on the transmission of the second signature command.

[0105] In some instances, the updated key is transmitted at least in part based on the time elapsed since the first transmitted key being transmitted meeting a threshold.

[0106] In some instances, the signaling transmission component 530 may be configured or otherwise support components for performing the following operations: transmitting to the memory system an indication of the size of a first protected area, an address range corresponding to the first protected area, or any combination thereof.

[0107] Figure 6 A block diagram 600 illustrates a memory device 620 supporting authenticated reading of memory system data according to an example disclosed herein. The memory device 620 may be a reference... Figures 1 to 4 Examples of various aspects of the described memory device. Memory device 620 or its various components may be examples of the various aspects of the components described herein for performing authenticated readings of data in a memory system. For example, memory device 620 may include a key receiving component 625, a signaling receiving component 630, a key management component 635, a response transmission component 640, a key transmission component 645, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0108] Key receiving component 625 may be configured or otherwise supported to perform the following operations: receiving, at the memory system, one or more keys associated with the host system, wherein each of the one or more received keys corresponds to a corresponding paired key associated with the host system, and is associated with a corresponding protected area among one or more protected areas at the memory system. Signaling receiving component 630 may be configured or otherwise supported to perform the following operations: receiving, at the memory system, a signed command to read data from a first protected area among one or more protected areas, wherein the first protected area is associated with a first received key among one or more received keys. Key management component 635 may be configured or otherwise supported to perform the following operations: determining whether to read data from the first protected area based at least in part on the signature of an attempt to decrypt the signed command, wherein the attempt to decrypt the signature is at least in part based on the first received key associated with the host system. Response transmission component 640 may be configured or otherwise supported to perform the following operations: transmitting data to the host system based at least in part on the successful decryption of the signed command.

[0109] In some instances, the key transmission component 645 may be configured or otherwise support a component for performing the following operations: transmitting to a host system one or more public keys associated with a memory system, wherein each of the one or more transmitted public keys associated with the memory system corresponds to a corresponding private key associated with the memory system and is different from each of the one or more received keys associated with the host system; and attempting to decrypt the signature of a signature command is further based at least in part on a first private key associated with the memory system.

[0110] In some instances, the key management component 635 may be configured or otherwise support a component for performing the following operations: generating a symmetric key based at least in part on a first received key associated with a host system and a first private key associated with a memory system, wherein the signature of an attempt to decrypt a signature command is based at least in part on the generated symmetric key.

[0111] In some instances, the signaling receiving component 630 may be configured or otherwise supported to perform the following operation: receiving an indication that a signed command has been signed.

[0112] In some instances, the response transmission component 640 may be configured or otherwise support components for performing the following operations: transmitting a signature of a memory system associated with data, the signature being at least in part based on a key associated with the memory system.

[0113] In some instances, the signaling receiving component 630 may be configured or otherwise supported to perform the following operations: receiving at the memory system a second signed command to read second data from a second protected area in one or more protected areas at the memory system, wherein the second signed command is signed at least in part based on a pairing key corresponding to a first received key associated with the host system. In some instances, the key management component 635 may be configured or otherwise supported to perform the following operations: determining whether to read data from the second protected area based at least in part on the signature of an attempt to decrypt the second signed command, the signature of which is at least in part based on the first received key associated with the host system. In some instances, the response transmission component 640 may be configured or otherwise supported to perform the following operations: transmitting to the host system an indication that the host system is not authorized to access the second protected area, based at least in part on the second signed command.

[0114] In some instances, the signaling receiving component 630 may be configured or otherwise supported to perform the following operation: receiving at the memory system an unsigned command to read second data from a first protected area at the memory system. In some instances, the response transmission component 640 may be configured or otherwise supported to perform the following operation: transmitting to the host system, at least in part, an indication that the host system is not authorized to access the first protected area, based on the unsigned command.

[0115] In some instances, the key management component 635 may be configured or otherwise support components for performing the following operations: storing at a memory system each of one or more received keys associated with the host system, an indication of the corresponding protected area associated with each of one or more received keys associated with the host system, or any combination thereof.

[0116] In some instances, the signaling receiving component 630 may be configured or otherwise supported to perform the following operations: receiving from the host system an indication of the size of a first protected area, an address range corresponding to the first protected area, or any combination thereof.

[0117] In some instances, the storage system includes eMMC devices, UFS devices, SD devices, SSDs, or any combination thereof.

[0118] Figure 7 A flowchart is shown illustrating a method 700 for authenticated reading of memory system data according to an example disclosed herein. Operation of method 700 can be implemented by a host device or its components described herein. For example, operation of method 700 can be performed by a reference... Figures 1 to 5The described host device performs the function. In some instances, the host device may execute an instruction set to control the functional elements of the device, thereby performing the described function. Alternatively, the host device may use dedicated hardware to perform aspects of the described function.

[0119] In 705, the method may include transmitting one or more keys associated with the host system to the memory system, wherein each of the one or more transmitted keys is associated with a corresponding protected area in one or more protected areas at the memory system. Operation of 705 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 705 may be derived from references... Figure 5 The described key transfer component 525 is used to perform this.

[0120] In 710, the method may include transmitting a signed command from a host system to a memory system to read data from a first protected area among one or more protected areas, wherein the signed command is signed at least in part based on a pairing key corresponding to a first transmitted key among one or more transmitted keys, and wherein the first protected area is associated with the first transmitted key associated with the host system. The operation of 710 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 710 may be derived from references... Figure 5 The signaling transmission component 530 described is used to perform this.

[0121] At 715, the method may include receiving data from a memory system based at least in part on a transmission signature command. The operation of 715 can be performed according to the examples disclosed herein. In some instances, aspects of the operation of 715 can be derived from references... Figure 5 The response receiving component 535 described is used to perform this action.

[0122] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0123] Aspect 1: The device includes features, circuitry, logic, components, or instructions, or any combination thereof, for performing the following: (e.g., from a host system to a memory system) transmitting one or more keys associated with the host system, wherein each of the one or more transmitted keys is associated with a corresponding protected area among one or more protected areas at the memory system; (e.g., from the host system to the memory system) transmitting a signed command to read data from a first protected area among one or more protected areas, wherein the signed command is signed at least in part based on a pairing key corresponding to a first transmitted key among one or more transmitted keys, and wherein the first protected area is associated with the first transmitted key associated with the host system; and (e.g., from the memory system) receiving data at least in part based on transmitting the signed command.

[0124] Aspect 2: The device according to aspect 1 further includes an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing: receiving one or more public keys associated with a memory system at a host system, wherein the pairing key contains a private key associated with the host system; each of the one or more received public keys associated with the memory system corresponds to a corresponding private key associated with the memory system and is different from each of the one or more transmitted keys associated with the host system; and the signing command is further signed at least in part based on the first received public key among the one or more received public keys associated with the memory system.

[0125] Aspect 3: The device according to aspect 2 further includes an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing the following: generating a symmetric key based at least in part on a private key associated with a host system and a first received public key associated with a memory system, wherein a signing command is signed at least in part based on the generated symmetric key.

[0126] Aspect 4: The apparatus according to any one of aspects 1 to 3 further includes an operation, feature, circuit, logic, component or instruction or any combination thereof for performing an indication that a signature command has been signed (e.g., from a host system to a memory system).

[0127] Aspect 5: The apparatus according to any one of aspects 1 to 4, wherein the signature command instructs the memory system to transmit a signature of the memory system associated with data, further comprising an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing: (e.g., from the memory system) receiving a signature of the memory system associated with data; and determining, at least in part, whether data has been received from the memory system based on the received signature of the memory system.

[0128] Aspect 6: The device according to aspect 5, wherein the signature of the memory system is at least in part based on a key associated with the memory system.

[0129] Aspect 7: The device according to aspect 6, wherein the key associated with the memory system is a private key associated with the memory system, and determining whether data has been received from the memory system is further based at least in part on a public key corresponding to the private key associated with the memory system.

[0130] Aspect 8: The apparatus according to any one of aspects 1 to 7 further comprises an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing: (e.g., from a host system to a memory system) transmitting a second signed command to read second data from a second protected area in one or more protected areas at the memory system, wherein the second signed command is signed at least in part based on a pairing key corresponding to a first transmitted key associated with the host system; and receiving (e.g., from the memory system) an indication that the host system is not authorized to access the second protected area, at least in part based on the second signed command.

[0131] Aspect 9: The device according to aspect 8, wherein the operation, feature, circuit, logic, component, or instruction or any combination thereof for the instruction to receive a host system that is not authorized to access the second protected area includes an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing the following: receiving a signature based at least in part on second data and a second key associated with the second protected area in the absence of receiving the second data.

[0132] Aspect 10: The apparatus according to any one of aspects 1 to 9 further includes an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing: (e.g., from a host system to a memory system) transmitting an unsigned command to read second data from a first protected area at the memory system; and receiving, at least in part based on the unsigned command (e.g., from the memory system), an indication that the host system is not authorized to access the first protected area.

[0133] Aspect 11: The apparatus according to any one of aspects 1 to 10 further includes operations, features, circuits, logic, components, or instructions or any combination thereof for performing: generating an updated key associated with a host system and for association with a first protected area at a memory system after transmitting a signature command; transmitting the updated key to (e.g., the memory system); transmitting a second signature command (e.g., from the host system to the memory system) to read second data from the first protected area, wherein the second signature command is at least partially based on a second pairing key corresponding to the updated key; and receiving second data at least partially based on transmitting the second signature command (e.g., from the memory system).

[0134] Aspect 12: The device according to aspect 11 further includes an operation, feature, circuit, logic, component or instruction or any combination thereof for performing the following: transmitting an updated key based at least in part on a threshold being met since the time elapsed since the transmission of the first transmitted key.

[0135] Aspect 13: The apparatus according to any one of aspects 1 to 12 further includes an operation, feature, circuit, logic, component or instruction or any combination thereof for performing the following: (e.g., to a memory system) transmitting an indication of the size of a first protected area, an address range corresponding to the first protected area, or any combination thereof.

[0136] Figure 8 A flowchart is shown illustrating a method 800 for authenticated reading of memory system data according to an example disclosed herein. Operation of method 800 can be implemented by a memory device or its components described herein. For example, operation of method 800 can be provided by reference to... Figures 1 to 4 The memory device described in section 6 performs the functions described herein. In some instances, the memory device may execute an instruction set to control the functional elements of the device, thereby performing the functions described herein. Alternatively, the memory device may use dedicated hardware to perform aspects of the functions described herein.

[0137] In 805, the method may include: receiving, at a memory system, one or more keys associated with a host system, wherein each of the one or more received keys corresponds to a corresponding pairing key associated with the host system, and for association with a corresponding protected area in one or more protected areas at the memory system. Operation of 805 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 805 may be derived from references... Figure 6 The described key receiving component 625 performs this action.

[0138] In 810, the method may include: receiving at a memory system a signed command to read data from a first protected area among one or more protected areas, wherein the first protected area is associated with a first received key among one or more received keys. The operation of 810 can be performed according to the examples disclosed herein. In some examples, aspects of the operation of 810 may be derived from references... Figure 6 The signaling receiving component 630 described is used to perform this action.

[0139] In 815, the method may include: determining whether to read data from a first protected area based at least in part on the signature of an attempt to decrypt a signature command, wherein the attempt to decrypt the signature is based at least in part on a first received key associated with the host system. The operation of 815 can be performed according to the examples disclosed herein. In some instances, aspects of the operation of 815 may be derived from references... Figure 6 The described key management component 635 is used to perform this.

[0140] In 820, the method may include: transmitting data to a host system based at least in part on the successful decryption of a signature command. The operation of 820 can be performed according to the examples disclosed herein. In some instances, aspects of the operation of 820 can be derived from references... Figure 6 The described response transmission component 640 is used to perform this.

[0141] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0142] Aspect 14: The device includes features, circuitry, logic, components, or instructions or any combination thereof for performing the following: (e.g., from a host system at a memory system) receiving one or more keys associated with the host system, wherein each of the one or more received keys corresponds to a corresponding paired key associated with the host system, and for association with a corresponding protected area among one or more protected areas at the memory system; (e.g., at the memory system) receiving a signed command to read data from a first protected area among one or more protected areas, wherein the first protected area is associated with a first received key among one or more received keys; determining whether to read data from the first protected area based at least in part on a signature of an attempt to decrypt the signed command, wherein the attempt to decrypt the signature is based at least in part on the first received key associated with the host system; and (e.g., to the host system) transmitting data based at least in part on a signature of a successfully decrypted signed command.

[0143] Aspect 15: The device according to aspect 14 further includes an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing: (e.g., to a host system) transmitting one or more public keys associated with a memory system, wherein each of the one or more transmitted public keys associated with the memory system corresponds to a corresponding private key associated with the memory system and is different from each of the one or more received keys associated with the host system; and attempting to decrypt the signature of a signature command is further based at least in part on a first private key associated with the memory system.

[0144] Aspect 16: The apparatus according to aspect 15 further includes an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing the following: generating a symmetric key based at least in part on a first received key associated with a host system and a first private key associated with a memory system, wherein an attempt to decrypt a signature of a signature command is based at least in part on the generated symmetric key.

[0145] Aspect 17: The apparatus according to any one of aspects 14 to 16 further includes an operation, feature, circuit, logic, component or instruction or any combination thereof for performing an indication that a signature command has been signed.

[0146] Aspect 18: The apparatus according to any one of aspects 14 to 17 further includes an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing the following: transferring a signature of a memory system in association with data, the signature being at least in part based on a key associated with the memory system.

[0147] Aspect 19: The apparatus according to any one of aspects 14 to 18 further comprises an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing: (e.g., in a memory system) receiving a second signed command to read second data from a second protected area in one or more protected areas at the memory system, wherein the second signed command is signed at least in part based on a pairing key corresponding to a first received key associated with a host system; determining whether to read data from the second protected area based at least in part on an attempt to decrypt the signature of the second signed command, the attempt to decrypt the signature of the second signed command being at least in part based on the first received key associated with the host system; and transmitting (e.g., to the host system) an indication that the host system is not authorized to access the second protected area based at least in part on the second signed command.

[0148] Aspect 20: The apparatus according to any one of aspects 14 to 19 further includes an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing: (e.g., at a memory system) receiving an unsigned command to read second data from a first protected area at a memory system; and transmitting, at least in part, an indication (e.g., to a host system) that the host system is not authorized to access the first protected area based on the unsigned command.

[0149] Aspect 21: The apparatus according to any one of aspects 14 to 20 further includes an operation, feature, circuit, logic, component, or instruction or any combination thereof for performing the following: storing at a memory system each of one or more received keys associated with a host system, an instruction for a corresponding protected area associated with each of one or more received keys associated with a host system, or any combination thereof.

[0150] Aspect 22: The device according to any one of aspects 14 to 21 further includes an operation, feature, circuit, logic, component or instruction or any combination thereof for performing the following: (e.g., from a host system) receiving an indication of the size of a first protected area, an address range corresponding to the first protected area, or any combination thereof.

[0151] Aspect 23: The device according to any one of aspects 14 to 22, wherein the memory system includes an eMMC device, a UFS device, an SD device, an SSD, or any combination thereof.

[0152] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0153] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, signals may represent buses of signals, which may have various bit widths.

[0154] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0155] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0156] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0157] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0158] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0159] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0160] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, such as degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0161] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0162] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral distinguishing them from each other. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0163] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0164] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0165] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0166] Computer-readable media includes both non-transitory computer-readable storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then those coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of these are also included within the scope of computer-readable media.

[0167] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A controller configured to be coupled to a memory system, wherein the controller is configured to cause the device to perform the following operations: Transmit one or more keys associated with the host system, wherein each of the one or more transmitted keys is used to be associated with a corresponding protected area in one or more protected areas at the memory system; A signature command for reading data from a first protected area among the one or more protected areas, wherein the signature command is signed at least in part based on a pairing key corresponding to a first transmitted key among the one or more transmitted keys, wherein the signature command includes an access command and a signature generated using a function that receives the pairing key and the access command as input, wherein the access command indicates an access operation to be performed at the memory system, and wherein the first protected area is associated with the first transmitted key associated with the host system; The data is received at least in part based on the transmission of the signature command; and The transmission command adjusts the first protected area from a first size to a second size and / or from a first address range to a second address range, wherein the first protected area before and after adjustment is associated with the first transmitted key.

2. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: Receive one or more public keys associated with the memory system at the host system, wherein: The pairing key includes a private key associated with the host system; Each of the one or more received public keys associated with the memory system corresponds to a corresponding private key associated with the memory system, and is different from each of the one or more transmitted keys associated with the host system; and The signing command is further signed based at least in part on a first received public key among the one or more received public keys associated with the memory system.

3. The device of claim 2, wherein the controller is further configured to cause the device to perform the following operations: A symmetric key is generated at least in part based on the private key associated with the host system and the first received public key associated with the memory system, wherein the signing command is signed at least in part based on the generated symmetric key.

4. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The transmission indicates that the signature command has been signed.

5. The device of claim 1, wherein the signature command instructs the memory system to transmit a signature of the memory system associated with the data, and wherein the controller is further configured to cause the device to perform the following operations: Receive the signature of the memory system associated with the data; and Whether the data was received from the memory system is determined at least in part based on the signature received by the memory system.

6. The device of claim 5, wherein the signature of the memory system is at least in part based on a key associated with the memory system.

7. The device according to claim 6, wherein: The key associated with the memory system includes a private key associated with the memory system, and Determining whether the data has been received from the memory system is further based, at least in part, on the public key corresponding to the private key associated with the memory system.

8. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: A second signed command is transmitted to read second data from a second protected area in one or more protected areas at the memory system, wherein the second signed command is signed at least in part based on the pairing key corresponding to the first transmitted key associated with the host system; and The host system receives an instruction that it is not authorized to access the second protected area, at least in part based on the second signature command.

9. The device of claim 8, wherein, in order to receive the indication that the host system has not been authorized to access the second protected area, the controller is configured to cause the device to perform the following operations: The signature is received at least in part based on the second data and, in the event that the second data is not received, a second key associated with the second protected area.

10. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: Transmit an unsigned command to read second data from the first protected area at the memory system; and; The host system receives an instruction that it is not authorized to access the first protected area, at least in part based on the unsigned command.

11. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: After transmitting the signature command, an updated key is generated that is associated with the host system and used to associate with the first protected area at the memory system; Transmit the updated key; Transmit a second signature command to read second data from the first protected area, wherein the second signature command is at least partially based on a second pairing key corresponding to the updated key; and The second data is received at least in part based on the transmission of the second signature command.

12. The device of claim 11, wherein the controller is configured to cause the device to perform the following operations: The updated key is transmitted at least in part based on the time elapsed since the first transmitted key was transmitted meeting a threshold.

13. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: Transmit an indication of the size of the first protected area, an address range corresponding to the first protected area, or any combination thereof.

14. An apparatus comprising: Memory system; as well as A controller, used in the memory system and configured to cause the device to perform the following operations: Receive one or more keys associated with a host system, wherein each of the one or more received keys corresponds to a corresponding pairing key associated with the host system, and is used to associate with a corresponding protected area in one or more protected areas at the memory system; A signed command is received to read data from a first protected area among the one or more protected areas, wherein the signed command includes an access command and a signature generated using a function that receives the corresponding pairing key and the access command as input, wherein the access command indicates an access operation to be performed at the memory system, and wherein the first protected area is associated with a first received key among the one or more received keys. Whether to read the data from the first protected area is determined at least in part based on an attempt to decrypt the signature, wherein the attempt to decrypt the signature is at least in part based on the first received key associated with the host system; The data is transmitted at least in part based on the successful decryption of the signature of the signature command; and A command is received to adjust the first protected area from a first size to a second size and / or to adjust the first protected area from a first address range to a second address range, wherein the first protected area before and after adjustment is associated with the first received key.

15. The device of claim 14, wherein the controller is further configured to cause the device to perform the following operations: Transmit one or more public keys associated with the memory system, wherein: Each of the one or more transmitted public keys associated with the memory system corresponds to a corresponding private key associated with the memory system, and is different from each of the one or more received keys associated with the host system; and The signature of the attempt to decrypt the signature command is further based, at least in part, on a first private key associated with the memory system.

16. The device of claim 15, wherein the controller is further configured to cause the device to perform the following operations: A symmetric key is generated at least in part based on the first received key associated with the host system and the first private key associated with the memory system, wherein the signature of the attempt to decrypt the signature command is at least in part based on the generated symmetric key.

17. The device of claim 14, wherein the controller is further configured to cause the device to perform the following operations: Receive an indication that the signature command has been signed.

18. The device of claim 14, wherein the controller is further configured to cause the device to perform the following operations: A signature of the memory system is transmitted in association with the data, the signature being at least in part based on a key associated with the memory system.

19. The device of claim 14, wherein the controller is further configured to cause the device to perform the following operations: Receive a second signature command to read second data from a second protected area in one or more protected areas at the memory system, wherein the second signature command is signed at least in part based on a pairing key corresponding to the first received key associated with the host system; Whether to read the data from the second protected area is determined at least in part based on an attempt to decrypt the signature of the second signature command, the attempt to decrypt the signature of the second signature command being at least in part based on the first received key associated with the host system; as well as The instruction that the host system is not authorized to access the second protected area is transmitted, at least in part based on the second signature command.

20. The device of claim 14, wherein the controller is further configured to cause the device to perform the following operations: Receive an unsigned command to read second data from the first protected area at the memory system; and; The instruction that the host system is not authorized to access the first protected area is transmitted, at least in part based on the unsigned command.

21. The device of claim 14, wherein the controller is further configured to cause the device to perform the following operations: The memory system stores an indication of each of the one or more received keys associated with the host system, an indication of the corresponding protected area associated with each of the one or more received keys associated with the host system, or any combination thereof.

22. The device of claim 14, wherein the controller is further configured to cause the device to perform the following operations: Receive an indication of the size of the first protected area, an address range corresponding to the first protected area, or any combination thereof.

23. The device of claim 14, wherein the memory system comprises an embedded multimedia card (eMMC) device, a universal flash storage (UFS) device, a secure digital storage (SD) device, a solid-state drive (SSD), or any combination thereof.

24. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by at least one processor of an electronic device, cause the electronic device to perform the following operations: Transmit one or more keys associated with the host system, wherein each of the one or more transmitted keys is used to associate with a corresponding protected area in one or more protected areas at the memory system; A signature command for reading data from a first protected area among the one or more protected areas, wherein the signature command is signed at least in part based on a pairing key corresponding to a first transmitted key among the one or more transmitted keys, wherein the signature command includes an access command and a signature generated using a function that receives the pairing key and the access command as input, wherein the access command indicates an access operation to be performed at the memory system, and wherein the first protected area is associated with the first transmitted key associated with the host system; The data is received at least in part based on the transmission of the signature command; and The transmission command adjusts the first protected area from a first size to a second size and / or from a first address range to a second address range, wherein the first protected area before and after adjustment is associated with the first transmitted key.

25. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by at least one processor of an electronic device, cause the electronic device to perform the following operations: Receive one or more keys associated with a host system, wherein each of the one or more received keys corresponds to a corresponding pairing key associated with the host system, and is used to associate with a corresponding protected area in one or more protected areas at the memory system; A signed command is received to read data from a first protected area among the one or more protected areas, wherein the signed command includes an access command and a signature generated using a function that receives the corresponding pairing key and the access command as input, wherein the access command indicates an access operation to be performed at the memory system, and wherein the first protected area is associated with a first received key among the one or more received keys. Whether to read the data from the first protected area is determined at least in part based on an attempt to decrypt the signature, wherein the attempt to decrypt the signature is at least in part based on the first received key associated with the host system; The data is transmitted at least in part based on the successful decryption of the signature of the signature command; and A command is received to adjust the first protected area from a first size to a second size and / or to adjust the first protected area from a first address range to a second address range, wherein the first protected area before and after adjustment is associated with the first received key.

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