An efuse module fast read-write verification method and system
By generating a random number array to modify the netlist of the efuse module and verifying it using a simulation testbench, the problem of complex and time-consuming efuse module read/write verification in the existing technology is solved, achieving a fast and comprehensive verification effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU GUILUN ELECTRONIC TECH CO LTD
- Filing Date
- 2022-12-27
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, the read/write verification method of the efuse module is complex, time-consuming, and prone to errors, and cannot fully cover all bytes, resulting in incomplete verification.
By generating a random number array with the same number of rows and columns as the efuse module, modifying the netlist to write random numbers, and using a simulation testbench to perform a full array read operation, the consistency of the written and read data is compared to verify the correctness of the internal logic.
It enables fast and comprehensive efuse module read/write verification, improving verification efficiency and accuracy, shortening the design cycle, and is applicable to different processes and module sizes.
Smart Images
Figure CN116011367B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of chip circuits, and in particular to a fast read / write verification method and system for an efuse module. Background Technology
[0002] Thermal fuses, as a fundamental circuit protection device, have been successfully used for over 150 years. They are effective, reliable, and easy to use, available in various values and versions to meet diverse design goals. However, for designers seeking to interrupt current extremely quickly, the unavoidable drawbacks of thermal fuses are their self-resetting capability and their ability to operate at relatively low currents. For these designers, electronic fuses (usually denoted as eFuse or e-Fuse) are a good solution and can sometimes replace thermal fuses, but are typically used as a supplement to their functionality.
[0003] eFuse is based on a simple concept: detecting current by measuring the voltage across a known resistor, and then cutting off the current via a field-effect transistor (FET) when the current exceeds a design limit. eFuse offers characteristics, flexibility, and functionality that thermal fuses cannot achieve.
[0004] The working principle of a traditional thermal fuse is simple, reliable, and well-known: when the current through the fusible link exceeds the design value, the element is heated sufficiently to melt. This breaks the current path, bringing the current to zero. Depending on the fuse's rating, type, and the magnitude of the overcurrent, a thermal fuse can respond and disconnect the current path within hundreds of milliseconds to a few seconds. Of course, like all active and passive components, even for this simple, purely passive device, there are many variations, details, and shielding options available.
[0005] In contrast, the operating principle of an electronic fuse (eFuse) is quite different. While electronic fuses share some of the same functions, they also add different new features and functionalities. The basic concept of an eFuse is also straightforward: the load current flows through a FET and a sense resistor, and is monitored by the voltage across this sense resistor. When this voltage exceeds a preset value, the control logic disconnects the FET and cuts off the current path. The FET, connected in series with the power supply line and the load, must have very low on-resistance to avoid causing excessive current resistance (IR) drop or power loss.
[0006] Electronic fuses (eFuse) have the following unique properties:
[0007] (1) Speed: Fast response, with a disconnection response time in the microsecond range, and some designs can even reach the nanosecond range. This attribute is very important for circuits that use relatively sensitive ICs and passive components today.
[0008] (2) Low current operation: Electronic fuses can not only be designed to operate at low current (approximately 100 mA or less), but can also operate normally at very low single-digit voltages. At these levels, thermal fuses often cannot obtain sufficient self-heating current to cause their fusible connection to melt.
[0009] (3) Resettable: Depending on the specific model, the eFuse can be selected to remain disconnected after activation (called latch-up mode) or resume normal operation after the current fault disappears (auto-restart mode). The latter setting is particularly useful in the event of transient surge currents without a "hard" fault, such as when the board is plugged into a live bus. It is also useful when replacing fuses is difficult or costly.
[0010] (4) Reverse Current Protection: Electronic fuses can also provide reverse current protection, which thermal fuses cannot. Reverse current occurs when the system output voltage is higher than its input voltage. For example, this can happen when a set of redundant power supplies are connected in parallel.
[0011] (5) Overvoltage protection: With the help of some additional circuitry, eFuse can also provide overvoltage protection to prevent surge or induced tripping, that is, when the input voltage exceeds the set overvoltage tripping point, the FET is disconnected and remains in the off state during the overvoltage condition.
[0012] (6) Reverse polarity protection: eFuse also provides reverse polarity protection, which quickly cuts off the current if the power supply is connected in reverse. For example, a car battery may be briefly reversed due to accidental cable contact.
[0013] (7) Increasing switching rate: Some advanced electronic fuses can also control the switching between the on and off of passive element FETs through external control or the use of fixed components, thereby providing a specified power-off / power-on current switching rate.
[0014] Although eFuse has many advantages mentioned above, read / write verification is required during the front-end design of the eFuse module to ensure the correctness of its internal logic. In existing technologies, read / write verification is generally performed by: (1) manually modifying the schematic of the eFuse module, writing data, and then simulating; (2) manually modifying the eFuse netlist, writing data, and then simulating. However, the disadvantages of these methods are also obvious: modifying the schematic or netlist is complex and time-consuming; manually checking and comparing the written and read data is tedious and prone to errors; when the macro (eFuse module) is large, it cannot cover all bytes, leading to omissions. Summary of the Invention
[0015] To address the aforementioned problems, the present invention aims to provide a fast read / write verification method and system for the efuse module. This method modifies the netlist programmatically, writing a random number array into the efuse macro to ensure that each bit can be written with either 0 or 1, guaranteeing comprehensive coverage. Simultaneously, it can quickly verify the internal logic of the efuse macro by comparing the consistency between the written and read matrices.
[0016] The above-mentioned objective of this invention is achieved through the following technical solutions:
[0017] A fast read / write verification method for the efuse module includes the following steps:
[0018] S1: Obtain the number of rows and columns of an efuse module, and generate a random number array with the same number of rows and columns;
[0019] S2: Modify the netlist of the efuse module and write random numbers into the netlist;
[0020] S3: Generate a simulation testbench with input stimulus that simulates the actual environment, and perform a full array read operation simulation on the efuse module;
[0021] S4: Compare the random number written in the netlist in step S2 with the output data obtained from the simulation in step S3, and perform read and write verification on the efuse module to verify the correctness of the internal logic.
[0022] Further, in step S1, generating the random number array with the same number of rows and columns specifically involves:
[0023] The random number array is set to have a range of values greater than or equal to 0 and less than 2.
[0024] The random number array is assigned a value according to the range of random number values. After the assignment is completed, the random number array is an array with a value of 0 or 1.
[0025] Further, in step S2, the netlist of the efuse module is modified by writing random numbers into the netlist, specifically as follows:
[0026] Iterate through each bit of the row number in the random number array and write 0 or 1 into the netlist row by row;
[0027] Iterate through the line numbers, replacing 0 with the description fuse_pgnfet_in ntact that indicates the circuit has not been broken, and replacing 1 with the description fuse_pgnfet_b l own that indicates the circuit has been broken.
[0028] Further, in step S3, generating a simulation testb ench with input stimulus that simulates the actual environment, and performing a full array read operation simulation on the efuse module, also includes:
[0029] Create a test file for the simulation testbench, and use the test file to simulate and obtain the output of the efuse module.
[0030] Further, in step S4, the random number written in the netlist in step S2 is compared with the output data obtained from the simulation in step S3 to perform read / write verification on the efuse module, thereby verifying the correctness of the internal logic. Specifically:
[0031] Traverse the efuse module by line;
[0032] If the data written in the current row is the same as the simulated output data, then the internal logic of the current row is correct.
[0033] If the data written to the current line is different from the simulated output data, then the internal logic of the current line is incorrect.
[0034] Furthermore, step S4 also includes:
[0035] Output the comparison result between the written data and the simulated output data in the current row;
[0036] When the data written to the current line is the same as the simulated output data, a correct message is output.
[0037] When the data written to the current line is different from the simulated output data, an error message is output, along with the written data and the simulated output data.
[0038] An efuse module fast read / write verification system for executing the efuse module fast read / write verification method as described above includes:
[0039] A random number array generation module is used to obtain the number of rows and columns of an efuse module and generate a random number array with the same number of rows and columns.
[0040] The netlist writing module is used to modify the netlist of the efuse module and write random numbers into the netlist;
[0041] The simulation verification module is used to generate a simulation testbench with input stimulus that simulates the actual environment, and to perform full array read operation simulation on the efuse module.
[0042] The read / write verification module is used to compare the random number written in the netlist in the netlist writing module with the output data obtained from simulation in the simulation verification module to perform read / write verification on the efuse module, thereby verifying the correctness of the internal logic.
[0043] A computer device includes a memory and one or more processors, the memory storing computer code that, when executed by the one or more processors, causes the one or more processors to perform the method described above.
[0044] A computer-readable storage medium storing computer code that, when executed, performs the method described above.
[0045] Compared with the prior art, the present invention has at least one of the following beneficial effects:
[0046] (1) A fast read / write verification method for the efuse module is provided, comprising the following steps: S1: Obtain the number of rows and columns of an efuse module, and generate a random number array with the same number of rows and columns; S2: Modify the netlist of the efuse module and write random numbers into the netlist; S3: Generate a simulation testbench with input stimulus simulating the actual environment, and perform a full array read operation simulation on the efuse module; S4: Compare the random numbers written into the netlist in step S2 with the output data obtained from the simulation in step S3 to perform read / write verification on the efuse module, thereby verifying the correctness of the internal logic. The above technical solution, by using a program to modify the netlist, generate a random number array, and write it into the efuse module, ensures that each bit can be written with 0 or 1, achieving full coverage of the efuse module. By comparing the write matrix and the read matrix of the simulation testbench to verify the internal logic of the efuse module, the check is comprehensive and has high coverage, ensuring that the write and read data of all bits inside the efuse module are checked.
[0047] (2) Improved efficiency of writing and verifying netlists in the efuse module, shortened the design cycle, and only took a few seconds to write random numbers or verify the accuracy of data written and read by the efuse module in the netlist, ensuring the correctness of internal logic.
[0048] (3) The code for writing and verifying the netlist in the efuse module is reusable, highly versatile, applicable to different processes and modules of different sizes, and easy to maintain. Attached Figure Description
[0049] Figure 1 This is a simplified schematic diagram of the eFuse module of the present invention;
[0050] Figure 2 This is an overall flowchart of the fast read / write verification method for the efuse module of the present invention;
[0051] Figure 3 This is an overall structural diagram of the efuse module fast read / write verification system of the present invention. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0053] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0054] like Figure 1 The diagram shown is a simple example of an eFuse module. Before designing the front end of the eFuse module, read / write verification is required to ensure the correctness of the internal logic of the eFuse module. In the existing technology, read / write authentication is generally performed by: (1) manually modifying the schematic of the eFuse module and writing data, and then simulating; (2) manually modifying the eFuse netlist and writing data, and then simulating. However, the disadvantages of the above methods are also obvious: modifying the schematic or the netlist is complicated and time-consuming; manually checking and comparing the written data and read data is tedious and prone to errors; when the macro (eFuse module) is large, it cannot cover all bytes, and omissions are easy to occur.
[0055] This invention proposes a fast read / write verification method and system for the efuse module. By modifying the netlist programmatically, a random number array is written into the efuse macro, ensuring that each bit can be written with either 0 or 1, guaranteeing full coverage. Simultaneously, it can quickly verify the internal logic of the efuse macro by comparing the consistency between the written and read matrices.
[0056] The following is an illustration through specific examples:
[0057] First Embodiment
[0058] like Figure 2 As shown, this embodiment provides a fast read / write verification method for the efuse module, including the following steps:
[0059] S1: Obtain the number of rows and columns of an efuse module, and generate a random number array with the same number of rows and columns.
[0060] Specifically, each efuse module typically exists in the form of a certain number of rows multiplied by a certain number of columns. Therefore, to ensure that every bit is fully covered when assigning values to the efuse module's netlist, a random number array with the same number of rows and columns as the efuse module is generated before writing random numbers to the netlist. By leveraging the fact that the random number array has the same number of rows and columns as the efuse module, when assigning values to the netlist, traversing the random number array can achieve full coverage of every bit in the efuse module.
[0061] For generating a random number array with the same number of rows and columns as the efuse module, a preferred method is to set the range of random number values in the random number array to be greater than or equal to 0 and less than 2; assign values to the random number array according to the range of random number values, and after the assignment is completed, the random number array is an array with values of 0 or 1.
[0062] Furthermore, this embodiment does not impose any restrictions on the method of setting the random number array. For example, the Python `random.random` function can be used to create it. For instance, `list = np.random.random.random(0, 2**row, column)` creates a random number array `list` with rows of rows and columns of columns, using random numbers greater than or equal to 0 and less than 2.
[0063] S2: Modify the netlist of the efuse module and write random numbers into the netlist.
[0064] After the random number array is created, the netlist of the efuse module is modified by the program to write random numbers into the netlist. Specifically, this includes: traversing each bit of the row number of the random number array, writing 0 or 1 into the netlist row by row, and writing the random number at the corresponding position into each row.
[0065] This step also includes creating more clearly defined variables so that users can clearly see whether the current bit has been blown. The steps for creating these clearer variables are: iterate through each bit; replace 0 with the description fuse_pgnfet_intact indicating that the circuit has not been blown, and replace 1 with the description fuse_pgnfet_blown indicating that the circuit has been blown.
[0066] For example, this step can be achieved using the following code:
[0067]
[0068]
[0069] S3: Generate a simulation testbench with input stimuli simulating the actual environment, and perform a full array read operation simulation on the efuse module.
[0070] To simulate the output effect of the efuse module, this embodiment uses a sense mode simulation testbench. A testbench is a verification method. First, every design has inputs and outputs. However, in a software environment, there are no stimulus inputs, and the correctness of your design's output is not evaluated. Therefore, a "virtual platform" that simulates the input stimulus and output verification of a real-world environment is created. On this platform, you can analyze and verify your design at the software level; this is the meaning of a testbench.
[0071] Specifically, by creating a test file for the simulation testbench, the output of the efuse module is obtained through simulation using the test file.
[0072] For example, creating a test file for a simulation testbench can be achieved using the following procedure:
[0073]
[0074]
[0075] S4: Compare the random number written in the netlist in step S2 with the output data obtained from the simulation in step S3, and perform read and write verification on the efuse module to verify the correctness of the internal logic.
[0076] Specifically, the process is traversed line by line in the efuse module; if the written data of the current line is the same as the simulated output data, then the internal logic of the current line is correct; if the written data of the current line is different from the simulated output data, then the internal logic of the current line is incorrect.
[0077] Furthermore, this step also includes: outputting the comparison result between the written data and the simulated output data of the current row; outputting a correct message when the written data and the simulated output data of the current row are the same; outputting an error message when the written data and the simulated output data of the current row are different, and simultaneously outputting the written data and the simulated output data.
[0078] For example, to perform read / write verification on the efuse module and ensure the correctness of its internal logic, the following procedure can be used:
[0079]
[0080] / / When the data written to the current line is different from the simulated output data, output an error message, and simultaneously output the written data and the simulated output data.
[0081] pr i nt("wt"+str(i),"Funct ion Wrong!","Wr ite data"+i nt_data[i],"Read data"+i nput_l i nes[i])
[0082] The above program runs as follows:
[0083] If the read and write operations are the same:
[0084] ('wl0', 'Function pass.')
[0085] ('wl1', 'Function pass.')
[0086] ('wl2', 'Function pass.')
[0087] ('wl3','Function pass.')
[0088] ('wl4','Function pass.')
[0089] ('wl5','Function pass.')
[0090] ('wl6', 'Function pass.')
[0091] ('wl7', 'Function pass.')
[0092] ('wl8', 'Function pass.')
[0093] ('wl9', 'Function pass.')
[0094] ('wl10', 'Function pass.')
[0095] ('wl11', 'Function pass.')
[0096] ('wl12', 'Function pass.')
[0097] ('wl13', 'Function pass.')
[0098] ('wl14', 'Function pass.')
[0099] ('wl15', 'Function pass.')
[0100] ('wl16', 'Function pass.')
[0101] ('wl17', 'Function pass.')
[0102] ('wl18', 'Function pass.')
[0103] If there is a mismatch between reading and writing in a certain line:
[0104] ('wl0', 'Function pass.')
[0105] ('wl1', 'Function pass.')
[0106] ('wl2', 'Function pass.')
[0107] ('wl3', 'Function pass.')
[0108] ('wl4', 'Function pass.')
[0109] ('wl5','Function Wrong!','Write data 00100101',u'Read data 10000001')
[0110] ('wl6','Function pass.')
[0111] ('wl7','Function pass.')
[0112] ('wl8','Function pass.')
[0113] ('wl9','Function pass.')
[0114] ('wl10', 'Function pass.')
[0115] ('wl11', 'Function pass.')
[0116] ('wl12', 'Function pass.')
[0117] ('wl13', 'Function pass.')
[0118] ('wl14','Function pass.')
[0119] ('wl15', 'Function pass.')
[0120] ('wl16','Function pass.')
[0121] ('wl17','Function pass.')
[0122] ('wl18', 'Function pass.')
[0123] Second Embodiment
[0124] like Figure 3 As shown, this embodiment provides an efuse module fast read / write verification system for executing the efuse module fast read / write verification method as described in the first embodiment, comprising:
[0125] Random number array building module 1 is used to obtain the number of rows and columns of an efuse module and generate a random number array with the same number of rows and columns;
[0126] Netlist writing module 2 is used to modify the netlist of the efuse module and write random numbers into the netlist;
[0127] Simulation verification module 3 is used to generate a simulation testbench with input stimulus that simulates the actual environment, and to perform a full array read operation simulation on the efuse module.
[0128] The read / write verification module 4 is used to compare the random number written in the netlist in the netlist writing module with the output data obtained from simulation in the simulation verification module to perform read / write verification on the efuse module, thereby verifying the correctness of the internal logic.
[0129] A computer-readable storage medium stores computer code that, when executed, performs the methods described above. Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. This program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk, etc.
[0130] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.
[0131] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0132] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. An efuse module fast read-write verification method, characterized in that, Includes the following steps: S1: Obtain the number of rows and columns of an efuse module, and generate a random number array with the same number of rows and columns; The random number array is set to have a range of values greater than or equal to 0 and less than 2; the random number array is assigned values according to the range of random number values, and after the assignment is completed, the random number array is an array with values of 0 or 1; S2: Modify the netlist of the efuse module and write random numbers into the netlist; Iterate through each bit of the row number in the random number array and write 0 or 1 into the netlist row by row; Traverse the line numbers; Replace 0 with the description fuse_pgnfet_intact, which indicates that the circuit has not been broken, and replace 1 with the description fuse_pgnfet_blown, which indicates that the circuit has been broken. S3: Generate a simulation testbench with input stimulus that simulates the actual environment, and perform a full array read operation simulation on the efuse module; S4: Compare the random number written in the netlist in step S2 with the output data obtained from the simulation in step S3, and perform read and write verification on the efuse module to verify the correctness of the internal logic.
2. The fast read / write verification method for the efuse module according to claim 1, characterized in that, In step S3, a simulation testbench with input stimuli simulating the actual environment is generated, and a full array read operation simulation is performed on the efuse module. This also includes: Create a test file for the simulation testbench, and use the test file to simulate and obtain the output of the efuse module.
3. The fast read / write verification method for the efuse module according to claim 1, characterized in that, In step S4, the random number written in the netlist in step S2 is compared with the output data obtained from the simulation in step S3 to perform read / write verification on the efuse module, thereby verifying the correctness of the internal logic. Specifically: Traverse the efuse module by line; If the data written in the current row is the same as the simulated output data, then the internal logic of the current row is correct. If the data written to the current line is different from the simulated output data, then the internal logic of the current line is incorrect.
4. The fast read / write verification method for the efuse module according to claim 3, characterized in that, Step S4 also includes: Output the comparison result between the written data and the simulated output data in the current row; When the data written to the current line is the same as the simulated output data, a correct message is output. When the data written to the current line is different from the simulated output data, an error message is output, along with the written data and the simulated output data.
5. An efuse module fast read / write verification system for executing the efuse module fast read / write verification method as described in any one of claims 1-4, characterized in that, include: A random number array generation module is used to obtain the number of rows and columns of an efuse module and generate a random number array with the same number of rows and columns. The netlist writing module is used to modify the netlist of the efuse module and write random numbers into the netlist; The simulation verification module is used to generate a simulation testbench with input stimulus that simulates the actual environment, and to perform full array read operation simulation on the efuse module. The read / write verification module is used to compare the random number written in the netlist in the netlist writing module with the output data obtained from simulation in the simulation verification module to perform read / write verification on the efuse module, thereby verifying the correctness of the internal logic.
6. A computer device comprising a memory and one or more processors, the memory storing computer code that, when executed by the one or more processors, causes the one or more processors to perform the method as described in any one of claims 1 to 4.
7. A computer-readable storage medium storing computer code, wherein when the computer code is executed, the method of any one of claims 1 to 4 is performed.