A method for selecting the optimal device in device modeling

Abstract

This invention provides a method for selecting the optimal device in device modeling, comprising: obtaining test data of measurement parameters of all devices in each wafer of a whole wafer; calculating the median of each measurement parameter based on the test data; calculating the error data between the test data and the corresponding median; determining whether the error data meets the corresponding preset conditions; selecting the center wafer based on the wafer map; and, in response to the error data of each measurement parameter that meets the preset conditions being in the same device on the same wafer, and the wafer being the center wafer, then the device is the optimal device, and the wafer with the most optimal devices is the best wafer. This invention improves the selection of the optimal device in device modeling, ensuring that the finally selected device is the optimal device.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a method for selecting the optimal device in device modeling. Background Technology

[0002] In existing SPICE modeling techniques, the industry-standard method for optimal device selection is to use Excel to calculate and filter various metrics (Vtlin, Vtsat, Idlin, Idsat, etc.) for each device based on mapping test data, and then select a die (Golden Die) whose metrics are closest to the median. However, as semiconductor technology process nodes shrink to 55nm and below, device size decreases, and device fluctuations due to process technology become increasingly apparent. This leads to changes in device performance, as shown in Figure 1, where the device voltage Vt / current Ids of the Golden Die deviates from the median. The Golden Die cannot accurately reflect the typical electrical characteristics of the device. To design high-quality, competitive products, more work is needed to select good devices for device modeling, and to increase the difficulty and complexity of model extraction. Summary of the Invention

[0003] In view of this, the present invention provides a method for selecting the optimal device in device modeling, which improves the selection of the optimal device in device modeling, ensures that the finally selected device is the optimal device, and improves the accuracy of modeling extraction.

[0004] This invention provides a method for selecting the optimal device in device modeling, comprising the following steps:

[0005] Step 1: Obtain test data for the measurement parameters of all devices on each wafer of the entire wafer;

[0006] Step 2: Calculate the median of the measurement parameters based on the test data;

[0007] Step 3: Calculate the error between the test data and the corresponding median;

[0008] Step 4: Determine whether the error data meets the corresponding preset conditions;

[0009] Step 5: Select the central chip based on the chip map;

[0010] Step 6: In response to the error data of each measurement parameter that meets the preset conditions being in the same device on the same wafer, and the wafer being the central wafer, then the device is the optimal device, and the wafer with the most optimal devices is the best wafer.

[0011] Preferably, in step one, the test data of the device is obtained based on the results of the mapping test.

[0012] Preferably, the test parameters in step one include saturation current Idsat, linear current Idlin, linear threshold voltage Vtlin, and saturation threshold voltage Vtsat.

[0013] Preferably, the error data in step three includes the error between the test data and the corresponding median value of all measurement parameters for all device dimensions in each wafer.

[0014] Preferably, the error data in step three includes the difference between the linear threshold voltage Vtlin and the corresponding median, the difference between the saturation threshold voltage Vtsat and the corresponding median, the ratio of the saturation current Idsat to the corresponding median minus 1, and the ratio of the linear current Idlin to the corresponding median minus 1.

[0015] Preferably, the preset conditions in step four are: the difference between the voltage and the corresponding median does not exceed 20mV, and the ratio of the current to the corresponding median minus 1 does not exceed 3%.

[0016] Preferably, the central wafers selected in step five meet the following criteria: wafers not at coordinate (0,0), wafers with a small sum of absolute values ​​of their horizontal and vertical coordinates, and wafers whose number does not exceed 60% of the total number of wafers.

[0017] Preferably, the method further includes: in response to the failure to select the optimal device, returning to step four, redefining the preset conditions, and then making a judgment.

[0018] This invention first selects central wafers (Golden dies) that meet certain conditions based on the wafer map. Then, it selects the optimal device from among the central wafers using the selection rules for the optimal device. Simultaneously, the wafer with the most optimal devices is selected as the optimal wafer, and all devices within the optimal wafer satisfy the criteria for the golden device. This invention improves the selection of optimal devices in device modeling, ensuring that the finally selected device is the optimal device, thus improving the accuracy of modeling and extraction. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figures 1a-1b The graph shows the trend of voltage and current of devices within a wafer in the existing technology center as a function of length.

[0021] Figure 2The flowchart shown is a method for selecting the optimal device in device modeling according to an embodiment of the present invention;

[0022] Figure 3 The flowchart shown is a method for selecting the optimal device in device modeling according to an embodiment of the present invention.

[0023] Figure 4 The diagram shown is a wafer map according to an embodiment of the present invention.

[0024] Figures 5a-5d The table showing the selection results of the optimal device in this embodiment of the invention, along with the corresponding trend graphs of voltage and current as a function of length, is displayed. Detailed Implementation

[0025] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0026] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0027] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0028] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0029] SPICE modeling serves as a bridge between semiconductor manufacturing technology and circuit design, providing circuit designers with device-level models for circuit simulation. A complete SPICE model for a process node typically includes models of MOSFETs, BJTs and related back-end metal interconnect capacitors (MOM capacitors), MOSFET parasitic resistance, MOS varactors, etc. The SPICE modeling process generally begins with testing the test structure using Wafer Acceptance Test Mapping (WAT MAPPING). A wafer contains many identical die structures (DIEs). For the same device, each die has this device structure, and the electrical parameters of this device on each die are measured during mapping. This yields a set of data for each electrical parameter of each device. The median is then taken, and a trend graph can be plotted as the width or length changes. For each device of a specific size, the die closest to the median is selected after obtaining the mapping data; this is called the Golden Die. The goal of the SPICE model is to use a BSIM model to accurately fit the trends of the device's electrical parameters with size variations and extract the correct BSIM model parameter set. This invention improves the method for selecting the central wafer in device modeling, further ensuring that the finally selected device is the optimal device. The technical solution of this invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0030] Figure 2 This is a flowchart illustrating the method for selecting the optimal device in device modeling according to an embodiment of the present invention. For example... Figure 2 As shown, the method for selecting the optimal device in device modeling in this embodiment of the invention includes the following steps:

[0031] Step 1: Obtain test data for the measurement parameters of all devices on each wafer of the entire wafer.

[0032] In this embodiment of the invention, mapping data is obtained by performing mapping data tests on the devices of the entire wafer (die). The mapping data consists of tests on the main electrical parameters of all devices (such as linear threshold voltage Vtlin, saturation threshold voltage Vtsat, linear current Idlin, saturation current Idsat, off-state current Idoff, etc.).

[0033] Step 2: Calculate the median of the measurement parameters based on the test data.

[0034] For each measurement parameter of each device, a set of data is obtained, and the median is taken.

[0035] Step 3: Calculate the error between the test data and the corresponding median.

[0036] In this embodiment of the invention, the error data includes the error between the test data of all measurement parameters for all device dimensions in each wafer and the corresponding median value. Specifically, the error data includes the difference between the linear threshold voltage Vtlin and the corresponding median, the difference between the saturation threshold voltage Vtsat and the corresponding median, the ratio of the saturation current Idsat to the corresponding median minus 1, and the ratio of the linear current Idlin to the corresponding median minus 1.

[0037] Step 4: Determine whether the error data meets the corresponding preset conditions.

[0038] In this embodiment of the invention, the preset conditions are: the difference between the voltage and the corresponding median does not exceed 20mV, and the ratio of the current to the corresponding median minus 1 does not exceed 3%. Specifically, the preset conditions are: the difference between the linear threshold voltage Vtlin and the corresponding median does not exceed 20mV; the difference between the saturation threshold voltage Vtsat and the corresponding median does not exceed 20mV; the ratio of the saturation current Idsat to the median minus 1 does not exceed 3%; and the ratio of the linear current Idlin to the corresponding median minus 1 does not exceed 3%.

[0039] Step 5: Select the central chip based on the chip map.

[0040] A wafer map is a method used to record test results during wafer testing, typically including coordinates, bins, pass / fail information, etc. In this embodiment of the invention, the central wafers selected based on the wafer map meet the following criteria: wafers not located at coordinates (0, 0), the sum of the absolute values ​​of the wafer's horizontal and vertical coordinates is small, and their number does not exceed 60% of the total number of wafers. That is, the coordinates of the central wafer cannot be the center (0, 0), and it must be located within 60% of the map, because dies near the edge are not representative. The sum of the DieX and DieY coordinates is minimized, indicating that the wafer should be as close to the map's interior as possible, thus selecting representative dies.

[0041] Step 6: If the error data of each measurement parameter that meets the preset conditions are in the same device on the same wafer, and the wafer is the central wafer, then the device is the optimal device, and the wafer with the most optimal devices is the best wafer.

[0042] like Figure 4 As shown in the wafer map, the white dies represent the optimal devices, and the wafer with the most optimal devices in the white dies is the best wafer.

[0043] The method in this embodiment of the invention further includes: in response to the failure to select the optimal device, returning to step four, redefining the preset conditions, and then making a judgment.

[0044] Figure 3 This is a flowchart illustrating the method for selecting the optimal device in device modeling according to an embodiment of the present invention. For example... Figure 3 As shown, it includes the following steps:

[0045] S1: Input WAT data.

[0046] S2: Calculate according to the preset judgment table.

[0047] The preset judgment table, such as the difference between the linear threshold voltage Vtlin and the corresponding median: Vtlin-Vtlin_median, and the ratio of the saturation current Idsat to the corresponding median minus 1: Idsat / Idsat_median-1.

[0048] S3: Define the rules for judging the calculation results.

[0049] The calculation result refers to the calculation result of S2. Judgment rules include: the difference between voltage and the corresponding median does not exceed 20mV: abs(Vtlin-Vtlin_median) <= 20mV; the ratio of current to the corresponding median minus 1 does not exceed 3%.

[0050] abs(Idsat / Idsat_median-1)<=3%.

[0051] S4: Judgment rules for selecting the optimal device.

[0052] If the calculation results that satisfy the judgment rule S3 above are in the same device on the same wafer, then the data shown is the optimal device (Golden Device), and the wafer with the most optimal devices is the best wafer.

[0053] S5: Die Map Rules. The center wafer of the wafer map must meet the following conditions: wafers not at coordinates (0,0), wafers with a small sum of absolute values ​​of their x and y coordinates, and wafers whose number does not exceed 60% of the total number of wafers.

[0054] S6: Confirm whether it is the optimal device.

[0055] If the center die in the die map coincides with the best die in S4, then the device in that best die is the optimal device. Otherwise, return to S3, that is, redefine the judgment rule for the calculation result.

[0056] In this embodiment of the invention, it is necessary to continuously define the judgment rules for the calculation results of the device test data judgment table until the optimal device is selected, striving to ensure that the selected optimal device can accurately reflect the typical characteristics of the process and the device. This invention can improve the selection of the optimal device in device modeling, ensuring that the finally selected device is the optimal device and improving the accuracy of model extraction.

[0057] Figures 5a-5d The table showing the selection results of the optimal device in this embodiment of the invention, along with the corresponding trend graphs of voltage and current variations with length, illustrates this. As can be seen from the graphs, compared to the existing central die (Golden Die), the trend of the test data for the optimal device closely matches the trend of the bit values ​​in the mapping test data. In other words, the selected optimal device accurately reflects the typical characteristics of the process and the device.

[0058] This invention first selects central wafers (Golden dies) that meet certain conditions based on the wafer map. Then, it selects the optimal device from among the central wafers using the selection rules for the optimal device. Simultaneously, the wafer with the most optimal devices is selected as the optimal wafer, and all devices within the optimal wafer satisfy the criteria for the golden device. This invention improves the selection of optimal devices in device modeling, ensuring that the finally selected device is the optimal device, thus improving the accuracy of modeling and extraction.

[0059] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for selecting the optimal device in device modeling, characterized in that, Includes the following steps: Step 1: Obtain test data for the measurement parameters of all devices on each wafer of the entire wafer; Step 2: Calculate the median of the measurement parameters based on the test data; Step 3: Calculate the error between the test data and the corresponding median; Step 4: Determine whether the error data all meet the corresponding preset conditions; Step 5: Select the central wafers based on the wafer map; the central wafers must meet the following conditions: wafers not at coordinate (0,0), the sum of the absolute values ​​of the horizontal and vertical coordinates of the wafers is the smallest, and their number does not exceed 60% of the total number of wafers; Step 6: In response to the error data of each measurement parameter that meets the preset conditions being in the same device on the same wafer, and the wafer being the central wafer, then the device is the optimal device, and the wafer with the most optimal devices is the best wafer.

2. The method of claim 1, wherein, In step one, the test data of the device is obtained based on the results of the mapping test.

3. The method for selecting the optimal device in device modeling according to claim 1, characterized in that, The measurement parameters mentioned in step one include saturation current Idsat, linear current Idlin, linear threshold voltage Vtlin, and saturation threshold voltage Vtsat.

4. The method for selecting the optimal device in device modeling according to claim 1, characterized in that, The error data mentioned in step three includes the error between the test data and the corresponding median value of all measurement parameters for all device dimensions in each wafer.

5. The method for selecting the optimal device in device modeling according to claim 3, characterized in that, The error data mentioned in step three includes the difference between the linear threshold voltage Vtlin and its corresponding median, the difference between the saturation threshold voltage Vtsat and its corresponding median, the ratio of the saturation current Idsat to its corresponding median minus 1, and the ratio of the linear current Idlin to its corresponding median minus 1.

6. The method for selecting the optimal device in device modeling according to claim 5, characterized in that, The preset conditions mentioned in step four are: the difference between the voltage and the corresponding median does not exceed 20mV, and the ratio of the current to the corresponding median minus 1 does not exceed 3%.

7. The method for selecting the optimal device in device modeling according to claim 1, characterized in that, The method further includes: in response to the failure to select the optimal device, returning to step four, redefining the preset conditions, and then making a judgment.

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