Unit interference prevention using funnel device

Abstract

The present disclosure relates to cell interference prevention using funneling devices. Various embodiments of the invention include apparatuses and methods of forming the apparatuses. In one embodiment, an exemplary apparatus includes a plurality of memory cells. At least a portion of the memory cells have bottom electrodes, where each bottom electrode is at least partially electrically isolated from the rest of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to drain at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of Chinese invention patent application entitled "Unit Interference Prevention Using a Funnel Device", application number 201780073080.5, and application date October 31, 2017.

[0003] Priority application

[0004] This application claims priority to U.S. Application No. 15 / 340,682, filed November 1, 2016, the entire contents of which are incorporated herein by reference. Technical Field

[0005] This disclosure relates to unit interference prevention using a funnel device. Background Technology

[0006] Computers and other electronic systems (such as digital televisions, digital cameras, and cellular phones) typically have one or more memory devices to store information. The size of memory devices is decreasing to achieve higher storage densities. Even with these increased densities, consumers generally demand that memory devices use less power while maintaining high-speed access and stability of the data stored in them. Summary of the Invention

[0007] On one hand, this disclosure provides an apparatus comprising: a plurality of electronic devices, each of the plurality of electronic devices having at least a portion of a bottom electrode, the bottom electrode being at least partially electrically isolated from the bottom electrodes of other electronic devices; and a resistive interconnect electrically coupled to two or more of the bottom electrodes, the resistive interconnect being configured to discharge at least a portion of excess charge from the two or more bottom electrodes.

[0008] On the other hand, this disclosure also provides a method comprising: forming a plurality of electronic devices, each of the plurality of electronic devices having at least one electrode; and forming a funnel device to electrically couple at least a portion of the electrode of the plurality of electronic devices, the funnel device being used to discharge at least a portion of excess charge from the at least a portion of the electrode.

[0009] On the other hand, this disclosure also provides an apparatus comprising: a plurality of memory cells arranged in rows and columns, each of the plurality of memory cells having a bottom electrode at least partially electrically isolated from the bottom electrodes of other memory cells in the plurality of memory cells; a plurality of funnel devices, each including a resistive interconnect, wherein one of the funnel devices is coupled to each of the bottom electrodes in a corresponding row of the plurality of memory cells, each funnel device being configured to discharge at least a portion of excess charge from the bottom electrode to prevent memory cell interference while not electrically short-circuiting the corresponding bottom electrode; and a contact line electrically coupling each of the plurality of funnel devices to a discharge structure.

[0010] On the other hand, this disclosure also provides an apparatus comprising: a plurality of electronic devices, each having an electrode node and an electrode directly coupled to the electrode node, the electrode nodes of the plurality of electronic devices being at least partially electrically isolated from each other; and a funnel device comprising an interconnection directly coupled to each of two or more electrode nodes of the plurality of substrate devices, and configured to drain at least a portion of excess charge from the two or more electrode nodes.

[0011] On the other hand, this disclosure also provides a method comprising: draining at least a portion of excess charge from two or more electrode nodes, the plurality of electrode nodes being at least partially electrically isolated from each other and each coupled to an electrode of one of a plurality of electronic devices, using a funnel device comprising an interconnection line directly coupled to each of the two or more electrode nodes.

[0012] On the other hand, this disclosure also provides an apparatus comprising: a plurality of electronic devices, each having an electrode node and an electrode directly coupled to the electrode node, the electrode nodes of the plurality of electronic devices being at least partially electrically isolated from each other; means for discharging at least a portion of excess charge from the electrode node; and means for electrically coupling the electrode node to the means for discharging, including means for directly coupling two or more of the plurality of electrode nodes to the means for discharging.

[0013] On the other hand, this disclosure also provides a system comprising: a controller; a memory device coupled to the controller; and a shift register coupled to the controller, wherein at least one of the controller, the memory device, and the shift register comprises: a plurality of memory cells, each having an electrode, the electrode being partially electrically isolated from the electrodes of other memory cells in the plurality of memory cells; and a funnel device electrically coupled to the plurality of electrodes of the plurality of memory cells and configured to discharge at least a portion of excess charge from the plurality of electrodes.

[0014] On the other hand, this disclosure also provides a method comprising: preventing memory cell interference in a system including a controller, a memory device, and a shift register by using a funnel device electrically coupled to a plurality of electrodes to discharge at least a portion of excess charge from the plurality of electrodes of the plurality of memory cells in the controller, the memory device, or the shift register, the plurality of electrodes being at least partially electrically isolated from each other.

[0015] On the other hand, this disclosure also provides a memory device comprising: a plurality of memory cells arranged in rows and columns, each of the plurality of memory cells having an electrode at least partially electrically isolated from the electrodes of other memory cells in the plurality of memory cells; and a plurality of funnel devices, each coupled to an electrode in a corresponding row of the plurality of memory cells and configured to discharge at least a portion of excess charge from the electrically coupled electrode in the row of the plurality of memory cells. Attached Figure Description

[0016] Figure 1A This is an electrical schematic diagram of a memory device having a single access device electrically coupled to a bottom electrode, according to an embodiment;

[0017] Figure 1B This is an electrical schematic diagram of a memory device having two access devices according to an embodiment, wherein a first access device is electrically coupled to a bottom electrode and a second access device is electrically coupled to a top electrode;

[0018] Figure 2A This is an embodiment of a cross-sectional view of a portion of a memory array, showing the first position of the bottom node funnel assembly;

[0019] Figure 2B and 2C exhibit Figure 2A Plan views of various embodiments of alternative arrangements of the bottom node funnel device;

[0020] Figure 3A This is an embodiment of a cross-sectional view of a portion of a memory array, showing an alternative location for the bottom node funnel device;

[0021] Figure 3B and 3C exhibit Figure 3A Plan views of various embodiments of alternative arrangements of the bottom node funnel device;

[0022] Figure 4 Display according to Figure 2A or Figure 3A An embodiment of a cross-sectional view of a portion of a memory array of a bottom node funnel device, which demonstrates a bottom node funnel device capable of being coupled to a substrate to reduce or eliminate excess charge on the bottom electrode.

[0023] Figure 5A and 5B Display according to Figure 2A , 3A A plan view of an embodiment of a memory array incorporating a bottom node funnel device, as shown in Figure 4;

[0024] Figure 6 It is the basis for manufacturing Figure 2A , 3A Examples of high-level flowcharts of the methods of the apparatus in the embodiments shown in Figure 4; and

[0025] Figure 7 This is a block diagram of a system embodiment, which includes a memory device. Detailed Implementation

[0026] The following description includes illustrative devices (circuit systems, apparatus, structures, systems, and the like) and methods (e.g., processes, sequences, techniques, and sciences) that embody the subject matter of the invention. In the following description, numerous specific details are set forth for purposes of explanation to provide an understanding of various embodiments of the subject matter. However, after reading this invention, those skilled in the art will understand that various embodiments of the subject matter can be practiced without these specific details. Furthermore, well-known devices and methods have not been shown in detail to avoid obscuring the description of various embodiments. Additionally, as will be understood by those skilled in the art, relative terms used herein (e.g., top, bottom, upper, lower, etc.) are used only to convey the general concepts disclosed and should not be considered absolute terms. For example, a “bottom” node may actually be formed above a memory cell depending on the actual manufacturing sequence employed.

[0027] Many (if not most) primary memory cell interference mechanisms are caused by the potential established at the bottom-of-cell (CB) electrode node. As discussed in more detail below, this interference mechanism applies to ferroelectric RAM (FERAM). However, other types of electronic devices may also benefit from the subject matter described.

[0028] In an embodiment, each memory cell in the memory array is programmable to one of two data states to represent a binary value "0" or "1" in a single bit. This cell is sometimes referred to as a single-layer cell (SLC). Various operations on these types of cells are known independently in semiconductor and related technologies.

[0029] Regardless of the memory cell arrangement, the primary disturbance mechanisms discussed above can be attributed to various factors. For example, the charge on the bottom node of a cell can increase due to factors such as board pulse interference, access transistor leakage, inter-cell interactions, or other factors. If the dielectric material in the memory cell is significantly leaking, it can adversely affect the cell's state.

[0030] In the various embodiments described herein, a bottom node funnel device (or funnel device, regardless of location) is electrically coupled to one or more CB electrode nodes, thereby draining excess charge from the CB electrode nodes (e.g., internal nodes of a memory device). The bottom node funnel device may be further electrically coupled to a substrate on which memory cells are formed. Thus, bottom node funnel devices are introduced into memory arrays to prevent the accumulation of potential at the bottom nodes of individual memory cells, as discussed in more detail below.

[0031] refer to Figure 1A The diagram illustrates an electrical schematic of a capacitor-based memory device 100. The memory device 100 is shown as including a top electrode 101, a capacitor 103, an access device 107, and a bottom node 105 of a cell electrically coupled between the capacitor 103 and the access device 107. This type of memory device 100 typically refers to a single-transistor single-capacitor (1T1C) device.

[0032] Access device 107 may include, for example, various types of transistors, including thin-film transistors or other switching devices known in the art (e.g., bidirectional limit switches (OTS), tunneling diodes, etc.). Capacitor 103 may include various types of electrode plates formed close to or around dielectric and ferroelectric materials, as known in the art and discussed in more detail below.

[0033] Figure 1B An electrical schematic diagram of a memory device 110 with two access devices is shown. The memory device 110 is shown as including a first access device 109 coupled to a top node 111 and a capacitor 113. The capacitor is further coupled to a bottom node 115 and a second access device 117. Each of the first access device 109 and the second access device 117 may be the same as or similar to... Figure 1A Access device 107. Furthermore, capacitor 113 may be the same as or similar to... Figure 1AThe capacitor 103. As shown, memory device 110 generally refers to a dual-transistor single-capacitor (2T1C) device.

[0034] exist Figure 1A memory cell 100 or Figure 1B In memory cell 110, during fast access to the cell, various pull-up and pull-down cycles (implemented as needed by selecting individual access devices 107, 109, 117) used to store a given binary state in the ferroelectric material can cause excessive charge accumulation on the bottom nodes 105, 115 of the cell. This excessive charge can interfere with cells undergoing charge / discharge cycles and potentially interfere with neighboring memory cells. These processes are described below. Figures 2A to 4 To make it easier to understand.

[0035] For reference Figure 2A This diagram illustrates an embodiment of a cross-sectional view 200 showing a portion of a memory array. The cross-sectional view 200 shows an portion of the memory array including an electrode plate 201, a top electrode 203, a bottom electrode 205, and a cell bottom node electrode 207. Memory cell material 215 is generally formed within a cavity formed between the top electrode 203 and the bottom electrode 205. As shown, each memory cell 211 includes a top electrode 203, a bottom electrode 205, and memory cell material 215.

[0036] Individual memory cells 211 are separated from each other (e.g., at least partially electrically isolated) and surrounded by a first dielectric material 209. In one embodiment, the first dielectric material 209 may comprise various types of dielectric materials (e.g., silicon dioxide (SiO2)) to at least partially electrically isolate the memory cells 211 from each other. However, those skilled in the art will recognize upon reading the disclosure provided herein that materials other than silicon dioxide or other various types of insulating materials can be used to form the first dielectric material 209. For example, various types of dielectric materials (e.g., silicon nitride (SiO2)) x N y (or various other dielectric or ceramic materials) can be used as a substitute for or in combination with silicon dioxide or other types of dielectric or insulating materials.

[0037] In one embodiment, the memory cell material 215 comprises a ferroelectric material (e.g., lead zirconate titanate (PZT)). In other embodiments, the dielectric composition of the memory cell material may include HfO2, ZrO2, Hf x Zr y O, NbO x AlO x LaO xSrTiO3, SrO, HfSiO x HfAlO x Or a combination of these and other dielectric materials. Therefore, the dielectric composition of the memory cell material 215 may or may not include materials that are the same as the first dielectric material 209.

[0038] A first dielectric material 209 and a plurality of memory cells 211 are formed over a substrate (not shown but readily understood by those skilled in the art). In various embodiments, the substrate may comprise, for example, any of a variety of substrates used in the semiconductor and related industries (which may be referred to herein as a “semiconductor substrate” or simply a “substrate”). Thus, substrate types may include silicon substrates (e.g., wafers) or substrates based on other semiconductor elements, composite wafers (e.g., from group III-V, II-VI, etc.), thin-film head assemblies, polyterephthalic acid (PET) films deposited or otherwise formed with semiconductor layers, or several other types of substrates independently known in the art. Furthermore, the substrate may include regions of semiconductor material formed over non-semiconductor materials, or vice versa. For ease of understanding of the manufacturing activities presented herein, the substrate may be considered as a silicon wafer. Upon reading and understanding the disclosure provided herein, those skilled in the art will understand how various memory cell manufacturing activities can be modified to account for other types of materials and electronic devices.

[0039] Each of the bottom node electrodes 207 of the cell is coupled to an access transistor (not shown but conceptually similar). Figure 1A and 1B (Access transistors 107, 109, 117). Furthermore, those skilled in the art will recognize that modifications are readily possible. Figure 2A Memory cells with similar Figure 1B The electrical schematic diagram shows multiple 2T1C structures.

[0040] Figure 2AFurther illustration includes a bottom node funnel 213. Although only a single funnel is shown, additional funnels can be added, as discussed in more detail below. The bottom node funnel 213 can electrically couple some or all of the memory cells 211. The resistance of the bottom node funnel 213 can be customized to remove excess charge from the memory cells 211 without short-circuiting the bottom electrode 205. Thus, the bottom node funnel is a resistive interconnect. If the bottom node funnel leakage is too high, one or more memory cells may experience inter-cell interference. If the bottom node funnel leakage (conductivity) is not high enough, excess charge will not be drained. Those skilled in the art will recognize how to calculate the required resistance of the bottom node funnel 213 for a given memory array. For example, the resistance of the bottom node funnel 213 can be selected from about 0.1 MΩ (megaohms) to about 5 MΩ. When determining the required resistance of the bottom node funnel 213, factors such as the spacing between adjacent memory cells, the dielectric material used between cells, physical dimensions (e.g., the total height 217 of the bottom electrode 205), the amount of charge placed in the cell, the size of the memory array, and the frequency of operation can be taken into consideration.

[0041] The physical cross-section of the bottom node funnel and the material selected to form the bottom node funnel 213 are factors to be considered when forming the bottom node funnel 213. For example, the bottom node funnel 213 may be made of, for example, amorphous silicon (with a thickness of, for example, approximately...). To date α-Si), niobium oxide (for example) with a thickness of approximately To date NbO x ), leaked silicon-rich silicon nitride (e.g., thickness of approximately To date Si x N y Materials formed from materials of the present invention or their combinations thereof or other materials independently known in the present technology. Each of these materials may be formed or otherwise deposited using a variety of forming or deposition processing tools, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), etc.

[0042] The bottom node funnel 213 can be placed anywhere along the total height 217 of the bottom electrode 205. The location of the bottom node funnel 213 can be selected based on specific process steps or other factors. For example, the bottom node funnel 213 can be positioned as follows: Figure 2AAs shown in the diagram, it is positioned close to but not above the upper portion of the bottom electrode 205. In this embodiment, those skilled in the art will recognize that a portion of the bottom node funnel 213 can be stripped as needed using a reverse mask, which is independently known in semiconductor technology. In other embodiments, the bottom node funnel 213 may be positioned on top of the bottom electrode 205 to avoid using a reverse mask. As discussed below, Figure 3A Provides an instance of an alternative placement for the bottom node funnel 213.

[0043] Figure 2B and 2C exhibit Figure 2A Plan view of various embodiments of alternative arrangements of the bottom node funnel 213 (at section AA). It should be noted that... Figure 2B and Figure 2C The top electrode 203 is not shown; this omission is merely to avoid confusion with various examples of arrangements forming the bottom node funnel 213. Those skilled in the art will understand that in this embodiment, the memory cell 211 is formed as a plurality of vias. However, this arrangement is not necessary, and the memory cell 211 can be formed as trenches or in various other ways independently known in semiconductor technology. For example, as described in detail below, Figures 3A to 3C Another embodiment is described, in which the memory cells can replace the terrain as trenches.

[0044] In the first arrangement 210 of the bottom node funnel 213, each of the memory cells is shown as coupled by a single material “line” forming the bottom node funnel 213. Although shown as a single line coupling the memory cells 211, those skilled in the art will recognize, based on reading and understanding the inventive subject matter disclosed herein, that multiple material lines can be used. Furthermore, the line need not be formed near the central portion of the memory cell 211, but can be formed at other locations (e.g., formed to couple to the outer edge of the memory cell 211). Moreover, as discussed above, not all memory cells 211 need to be coupled to each other; only selected memory cells 211 can be electrically coupled to the bottom funnel node 213.

[0045] In the second arrangement 220 of the bottom node funnel 213, each of the memory cells is shown to be coupled by more than one material layer forming the bottom node funnel 213. Although shown as a single layer coupling the memory cells 211, those skilled in the art will recognize, based on reading and understanding the inventive subject matter disclosed herein, that multiple material layers may be used, each of which is separated from the others by a dielectric material layer. Each of the layers may comprise materials that are the same as or different from the examples materials discussed above, or other materials. Furthermore, as discussed above, not all memory cells 211 need to be coupled to each other; only selected memory cells 211 may be electrically coupled to the bottom funnel node 213.

[0046] exist Figure 3A The image shows an embodiment of a cross-sectional view 300 of a portion of a memory array. The cross-sectional view 300 shows an portion of the memory array including an electrode plate 301, a top node 303, a bottom node 305, and a cell bottom node 307. Memory cell material 315 is generally formed within a cavity formed between the top node 303 and the bottom node 305. As shown, each memory cell 311 includes a top node 303, a bottom node 305, and memory cell material 315.

[0047] Figure 3A This is further illustrated by including the bottom node funnel 313. Figure 3A In some embodiments, the bottom node funnel is positioned at or near the bottom edge of the bottom electrode 305. However, as... Figure 2A The bottom node funnel 313 can be placed anywhere along the total height 317 of the bottom node 305. Figure 3A The bottom node funnel 313 can also electrically couple some or all of the memory cells 311. Furthermore, as... Figure 2A The location of the bottom node funnel 213 can be selected based on specific process steps or other factors. Each of these components can be made similar to or the same as those relating to... Figure 2A The material formation described by the relevant components.

[0048] For reference Figure 3B and 3C The plan view, at section BB, shows... Figure 3A Various embodiments of alternative arrangements of the bottom node funnel device 313. It should be noted that... Figure 3B and Figure 3C The top electrode 203 is not shown in any of the examples; this omission is solely to avoid confusion with the various arrangements forming the bottom node funnel 313. Furthermore, as shown, Figure 3A The memory cells are formed as trenches.

[0049] In the first arrangement 310 of the bottom node funnel 313, each of the memory cells is shown as coupled by a single material “line” forming the bottom node funnel 313. Although shown as a single line coupling the memory cells 311, those skilled in the art will recognize, based on reading and understanding the inventive subject matter disclosed herein, that multiple material lines can be used. Furthermore, the line need not be formed near the central portion of the memory cell 311, but can be formed at other locations (e.g., formed to couple to the “upper” or “lower” edge of the memory cell 311 relative to the plan view). Moreover, as discussed above, not all memory cells 311 need to be coupled to each other; only selected memory cells 311 can be electrically coupled to the bottom funnel node 313.

[0050] In the second arrangement 320 of the bottom node funnel 313, each of the memory cells is shown to be coupled via more than one material layer forming the bottom node funnel 313. As... Figure 2C Although shown as a single layer of coupled memory cell 311, those skilled in the art will recognize, upon reading and understanding the inventive subject matter disclosed herein, that multiple material layers may be used. Each of the layers may comprise the same or different materials from the examples discussed above, or other materials. Furthermore, as discussed above, not all memory cells 311 need to be coupled to each other; only selected memory cells 311 may be electrically coupled to the bottom funnel node 313.

[0051] Figure 4 Display according to Figure 2A or Figure 3A An embodiment of a memory array, a portion 400 of a bottom node funnel device, is shown in cross-sectional view, illustrating a bottom node funnel device capable of coupling to a substrate to reduce or eliminate excess charge on the bottom electrode. However, Figure 4Further indications are provided regarding embodiments in which additional contact lines 401 are coupled on a first portion to bottom node funnels 213, 313 and on a lower portion to a substrate (not shown) in which a memory array is formed, or to another discharge structure (again not shown, but which will be understood by those skilled in the art upon reading and understanding the disclosure provided herein). The contact lines can be formed from a variety of materials known in the semiconductor industry. The materials may be the same as or similar to the materials used to form the bottom node funnels 213, 313, or several materials. In other embodiments, contact lines 401 may be formed from a conductive material, including, but not limited to, conductive materials comprising, but not limited to, oxides of metals, transition metals, or metals used in standard semiconductor manufacturing processes (e.g., aluminum (Al), tungsten (W), tantalum (Ta), titanium (Ti), copper (Cu), platinum (Pt), etc.). Contact lines 401 may also include a component containing metals (e.g., metal silicides, metal carbides, etc.) and conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.) or various combinations thereof.

[0052] Contact line 401 can discharge excess charge from the bottom electrodes 205, 305 to the substrate or other discharge structures. Similar to... Figure 2A or Figure 3A Relatedly, bottom node funnels 213, 313 may couple all or some selected of memory cells 211, 311, which are in turn electrically coupled to contact line 401 and substrate or other discharge structures.

[0053] For reference Figure 5A and 5B Display according to Figure 2A , 3A A plan view of an embodiment of a memory array incorporating a bottom node funnel device, as shown in embodiment 4. Figure 2A (Obtained at section AA). As mentioned above, Figure 5A and Figure 5B None were displayed. Figure 2A The top electrode 203. The top electrode 203 is not shown only to avoid confusion with various examples of the arrangement that form the bottom node funnel 213.

[0054] refer to Figure 5A The first two-dimensional arrangement 500 of the memory cells, in this embodiment, each of the memory cells is coupled to each other within a given row via a bottom node funnel 213 leading to an interconnect 501. The interconnect 501 is in turn coupled to... Figure 4The bottom contact line 401 (not shown). The interconnect 501 may be formed of a material similar to or the same as the contact line 401. In various embodiments, the contact line 401 may extend directly down from each separate bottom node funnel 213 to the substrate or other discharge structure, rather than coupling each of the bottom node funnel 213 lines to the interconnect 501. In various embodiments, not all memory cells are coupled to the bottom node funnel 213.

[0055] refer to Figure 5B The second two-dimensional arrangement 510 of the memory cells, in this embodiment, each of the memory cells is coupled to each other within a given row and coupled to each other across adjacent rows via a bottom node funnel 213 leading to the interconnect 501. As... Figure 5A The interconnect 501 is coupled to the underlying contact line 401 (not shown). Furthermore, as... Figure 5A In various embodiments, contact lines 401 may extend directly down from each separate bottom node funnel 213 to the substrate or other discharge structure, rather than coupling each of the bottom node funnel 213 lines to the interconnect 501. In various embodiments, not all memory cells are coupled to the bottom node funnel 213, whether within a row or across adjacent rows.

[0056] Now transferred to Figure 6 Showcase manufacturing based on Figure 2A , 3A An example of a high-level flowchart 600 of the method of the apparatus of the embodiment shown in Figure 4. In operation 601, memory cells are formed on a substrate. As mentioned above, memory cells can be manufactured according to known processes and techniques, and can be fabricated as multiple cells formed in the form of vias, trenches, or various other geometries.

[0057] In operation 603, a first dielectric is formed at least partially along the total height of the bottom electrode of the memory cell. The first dielectric material can be formed from any dielectric material or a combination thereof, as discussed above. However, if the subsequently formed bottom node funnel is formed in a manner similar to... Figure 3A At the lowest part of the bottom node discussed, a first dielectric material may or may not be necessary, depending at least in part on how the cell bottom node electrode is formed (e.g., within the first dielectric material 209, 309 or otherwise formed after the formation of the embedded access device but before the formation of the first dielectric material).

[0058] In operation 605, a bottom node funnel is formed to electrically couple two or more memory cells to each other. The bottom node funnel can be formed of any material or combination thereof, as discussed above. In subsequent operations, the bottom node funnel may optionally be etched to produce, as shown in the reference... Figure 2B and 3BThe described bottom node funnel line.

[0059] In operation 607, a second dielectric material is formed above the bottom node funnel. The second dielectric material may be formed of a material identical to the first dielectric material. Alternatively, the second dielectric material may be formed of any other dielectric material or combination thereof, as discussed above.

[0060] In operation 609, contact lines are formed to couple the bottom node funnel to the substrate or other discharge structure. However, the contact lines are optional and depend on the discharge potential of the memory cell and the accompanying cell interference potential, as well as the requirements of the given overall memory array design.

[0061] As mentioned above, each step of the individual processing steps is independently known to those skilled in the art and can be performed using many common manufacturing techniques based on the embodiments and component symbols described herein. Furthermore, additional manufacturing steps known to those skilled in the art (e.g., forming memory cell materials with memory cells and forming electrodes and other related structures) are known in this art and therefore will not be described in detail hereafter.

[0062] Although the various embodiments discussed herein use examples relating to single-bit memory cells for understanding, the inventive subject matter can also be applied to many multi-bit schemes. For example, each of the memory cells 211, 311 can be programmed to be different in at least two data states to represent, for example, a fractional bit value, a single bit value, or multiple bit values ​​(e.g., two, three, four, or a greater number of bits). The bottom node funnels 213, 313 can then be used to remove or reduce excess charge on the walls of the memory cells.

[0063] Those skilled in the art will recognize that memory cells and memory arrays may include other components, at least some of which are discussed herein. However, several of these components are not shown in the figures to avoid obscuring the details of the various embodiments described. Memory cells and memory arrays can be operated using memory operations (e.g., programming and erasing operations) similar to or identical to those independently known in the art.

[0064] Based on reading and understanding the invention provided herein, those skilled in the art can readily extend the techniques and concepts to any number and arrangement of memory cells. For example, those skilled in the art can apply the techniques and concepts to memory blocks having hundreds, thousands, or even more memory cells. Therefore, many embodiments can be implemented.

[0065] For example, Figure 7System 700 is shown as including a controller 703, an input / output (I / O) device 711 (e.g., a keyboard, touchscreen, or display), a memory device 709, a wireless interface 707, a random access memory (e.g., DRAM or SRAM) device 701, and a shift register 715, which are coupled to each other via a bus 713. In one embodiment, a battery 705 may supply power to system 700. Memory device 709 may include NAND memory, flash memory, NOR memory, combinations thereof, or the like.

[0066] Controller 703 may include, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory device 709 may be used to store information transmitted to or through system 700. Memory device 709 may also optionally be used to store information in the form of instructions executed by controller 703 during operation of system 700, and may be used to store information in the form of user data (e.g., image data) generated, collected, or received by system 700. As disclosed herein, the instructions may be stored as digital information and user data, and may be stored as digital information in one segment of memory and as analog information in another segment. As another example, a given segment may be marked to store digital information, and then the given segment may be reallocated and reconfigured to store analog information. Controller 703, memory device 709, and / or shift register 715 may include one or more novel memory devices described herein.

[0067] I / O device 711 can be used to generate information. System 700 can use wireless interface 707 to transmit information to and receive information from wireless communication networks using radio frequency (RF) signals. Examples of wireless interface 707 may include an antenna or a wireless transceiver (e.g., a dipole antenna). However, the scope of the inventive subject matter is not limited in this respect. Furthermore, I / O device 711 can deliver signals reflecting what is stored as a digital output (if digital information is stored) or an analog output (if analog information is stored). Although examples in wireless applications are provided above, embodiments of the inventive subject matter disclosed herein can also be used in non-wireless applications. I / O device 711 may include one or more novel memory devices described herein.

[0068] The various illustrations of the methods and apparatus are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all elements, materials, and features of the apparatus and methods that can utilize the structures, features, and techniques described herein.

[0069] The devices of various embodiments may include, for example, electronic circuit systems for high-speed computers, communication and signal processing circuits, single-processor or multi-processor modules, single or multiple embedded processors, multi-core processors, data switches and multi-layered application-specific modules, multi-chip modules or the like, or the devices of various embodiments may be included in all of the above. These devices may be further included as sub-components within various electronic systems (e.g., televisions, cellular phones, personal computers (e.g., laptops, desktop computers, PDAs, tablets, etc.), workstations, radios, video players, audio players, vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes and various other electronic systems).

[0070] Those skilled in the art will understand that, with respect to the methods disclosed herein and other methods (e.g., structure manufacturing), activities forming parts of various methods can be performed in different sequences and can be repeated and executed synchronously, wherein various elements substitute for each other. Furthermore, the actions and operations summarized are provided merely as examples, and some actions and operations may be selected, combined into fewer actions and operations, or extended into additional actions and operations without departing from the essence of the disclosed embodiments.

[0071] Therefore, the present invention is not limited to the specific embodiments described in this application (which are intended to illustrate various aspects). Many modifications and variations can be made, as will be understood by those skilled in the art upon reading and understanding the invention. From the foregoing description, those skilled in the art will understand that functionally equivalent methods and apparatuses other than those listed herein are within the scope of the invention. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Many other embodiments will be understood by those skilled in the art upon reading and understanding the description provided herein. Such modifications and variations are intended to fall within the scope of the appended claims. The invention is limited only by the terminology of the appended claims and their equivalents. It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.

[0072] Furthermore, as used herein, the term "or" may be understood to mean either inclusive or exclusive. Additionally, although the various exemplary embodiments discussed above focus on 1T1C memory cells, these embodiments are given only to illustrate the invention and are therefore not limited to 1T1C memory cells or even memory cells in general.

[0073] An abstract is provided to allow readers to quickly determine the essence of the invention. It should be understood that the abstract is not intended to interpret or limit the claims. Furthermore, as can be seen in the above embodiments, various features are grouped together in a single embodiment for the purpose of simplifying the invention. This approach of the invention should not be construed as limiting the claims. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is an independent, separate embodiment.

Claims

1. An electronic device comprising: A plurality of electronic devices, each having a bottom electrode, the bottom electrode being at least partially electrically isolated from the bottom electrodes of other electronic devices of the plurality of electronic devices; as well as A resistive interconnect electrically coupled to two or more bottom electrodes, the resistive interconnect being configured to drain at least a portion of excess charge from the two or more bottom electrodes and including an interconnect directly coupled to each of the two or more bottom electrodes.

2. The electronic device of claim 1, wherein at least some of the plurality of electronic devices comprise ferroelectric materials.

3. The electronic device of claim 1, wherein the plurality of electronic devices includes a memory array.

4. The electronic device of claim 1, further comprising a substrate, wherein the plurality of electronic devices are formed on the substrate, and the interconnects are directly coupled to the substrate.

5. The electronic device of claim 1, wherein the resistive interconnect comprises a plurality of interconnects, the plurality of interconnects including the interconnects directly coupled to each of the two or more bottom electrodes.

6. The electronic device of claim 1, wherein the resistive interconnect comprises a single-layer material.

7. The electronic device of claim 1, wherein the resistive interconnect comprises a multilayer material, wherein each of the multilayers is separated from the others by respective dielectric layers.

8. An interference prevention method, comprising: A plurality of electronic devices are formed, each of the plurality of electronic devices having at least one electrode; as well as A funnel device is formed to electrically couple two or more electrodes of at least a portion of the plurality of electronic devices to each other using interconnects, the interconnects being directly coupled to each of the two or more electrodes, the funnel device being used to drain at least a portion of excess charge from the two or more electrodes.

9. The interference prevention method of claim 8, further comprising forming a contact line between the funnel device and the substrate, wherein the plurality of electronic devices are formed on the substrate, wherein the contact line is coupled to the funnel device at a first end and to the substrate at a second end.

10. The interference prevention method according to claim 9, wherein the contact wire comprises at least one conductive material, the at least one conductive material being selected from conductive materials including metals, transition metals, metal-containing components, conductive doped semiconductor materials, and nitrides of metals or transition metals.

11. An electronic device comprising: A plurality of memory cells arranged in rows and columns, each of the plurality of memory cells having a bottom electrode that is at least partially electrically isolated from the bottom electrodes of the other memory cells in the plurality of memory cells; Multiple funnel devices, each including a resistive interconnect, wherein one of the multiple funnel devices includes an interconnect directly coupled to each of the bottom electrodes in a corresponding row of the multiple memory devices, each funnel device being configured to drain at least a portion of excess charge from the bottom electrode coupled to the funnel device to prevent memory cell interference, while not electrically short-circuiting the bottom electrodes coupled to the funnel device to each other. as well as Contact lines that electrically couple each of the plurality of funnel devices to the discharge structure.

12. The electronic device of claim 11, wherein each of the plurality of funnel devices comprises at least one material selected from materials including amorphous silicon, niobium oxide and silicon nitride.

13. The electronic device of claim 11, wherein each of the plurality of memory cells is coupled to each other within a given row and across adjacent rows via at least one of the funnel devices.

14. An electronic device comprising: Multiple electronic devices, each having an electrode node and an electrode directly coupled to the electrode node, wherein the electrode nodes in the multiple electronic devices are at least partially electrically isolated from each other; as well as A funnel device comprising interconnects directly coupled to each of two or more electrode nodes of the plurality of electronic devices, and configured to drain at least a portion of excess charge from the two or more electrode nodes.

15. The electronic device of claim 14, wherein the plurality of electronic devices includes a memory array.

16. The electronic device of claim 14, further comprising a substrate, wherein the plurality of electronic devices are formed on the substrate, and wherein the interconnects are electrically coupled to the substrate.

17. The electronic device of claim 14, wherein the funnel device includes a resistive interconnect, the resistive interconnect including the interconnect line.

18. The electronic device of claim 17, wherein the resistive interconnect includes the interconnect and one or more additional interconnects, each of the one or more additional interconnects being directly coupled to each of two or more remaining electrode nodes of the plurality of electronic devices that are not directly coupled to the interconnect.

19. An interference prevention method, comprising: A funnel device comprising interconnects directly coupled to each of two or more electrode nodes discharges at least a portion of excess charge from two or more electrode nodes, the electrode nodes being at least partially electrically isolated from each other and each coupled to an electrode of one of a plurality of electronic devices.

20. The interference prevention method of claim 19, further comprising discharging at least a portion of the excess charge onto a substrate on which the plurality of electronic devices are formed.

21. The interference prevention method of claim 19, wherein using the funnel device includes using a resistive interconnect including the interconnect, the resistive interconnect having a resistance selected to drain at least a portion of excess charge from the two or more electrode nodes without electrically short-circuiting the two or more electrode nodes to each other.

22. The interference prevention method of claim 19, wherein the plurality of electronic devices includes a memory array, and discharging at least a portion of excess charge from the two or more electrode nodes includes discharging at least a portion of excess charge from the two or more electrode nodes of the electrodes of the memory cells all coupled to the memory array.

23. An electronic device comprising: Multiple electronic devices, each having an electrode node and an electrode directly coupled to the electrode node, wherein the electrode nodes of the multiple electronic devices are at least partially electrically isolated from each other; A means for discharging at least a portion of the excess charge from the electrode node; as well as The means for electrically coupling the electrode nodes to the discharge device includes means for directly coupling two or more of a plurality of electrode nodes to the discharge device.

24. The electronic device of claim 23, wherein the plurality of electronic devices includes a memory array, the memory array including memory cells formed on a substrate.

25. The electronic device of claim 24, wherein the means for discharging comprises the substrate and means for electrically coupling the two or more electrode nodes to the substrate.

26. An electronic system comprising: Controller; A memory device coupled to the controller; as well as A shift register, which is coupled to the controller. At least one of the controller, the memory device, and the shift register includes: Multiple memory cells, each having an electrode, wherein the electrode is electrically isolated from the electrodes of other memory cells in the plurality of memory cells; as well as A funnel device comprising interconnects of multiple electrodes directly electrically coupled to the plurality of memory cells and configured to discharge at least a portion of excess charge from the plurality of electrodes.

27. The electronic system of claim 26, wherein the memory device is a ferroelectric random access memory device, and the controller is configured to execute instructions stored in the memory device.

28. The electronic system of claim 27, further comprising a wireless interface coupled to the controller, the wireless interface being configured to transmit and receive information.

29. The electronic system of claim 26, wherein the funnel device includes a resistive interconnect, the resistive interconnect including the interconnect line.

30. The electronic system of claim 29, wherein at least one of the controller, the memory device, and the shift register further comprises a discharge structure and a contact line electrically connecting the funnel device to the discharge device.

31. An interference prevention method, comprising: Preventing memory cell interference in a system including a controller, memory device, and shift register involves using a funnel device comprising interconnects directly electrically coupled to multiple electrodes to drain at least a portion of excess charge from the multiple electrodes of the multiple memory cells in the controller, the memory device, or the shift register, the multiple electrodes being at least partially electrically isolated from each other.

32. The interference prevention method of claim 31, further comprising discharging at least a portion of the excess charge onto a substrate on which the plurality of memory cells are formed.

33. The interference prevention method of claim 31, wherein using the funnel device includes using a resistive interconnect, the resistive interconnect including the interconnect and having a resistance selected to drain at least a portion of excess charge from the plurality of electrodes without electrically short-circuiting the plurality of electrodes to each other.

34. A memory device comprising: A plurality of memory cells arranged in rows and columns, each of the plurality of memory cells having an electrode that is at least partially electrically isolated from the electrodes of other memory cells in the plurality of memory cells; as well as Multiple funnel devices, each including interconnects directly electrically coupled to each electrode within a corresponding row of the multiple memory cells, and configured to discharge at least a portion of excess charge from the electrically coupled electrodes within the rows of the multiple memory cells.

35. The memory device of claim 34, wherein all of the electrodes in the plurality of memory cells are coupled to one of the plurality of funnel devices.

36. The memory device of claim 34, wherein the electrodes of the selected memory cells of the plurality of memory devices are all coupled to one of the plurality of funnel devices.

37. The memory device of claim 34, wherein each of the plurality of funnel devices includes a resistive interconnect, the resistive interconnect including the interconnect line.

38. The memory device of claim 37, comprising: A substrate on which the plurality of memory cells are formed; as well as The contact line is directly coupled between the resistive interconnect of the plurality of funnel devices and the substrate.

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