Reconfigurable intelligent memory chip

Abstract

The application provides a reconfigurable intelligent storage chip, which comprises a security kernel and cache circuit, a reconfigurable encryption control logic circuit and a storage unit array; the security kernel and cache circuit are used for receiving a configuration instruction carrying a configuration flag, and configuring a connection path between hardware units of the reconfigurable encryption control logic circuit according to the configuration instruction; the reconfigurable encryption control logic circuit is used for receiving a write command, a write address and to-be-written data, performing encryption calculation on the to-be-written data by using the configured hardware units to obtain encrypted data, writing the encrypted data into the storage unit array, and / or receiving a read command and a read address, reading target data in the storage unit array, and performing decryption calculation on the target data by using the configured hardware units. The application realizes a reconfigurable intelligent storage chip structure, supports flexible expansion of computing power, and improves the flexibility and versatility of the chip.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a reconfigurable smart memory chip. Background Technology

[0002] Most chips in the current technology are system-on-chips (SoCs) with complete functions. Figure 1 An example of a System-on-a-Chip (SoC) is shown, including an LTE analog radio frequency unit (currently, the main mature processes are 55nm and 40nm), a CPU digital unit (advanced processes are 7nm and 5nm), and functional units such as a DSP (mainly mature processes are 28nm and 16nm). Since only one process can be used per wafer, all units except the CPU are forced to migrate from mature processes to higher processes (such as 7nm or 5nm). Some of these units may have better stability under mature processes, so this migration can lead to chip instability and high costs. Furthermore, chips need to continue migrating to higher processes every 18 months (according to the industry's typical upgrade pattern), resulting in the inability to reuse past chips and causing significant waste.

[0003] Application-Specific Integrated Circuit (ASIC) chips, as we know them today, are integrated circuits designed and manufactured to meet the specific requirements of a particular user and the needs of a particular electronic system. It can be seen that ASIC chips are geared towards the needs of specific users. Compared with general-purpose integrated circuits, ASIC chips offer advantages such as smaller size, lower power consumption, improved reliability, higher performance, enhanced security, and lower cost during mass production. However, because ASIC chips are designed for specific user needs, their disadvantages include a lack of flexibility and poor versatility. Summary of the Invention

[0004] At least one embodiment of this application provides a reconfigurable smart memory chip, which uses chip cells with different manufacturing processes to realize a reconfigurable smart memory chip structure, supports flexible expansion of computing power, and improves the flexibility and versatility of the chip.

[0005] To solve the above-mentioned technical problems, this application is implemented as follows:

[0006] This application provides a reconfigurable smart storage chip, including: a security kernel and cache circuit, a reconfigurable encryption control logic circuit, and a storage cell array. The reconfigurable encryption control logic circuit includes multiple hardware units; wherein:

[0007] The reconfigurable encryption control logic circuit is configured to receive a configuration instruction carrying a configuration flag, configure the connection path between the hardware units of the reconfigurable encryption control logic circuit to form a computing path according to the configuration instruction; and use the computing path to encrypt the data to be written to the storage unit array to obtain encrypted data, and / or to decrypt the data read from the storage unit array to obtain decrypted data.

[0008] The security kernel and cache circuit are used to cache at least one of the encrypted data, decrypted data, read commands, and write commands exchanged between the reconfigurable encryption control logic circuit and the storage unit array.

[0009] Optionally, the reconfigurable encryption control logic circuit is further configured to receive a write command, a write address, and data to be written; utilize the computing path formed by the configured hardware units to perform encryption calculations on the data to be written to obtain encrypted data; write the encrypted data to the storage unit array; and / or receive a read command and a read address to read target data from the storage unit array; utilize the computing path formed by the configured hardware units to perform decryption calculations on the target data to obtain decrypted data.

[0010] Optionally, the security kernel and cache circuitry include: an input / output cache, a command register, and an address register;

[0011] The input / output buffer is used to buffer input / output data between the storage cell array and the reconfigurable cryptographic control logic circuit;

[0012] The reconfigurable encryption control logic circuit is also used when the received chip selection CE signal is in the selected state:

[0013] The address data is received from the DQ data bus and sent to the address register. The address data is either a read address or a write address, and the address data is latched in the address register according to the received address latch enable ALE signal.

[0014] The system receives operation commands from the DQ data bus and sends them to the command register. It also latches the operation commands cached in the command register according to the received command latch enable (CLE) signal. The operation commands are either read commands or write commands.

[0015] According to the read command and read address, the target data in the storage unit array is read, and the target data is decrypted using the configured hardware unit to obtain decrypted data; or, the data to be written is received from the DQ data bus, the data to be written is encrypted using the configured hardware unit to obtain encrypted data, and the encrypted data is written to the storage unit array according to the write command and write address.

[0016] Optionally, the security kernel and cache circuitry further include:

[0017] An erase and high-voltage control circuit is used to erase data in the memory cell array under the control of a reconfigurable encryption control logic circuit.

[0018] Optionally, the reconfigurable encryption control logic circuit and the security kernel and cache circuit are disposed in the control core, and the storage cell array is formed by vertically stacking at least one storage sub-core;

[0019] The control core includes:

[0020] The control core includes a front external interface, a core control circuit connected to the front external interface, a back interface connected to the core control circuit, and a back connection layer connected to the back interface; wherein the core control circuit includes the reconfigurable encryption control logic circuit and the security kernel and cache circuit.

[0021] The rear interface includes a bus connection and bus expansion circuit connected to the core control circuit, a core rear external connection interface connected to the bus connection and bus expansion circuit, and a core internal connection interface connected to the core control circuit. The core front external connection interface and the core rear external connection interface are both equipped with an anti-static protection circuit and a physical conversion unit from digital signal to analog signal. The core internal connection interface is not equipped with the anti-static protection circuit and the physical conversion unit.

[0022] The back-side connection layer of the mother core is a perforated connection layer that connects to the mother core inline interface and the mother core back-side outline interface. It is used to connect the mother core back-side outline interface to the physical interface of an external chip through the formed perforations, and / or to connect the mother core inline interface to the front-side inline interface of the storage chip.

[0023] The storage sub-core includes:

[0024] The storage sub-core has a front inline interface, a storage function circuit connected to the inline interface, a back inline interface connected to the storage function circuit, and a back connection layer connected to the back inline interface.

[0025] Neither the front inline interface nor the back inline interface of the sub-core is equipped with an anti-static protection circuit or a physical conversion unit for digital signals to analog signals.

[0026] The front inline interface of the sub-core is used to connect to the back inline interface of another storage sub-core, or to connect to the back inline interface of the control mother core through the back connection layer of the control mother core.

[0027] The sub-core back-side connection layer is a perforated connection layer that connects to the sub-core back-side inline interface, and is used to connect the sub-core back-side inline interface to the sub-core front-side inline interface of another storage sub-core through the formed perforations.

[0028] Optionally, when the first storage sub-core is vertically stacked on top of the control core, the core inline interface of the control core is connected to the sub-core front inline interface of the first storage sub-core.

[0029] When the second memory chip is vertically stacked on top of the first memory chip, the inline interface on the back of the first memory chip is connected to the inline interface on the front of the second memory chip.

[0030] Optionally, the external interface on the front side and / or the external interface on the back side of the mother core are connected to an external chip via a metal ball-mounting process or a metal wire connection.

[0031] Optionally, the back-side inline interface of the mother core is connected to the front-side inline interface of the storage daughter core through a through-silicon via (TSV) or metal bonding process formed on the back-side connection layer of the mother core.

[0032] Optionally, the core control circuit further includes:

[0033] An interface multiplexing and interface safety control circuit for controlling the connection to the external interface on the front side and / or the external interface on the back side of the core.

[0034] Optionally, the security kernel employs a specific instruction set for encryption operations and security control, wherein the specific instruction set is an instruction system with automatic loading random noise; the security kernel includes a low-frequency automatic suppression structure, an anti-abrasion sensor and a self-destruct device, and uses a scrambled encryption bus to protect loading instructions and data.

[0035] Optionally, the external interface on the back of the female core is connected to the interface multiplexing and switching and interface safety control circuit via a bus connection and bus expansion circuit.

[0036] The internal interface of the mother core is connected to the security kernel and cache circuit in the mother core control circuit.

[0037] Optionally, the core control circuit further includes:

[0038] The power management circuit is used to manage the power supply to the memory chip and external chips.

[0039] Optionally, the back-side inline interface of the mother core is connected to the front-side inline interface of the storage daughter core through a through-silicon via (TSV) formed on the back-side connection layer of the mother core or through metal bonding.

[0040] Optionally, the back-side external interface of the sub-core is connected to the front-side internal interface of another storage sub-core through a through-silicon via (TSV) or metal bonding process formed on the back-side connection layer of the sub-core.

[0041] Optionally, the external chip includes at least one of the following chips: a security encryption chip for implementing specific security encryption and decryption functions, a specific algorithm chip for implementing specific algorithm operations, and a storage control chip for implementing specific storage control functions.

[0042] Optionally, the security kernel, cache circuit, and reconfigurable encryption control logic circuit are housed in an interface control chip, and the storage cell array includes at least one storage cell chip; wherein,

[0043] The interface control chip and the memory unit chip are fabricated using different process technologies.

[0044] The reconfigurable smart storage chip is formed by three-dimensionally connecting the storage unit chip and the interface control chip through a three-dimensional stacking process.

[0045] The interface control chip uses a different manufacturing process than the storage unit chip. In addition to having a standard data transmission interface and data encryption function, it also has one or more functions such as data error correction, data compression, clock retiming, and data transmission acceleration. The data encryption function includes a data channel encryption function that uses key data that changes synchronously with the external control system to scramble the transmitted data.

[0046] The memory cell chip type is one or more of the following: NOR memory chip, 3D NOR memory chip, NAND memory chip, 3D NAND memory chip, DRAM memory chip, and low-power DRAM memory chip.

[0047] Optionally, when there is only one memory cell chip, the three-dimensional stacking process refers to the interface control chip being packaged with top metal bumps using the FlipChip process, and then flipped to connect with the memory cell chip; when the metal bumps of the interface control chip cannot completely correspond to the connection points of the memory cell chip, the connection points are first redistributed and arranged through the RDL redistribution layer so that the connection points of the memory cell chip can completely match the metal bumps of the interface control chip.

[0048] Optionally, when there are multiple memory cell chips of the same type, the three-dimensional stacking process refers to first vertically connecting each memory cell chip through a through-silicon via (TSV) to form a single memory cell chip, then using the FlipChip process to perform top bump encapsulation of the interface control chip, and then flipping it to connect with the single memory cell chip.

[0049] Optionally, when there are multiple memory cell chips of different types, the three-dimensional stacking process refers to connecting all the chips, which are arranged vertically and slightly staggered, to an overall base through metal wire connections.

[0050] Optionally, the data error correction function, in addition to basic error correction implemented through hardware, also includes auxiliary error correction through an external controller.

[0051] Optionally, the channel encryption function means that the external controller and the interface control chip both have a pre-set synchronization key or parameters. When the key and parameters are synchronized, no other additional instructions are required to complete the efficient data channel encryption function through streaming encryption.

[0052] Optionally, the data transmission acceleration function includes data preloading and multi-channel data transmission acceleration functions.

[0053] Optionally, the interface control chip has a reconfigurable unit control function; the reconfigurable unit can quickly reconfigure the connection of hardware units through the control instructions of the interface control chip to realize the function of a specific hardware coprocessor, and the connection reconfiguration of the hardware units can be changed only once or can be changed dynamically multiple times.

[0054] Optionally, one or more cores of the interface control chip are implemented using the LoongArch instruction set.

[0055] Optionally, when the storage unit chip includes both DRAM and 3D NAND chips, the interface control chip supports hierarchical storage. With backup power available, during power-on, data is preferentially stored in the DRAM chip. Only when the DRAM chip is about to be full or a power failure occurs will some or all of the data in the DRAM chip be written to the 3D NAND chip. This maximizes the lifespan and speed advantages of the DRAM chip and reduces wear and tear on the 3D NAND chip.

[0056] Compared with the prior art, the reconfigurable smart memory chip provided in this application connects the control master chip and the memory sub-chip through the inter-chip inline interface, and the control master chip has a reconfigurable encryption control logic circuit. It adopts chip units with different processes to realize a stacked reconfigurable smart memory chip structure. This reconfigurable smart memory chip can achieve a computing efficiency comparable to ASIC chips, while reducing chip cost, improving stability, and supporting flexible expansion of computing power, thus improving the chip's flexibility and versatility. Attached Figure Description

[0057] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0058] Figure 1 An example diagram of a prior art SOC;

[0059] Figure 2 This is a schematic diagram of a reconfigurable smart storage chip according to an embodiment of this application;

[0060] Figure 3 This is a schematic diagram of the structure of a control core according to an embodiment of this application;

[0061] Figure 4 This is a schematic diagram of the connection relationship of the rear interface in an embodiment of this application;

[0062] Figure 5 This is a schematic diagram illustrating the connection relationship of an external interface according to an embodiment of this application;

[0063] Figure 6 This is a schematic diagram of a structure of the back-side connection layer of the female core according to an embodiment of this application;

[0064] Figure 7 This is a schematic diagram of a storage sub-core according to an embodiment of this application;

[0065] Figure 8 This is a schematic diagram of another structure of the reconfigurable smart memory chip according to an embodiment of this application;

[0066] Figure 9 This is a schematic diagram of another structure of the reconfigurable smart memory chip according to an embodiment of this application;

[0067] Figure 10 This is an example diagram illustrating the connection between the reconfigurable smart memory chip and multiple sub-chips and existing chips according to an embodiment of this application. Detailed Implementation

[0068] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0069] The terms “first,” “second,” etc., used in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. The terms “and / or” in the specification and claims indicate at least one of the connected objects.

[0070] The following description provides examples and is not intended to limit the scope, applicability, or configuration set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the spirit and scope of this disclosure. Various procedures or components may be appropriately omitted, substituted, or added to the examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with reference to certain examples may be combined in other examples.

[0071] This application provides a reconfigurable smart storage chip, comprising: a security kernel and cache circuit, a reconfigurable encryption control logic circuit, and a storage cell array, wherein the reconfigurable encryption control logic circuit includes multiple hardware units; wherein:

[0072] The reconfigurable encryption control logic circuit is configured to receive a configuration instruction carrying a configuration flag, configure the connection path between the hardware units of the reconfigurable encryption control logic circuit to form a computing path according to the configuration instruction; and use the computing path to encrypt the data to be written to the storage unit array to obtain encrypted data, and / or to decrypt the data read from the storage unit array to obtain decrypted data.

[0073] The security kernel and cache circuit are used to cache at least one of the encrypted data, decrypted data, read commands, and write commands exchanged between the reconfigurable encryption control logic circuit and the storage unit array.

[0074] Specifically, the reconfigurable encryption control logic circuit is also used to receive a write command, a write address, and data to be written; utilize the computing path formed by the configured hardware units to perform encryption calculations on the data to be written to obtain encrypted data; write the encrypted data to the storage unit array; and / or, receive a read command and a read address, read the target data in the storage unit array, and utilize the computing path formed by the configured hardware units to perform decryption calculations on the target data to obtain decrypted data.

[0075] In this embodiment, the reconfigurable encryption control logic circuit may include a built-in memory (with a small storage capacity) to store relevant configuration instructions. Since the configuration instructions for the reconfigurable encryption control logic circuit may be very long, to speed up configuration, the complete configuration instructions can be pre-stored in the storage cell array and assigned a flag or number. During configuration, the reconfigurable encryption control logic circuit receives the flag or number of the configuration instructions, reads the configuration instructions from the storage cell array based on the flag or number, and then configures the connection paths between the hardware units of the reconfigurable encryption control logic circuit to form a computational path.

[0076] Figure 2 A schematic diagram of a reconfigurable smart memory chip according to an embodiment of this application is provided.

[0077] Specifically, the security kernel and cache circuit may include:

[0078] Input / output buffers, command register, address register;

[0079] The input / output buffer is used to buffer input / output data between the storage cell array and the reconfigurable cryptographic control logic circuit; the input / output data includes encrypted data to be written to the storage cell array and target data read from the storage cell array.

[0080] The reconfigurable encryption control logic circuit is also used when the received chip selection CE signal is in the selected state:

[0081] The address data is received from the DQ data bus and sent to the address register. The address data is either a read address or a write address, and the address data is latched in the address register according to the received address latch enable ALE signal.

[0082] The system receives operation commands from the DQ data bus and sends them to the command register. It also latches the operation commands cached in the command register according to the received command latch enable (CLE) signal. The operation commands are either read commands or write commands.

[0083] According to the read command and read address, the target data in the storage unit array is read, and the target data is decrypted using the configured hardware unit to obtain decrypted data; or, the data to be written is received from the DQ data bus, the data to be written is encrypted using the configured hardware unit to obtain encrypted data, and the encrypted data is written to the storage unit array according to the write command and write address.

[0084] Optionally, the security kernel and cache circuitry further include:

[0085] An erase and high-voltage control circuit is used to erase data in the memory cell array under the control of a reconfigurable encryption control logic circuit.

[0086] In other words, reconfigurable cryptographic control logic circuits can control the writing or erasing of specific memory cells in a memory cell array.

[0087] In this embodiment of the application, the computing path is implemented in the following manner:

[0088] First, input the configuration command to configure the specific connection of the reconfigurable encryption control logic circuit to form a hardware unit, thereby implementing a specific operation mode (operation function or operation path). Until a new configuration command is received, the reconfigurable encryption control logic circuit retains the most recently configured specific operation mode, and the input data will be automatically processed according to the currently configured operation mode (e.g., encryption / decryption).

[0089] Optionally, the reconfigurable encryption control logic circuit and the security kernel and cache circuit can be set in the control core, and the storage cell array is formed by vertically stacking at least one storage sub-core.

[0090] In this embodiment, the reconfigurable smart memory chip can be composed of a master control CMOS circuit, multiple memory cell sub-chips (memory cell arrays), and existing chips. Existing chips include security encryption chips, algorithm chips, and control chips. The master control chip is characterized by including reconfigurable encryption control logic, capable of dynamically reconfiguring the circuit to implement different encryption control logics. Existing chips can specifically include one or more of the following types:

[0091] 1. Security encryption chip, used for specific security encryption and decryption functions;

[0092] 2. Specific algorithm chips: used for specific computing functions;

[0093] 3. Storage control chip: used for specific storage control functions.

[0094] The specific security encryption / decryption function, specific computing function, and specific storage control function mentioned here refer to a certain predetermined or preset function.

[0095] Based on the reconfigurable smart storage chip described in this application, a working process for the chip is provided, which may specifically include the following steps:

[0096] 1. External access devices first select the reconfigurable smart storage chip via the Chip Select (CE) signal.

[0097] 2. External access devices send address data to the data queue (DQ) bus and then latch the address through the address latch enable (ALE) signal.

[0098] 3. External access devices send operation commands to the DQ data bus and then latch the commands through the CommandLatch Enable (CLE) signal.

[0099] 4. The reconfigurable smart memory chip responds to commands and continues to receive data or return response signals via the DQ data bus.

[0100] 5. External access devices send data to the reconfigurable encryption control logic via the DQ bus signal and the bidirectional data strobe (DQS) synchronization signal.

[0101] 6. The reconfigurable encryption control logic performs data encryption and decryption operations based on the configured parameters.

[0102] Figure 2 middle:

[0103] The R / B# signal indicates the status of the reconfigurable smart memory chip, such as busy or idle state.

[0104] The WE signal indicates write enable, allowing data to be written to the reconfigurable smart memory chip.

[0105] The RE signal indicates read enable, allowing data to be read from the reconfigurable smart memory chip.

[0106] The WP# signal indicates that the reconfigurable smart memory chip is write-protected, meaning it can only read data and cannot write data.

[0107] The reconfigurable intelligent encryption control logic circuit can update its internal encryption / decryption parameters and operation methods in response to external configuration commands. Furthermore, the reconfigurable intelligent encryption control logic can connect to existing chips via a data bus to achieve more complex functions.

[0108] Depending on actual needs, the control master chip, storage daughter chip, and existing chips in this application embodiment can be multiple of each type, and their connection relationships can be arbitrarily stacked. After completing a complete packaging module, the packaging modules can be further stacked using the POP process.

[0109] Reconfigurable encryption control logic circuits have the characteristics of dual software and hardware programming. The hardware architecture and functions change dynamically in real time as the software changes, so they can also be called software-defined chips.

[0110] Reconfigurable encryption control logic circuits are configured at runtime to adjust hardware functions. Based on the characteristics of the data flow, the configured hardware units are interconnected to form relatively fixed computational paths, performing data-driven computations in a manner similar to ASIC (Application-Specific Integrated Circuit). The reconfigurable encryption control logic circuit can be configured to different functions at different times, thus performing data-driven ASIC computations. When the algorithm and application change, the hardware can be reconfigured again to execute different computational paths.

[0111] Here, the configuration is achieved through a cache in the reconfigurable encryption control logic circuit (i.e., the reconfigurable encryption control logic circuit may include built-in memory). The cache contents indicate how to configure the execution path of the hardware unit, thereby enabling the transformation of the data operation path through hardware programming. The data stream refers to the data group with configuration flags sent by the external device. The security kernel selects the corresponding configuration parameters according to the configuration flags to configure the reconfigurable encryption control logic circuit, and then delivers the data to the configured reconfigurable encryption control logic circuit for operation.

[0112] As can be seen from the embodiments of this application, there are many hardware units with variable connection paths in the reconfigurable encryption control logic circuit. By changing the connection relationship of the hardware units, new computing paths can be formed.

[0113] Traditional memory chips are typically instruction-driven, meaning the hardware units and their connections remain fixed. They use fixed instructions and data formats, programmed into software, for computation by the hardware units. Instructions are executed one by one in a pipeline, offering good versatility but low efficiency. In contrast, the reconfigurable smart memory chip of this application implements the functions originally implemented in software through the reorganization of hardware units. It eliminates the need for sequential execution of software instructions; instead, the entire hardware unit performs the task synchronously. Therefore, it avoids the latency and energy consumption of instruction fetching and decoding operations inherent in traditional instruction-driven computing architectures, resulting in high computational efficiency. Furthermore, it can execute computations in a manner approaching that of ASIC dedicated circuits. Because it executes based on configuration, its execution efficiency is comparable to ASICs, but its flexibility is far superior. Moreover, the computing power of the reconfigurable smart memory chip can be flexibly expanded, making it suitable for edge scenarios with combined requirements for high energy efficiency and flexibility.

[0114] The specific structures of the control core and the storage core are provided below.

[0115] like Figure 3 As shown, the control core in this embodiment includes:

[0116] The control core includes a front external interface, a core control circuit connected to the front external interface, a back interface connected to the core control circuit, and a back connection layer connected to the back interface; wherein the core control circuit includes the reconfigurable encryption control logic circuit and the security kernel and cache circuit.

[0117] Optionally, the internal interface of the mother core may specifically include a digital interface and / or a power interface. The security kernel uses a specific instruction set for encryption operations and security control, wherein the specific instruction set is an instruction system with automatic loading of random noise; the security kernel includes a low-frequency automatic suppression structure, an anti-wear sensor, and a self-destruct device, and uses a scrambled encryption bus to protect the loaded instructions and data.

[0118] In this embodiment of the application, the core control circuit may further include the following circuits:

[0119] An interface multiplexing and interface safety control circuit for controlling the connection to the external interface on the front side and / or the external interface on the back side of the core;

[0120] The power management circuit is used to manage the power supply to the memory chip and external chips.

[0121] like Figure 4 As shown, the rear interface includes a bus connection and bus expansion circuit connected to the mother core control circuit, a mother core rear external interface connected to the bus connection and bus expansion circuit, and a mother core internal interface connected to the mother core control circuit. The mother core front external interface and the mother core rear external interface are both equipped with anti-static protection circuits and physical conversion units from digital signals to analog signals. The mother core internal interface is not equipped with the anti-static protection circuits and physical conversion units.

[0122] Figure 4 In the provided connection diagram of the mother core's rear interface, the external interface on the mother core's rear side is connected to the interface multiplexing switching and interface security control circuit via a bus connection and bus expansion circuit. The internal interface of the mother core is connected to the security core and cache circuit in the mother core control circuit.

[0123] Figure 5A schematic diagram of an external interface (such as a front external interface and a back external interface of the female core) is provided. Specifically, the external interface includes an anti-static protection interface, which is equipped with an anti-static protection circuit. In addition, to achieve interface signal conversion, the external interface also includes a physical conversion unit connected to the anti-static protection interface.

[0124] like Figure 6 As shown, the back connection layer of the mother core is a perforated connection layer that connects to the mother core inline interface and the mother core back external connection interface. It is used to connect the mother core back external connection interface to the physical interface of an external chip through the formed perforations, and / or to connect the mother core inline interface to the front inline interface of the storage chip.

[0125] Figure 6 In the provided diagram illustrating the connection relationships of the back-side connection layer of the mother chip, the external interface and the internal interface of the mother chip are connected to the back-side connection layer of the mother chip, respectively. The back-side connection layer of the mother chip can form multiple through-silicon vias (TSVs) as needed. Thus, the external interface of the mother chip can be coupled to the physical interface of an external chip through the TSVs, and the internal interface of the mother chip can be coupled to the front-side internal interface of the storage chip through the TSVs.

[0126] It should be noted that the "back side" and "front side" mentioned in this article refer to two opposing surfaces of the chip. For example, the front side of the control chip can be the surface connected to the base, and the back side of the control chip can be the surface connected to the storage chip. The external chip can be any existing chip with complete interfaces and functional circuits.

[0127] Specifically, the internal interface of the mother core includes a digital interface and / or a power interface.

[0128] The external interface on the front side and / or the external interface on the back side of the mother core can be connected to an external chip via a metal ball-mounting process or a metal wire connection.

[0129] The back-side inline interface of the mother core can be connected to the front-side inline interface of the storage daughter core through a through-silicon via (TSV) formed on the back-side connection layer of the mother core or through metal bonding.

[0130] like Figure 7 As shown, the storage sub-chip in this application embodiment can also be called a smart sub-chip or simply a sub-chip, and specifically includes:

[0131] The storage sub-core has a front inline interface, a storage function circuit connected to the inline interface, a back inline interface connected to the storage function circuit, and a back connection layer connected to the back inline interface.

[0132] Neither the front inline interface nor the back inline interface of the sub-core is equipped with an anti-static protection circuit or a physical conversion unit for digital signals to analog signals.

[0133] The front inline interface of the sub-core is used to connect to the back inline interface of another storage sub-core, or to connect to the back inline interface of the control mother core through the back connection layer of the control mother core.

[0134] The sub-core back-side connection layer is a perforated connection layer that connects to the sub-core back-side inline interface, and is used to connect the sub-core back-side inline interface to the sub-core front-side inline interface of another storage sub-core through the formed perforations.

[0135] In this embodiment of the application, when the first storage sub-core is vertically stacked on top of the control core, the core inline interface of the control core is connected to the sub-core front inline interface of the first storage sub-core.

[0136] When the second memory chip is vertically stacked on top of the first memory chip, the inline interface on the back of the first memory chip is connected to the inline interface on the front of the second memory chip.

[0137] Here, the first memory chip and the second memory chip are different memory chips, and these memory chips can all have the same structure.

[0138] Specifically, the back-side inline interface and the front-side inline interface of the sub-core may each include a digital interface and / or a power interface.

[0139] The back-side inline interface of the mother core can be connected to the front-side inline interface of the storage daughter core through a through-silicon via (TSV) formed on the back-side connection layer of the mother core or through metal bonding.

[0140] The back-side external interface of the sub-core is connected to the front-side internal interface of another storage sub-core through a through-silicon via (TSV) formed on the back-side connection layer of the sub-core or by a metal bonding process.

[0141] Furthermore, this application does not impose specific limitations on the planar area relationship between the two chips in the stacked arrangement. For example, the planar area of ​​the control chip can be greater than, equal to, or less than the planar area of ​​the memory chip stacked on top of it. As another example, the planar area of ​​the first memory chip can be greater than, equal to, or less than the planar area of ​​the memory chips stacked on top of it.

[0142] During design and manufacturing, the female core is positioned with its front side facing up. After encapsulation, the female core is positioned with its front side facing down to connect with the external base.

[0143] Depending on actual needs, one or more of each type of chip, including the sub-chip and existing chips, can be used, and their connections can be arbitrarily stacked. After completing a full package module, the package modules can be stacked again using the POP process.

[0144] Based on the above reconfigurable smart memory chip structure, the embodiments of this application can realize the master control circuit on the master control chip using mature processes at low cost. Furthermore, chip units of different processes can be reused, resulting in a reduction in overall chip cost, improved reliability, and a shortened development cycle. This is because the memory sub-chips can continue to utilize existing mature processes and be directly stacked on the smart master chip, thereby significantly improving development efficiency. In addition, the embodiments of this application enable the stacking of the master control chip and multiple memory sub-chips to surpass the performance of a single high-process SOC chip using low-process technology, even without high-process equipment.

[0145] To help better understand the structure of the integrated circuit components in the embodiments of this application, the following description uses an exemplary structure.

[0146] Figure 8 The reconfigurable smart memory chip shown includes a control master chip and multiple memory sub-chips 1 to n. The control master chip is located at the lowest layer of the stacked structure, with memory sub-chips 1 to n stacked on top of it. The control master chip can be connected to the front inline interface of memory sub-chip 1 through its master chip inline interface. The connection between adjacent sub-chips is that the back inline interface of the lower-layer sub-chip is connected to the front inline interface of the upper-layer sub-chip.

[0147] Figure 9 Further examples of connections between the control core and multiple memory chips, as well as multiple existing chips, are provided. The control core is connected to the chip substrate via metal balls or metal wires. The front external interface of the control core includes an anti-static protection circuit and a physical conversion unit. The control core also includes a core control circuit, bus connection and expansion circuitry. These circuits are connected to the back external interface, the internal interface, and the front external interface. A back connection layer (perforated connection layer) is located inside the control core near the back side. Through perforations formed in this back connection layer, the back external interface is connected to the chip external interface of an existing chip, and / or, the internal interface is connected to the front internal interface of a memory chip.

[0148] In addition, the smart sub-chip includes storage function circuitry, a sub-chip back-side interconnect interface, and a sub-chip back-side connection layer. The sub-chip back-side interconnect interface connects to the sub-chip front-side interconnect interface of another smart sub-chip through a perforation formed in the sub-chip back-side connection layer.

[0149] In this embodiment, a through-hole can be formed in the back connection layer of the mother core, and copper metal can be deposited on the inner surface of the hole. The hole extends to the back surface of the mother core, where metal can be plated or solder balls can be added. The front internal interface of the daughter core can be directly connected to the metal or solder balls plated on the back of the mother core.

[0150] For example, the core control circuit may specifically include an interface multiplexing switching control circuit and an interface safety control circuit.

[0151] For example, the security kernel described in this application embodiment can employ a security kernel with a specific instruction set (typically, such as LoongArch, China's first independently developed instruction set) for encryption operations and security control. The security kernel uses an instruction set with auto-loading random noise, enabling it to resist logic analysis and DPA probing. It employs a low-frequency automatic suppression structure to prevent low-frequency analysis, uses anti-grinding sensors and self-destruct devices to prevent chip grinding detection, and uses a scrambled encryption bus to protect loading instructions and data. Other modules built into the security kernel include built-in memory and an encryption coprocessor. The control circuit based on the security kernel can achieve secure startup and operation. The security kernel can also perform security verification based on random numbers and authentication requests issued by the security controller in an external service platform or terminal, using these as security control conditions to control the interface multiplexing switching and on / off states of the chip's external and internal interfaces.

[0152] Figure 10 An example diagram is provided showing the connection between the control master chip and multiple memory daughter chips and existing chips according to an embodiment of this application, wherein:

[0153] The external interface 100 on the front of the control core 101 can be connected to the chip base.

[0154] A TSV semi-through hole 102 is formed in the control core 101. Through the TSV semi-through hole 102, the external interface on the back of the core can be connected to the physical interface of the external chip 120, and / or the internal interface of the core can be connected to the internal interface on the front of the storage core 118, such as the pin 107 connected to the internal interface on the front of the storage core 118.

[0155] Figure 10 In the process, the TSV semi-perforated 102 has a TSV perforated metal bump 103 formed on the back connection layer of the mother core, and the TSV perforated metal bump 103 can be connected to the metal distribution connection layer 104 of the mother core.

[0156] The control core 101 and the storage core 118 are metal bonded together by metal pillars 105 and 106.

[0157] A TSV semi-through hole 108 is formed in the storage sub-core 118. Through the TSV semi-through hole 108, the external interface on the back of the sub-core can be connected to the pin 113 of the internal interface on the front of the smart sub-core 119. A TSV semi-through hole 108 forms a TSV through-hole metal bump 109 on the connection layer on the back of the sub-core. Through the TSV through-hole metal bump 109, a connection can be formed with the metal distribution connection layer 110 of the sub-core.

[0158] Storage cores 118 and 119 are metal-bonded by metal pillars 111 and 112. Storage core 119 also includes: a TSV half-perforation 114, a TSV perforated metal bump 115 of the core back connection layer, a metal distribution connection layer 116, and a metal pillar 117 for metal bonding.

[0159] The reconfigurable smart storage chip provided in this application embodiment can also be used to implement a self-correcting smart storage chip.

[0160] Specifically, the security kernel, cache circuit, and reconfigurable encryption control logic circuit are housed in an interface control chip, and the storage unit array includes at least one storage unit chip; wherein,

[0161] The interface control chip and the memory unit chip are fabricated using different process technologies.

[0162] The reconfigurable smart storage chip is formed by three-dimensionally connecting the storage unit chip and the interface control chip through a three-dimensional stacking process.

[0163] The interface control chip uses a different manufacturing process than the storage unit chip. In addition to having a standard data transmission interface and data encryption function, it also has one or more functions such as data error correction, data compression, clock retiming, and data transmission acceleration. The data encryption function includes a data channel encryption function that uses key data that changes synchronously with the external control system to scramble the transmitted data.

[0164] The memory cell chip type is one or more of the following: NOR memory chip, 3D NOR memory chip, NAND memory chip, 3D NAND memory chip, DRAM memory chip, and low-power DRAM memory chip.

[0165] Optionally, when there is only one memory cell chip, the three-dimensional stacking process refers to the interface control chip being packaged with top metal bumps using the FlipChip process, and then flipped to connect with the memory cell chip; when the metal bumps of the interface control chip cannot completely correspond to the connection points of the memory cell chip, the connection points are first redistributed and arranged through the RDL redistribution layer so that the connection points of the memory cell chip can completely match the metal bumps of the interface control chip.

[0166] Optionally, when there are multiple memory cell chips of the same type, the three-dimensional stacking process refers to first vertically connecting each memory cell chip through a through-silicon via (TSV) to form a single memory cell chip, then using the FlipChip process to perform top bump encapsulation of the interface control chip, and then flipping it to connect with the single memory cell chip.

[0167] Optionally, when there are multiple memory cell chips of different types, the three-dimensional stacking process refers to connecting all the chips, which are arranged vertically and slightly staggered, to an overall base through metal wire connections.

[0168] Optionally, the data error correction function, in addition to basic error correction implemented through hardware, also includes auxiliary error correction through an external controller.

[0169] Optionally, the channel encryption function means that the external controller and the interface control chip both have a pre-set synchronization key or parameters. When the key and parameters are synchronized, no other additional instructions are required to complete the efficient data channel encryption function through streaming encryption.

[0170] Optionally, the data transmission acceleration function includes data preloading and multi-channel data transmission acceleration functions.

[0171] Optionally, the interface control chip has a reconfigurable unit control function; the reconfigurable unit can quickly reconfigure the connection of hardware units through the control instructions of the interface control chip to realize the function of a specific hardware coprocessor, and the connection reconfiguration of the hardware units can be changed only once or can be changed dynamically multiple times.

[0172] Optionally, one or more cores of the interface control chip are implemented using the LoongArch instruction set.

[0173] Optionally, when the storage unit chip includes both DRAM and 3D NAND chips, the interface control chip supports hierarchical storage. With backup power available, during power-on, data is preferentially stored in the DRAM chip. Only when the DRAM chip is about to be full or a power failure occurs will some or all of the data in the DRAM chip be written to the 3D NAND chip. This maximizes the lifespan and speed advantages of the DRAM chip and reduces wear and tear on the 3D NAND chip.

[0174] The self-correcting intelligent storage chip of this invention, in a specific embodiment, comprises a reconfigurable interface control chip, configurable hardware units, and a storage array unit chip bonded together to form a complete self-correcting intelligent storage chip. The interface control chip simulates the storage chip interface externally. The reconfigurable interface control chip acts as a hardware error correction coprocessor by rapidly reconfiguring the connection of hardware units, enabling direct error correction within the storage chip. From the outside, the self-correcting intelligent storage chip appears to be virtually error-free during operation. For errors that the interface control chip cannot repair, a repair component is installed on the external control system. By reading the uncorrectable error information, the corresponding row, column, or page is hidden or replaced, further improving the efficiency of the storage chip and the product yield.

[0175] Based on the above structure, the embodiments of the present invention involve a self-correcting intelligent memory chip formed by manufacturing interface control chips and memory array unit chips using different processes and then stacking them in three dimensions. By cooperating with the interface control chip with error correction function and the memory array unit chip, even when the memory array unit chip has a small error, the correctness of read and write data can be guaranteed to the maximum extent, the error rate can be reduced, and the difficulty of error correction control of the external main chip can be reduced.

[0176] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0177] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A reconfigurable intelligent memory chip, characterized by, include: The system includes a secure kernel and cache circuitry, a reconfigurable encryption control logic circuitry, and a memory cell array. The reconfigurable encryption control logic circuitry comprises multiple hardware units. The reconfigurable encryption control logic circuit is configured to receive a configuration instruction carrying a configuration flag, configure the connection path between the hardware units of the reconfigurable encryption control logic circuit to form a computing path according to the configuration instruction; and use the computing path to encrypt the data to be written to the storage unit array to obtain encrypted data, and / or to decrypt the data read from the storage unit array to obtain decrypted data. The security kernel and cache circuit are used to cache at least one of the encrypted data, decrypted data, read commands and write commands exchanged between the reconfigurable encryption control logic circuit and the storage unit array; The reconfigurable encryption control logic circuit is also used to receive a write command, a write address and data to be written, use the computing path formed by the configured hardware units to perform encryption calculation on the data to be written to obtain encrypted data, write the encrypted data to the storage unit array, and / or receive a read command and a read address to read the target data in the storage unit array, use the computing path formed by the configured hardware units to perform decryption calculation on the target data to obtain decrypted data. The security kernel and cache circuitry include: an input / output cache, a command register, and an address register; The input / output buffer is used to buffer input / output data between the storage cell array and the reconfigurable cryptographic control logic circuit; The reconfigurable encryption control logic circuit is also used when the received chip selection CE signal is in the selected state: The address data is received from the DQ data bus and sent to the address register. The address data is either a read address or a write address, and the address data is latched in the address register according to the received address latch enable ALE signal. The system receives operation commands from the DQ data bus and sends them to the command register. It also latches the operation commands cached in the command register according to the received command latch enable (CLE) signal. The operation commands are either read commands or write commands. According to the read command and read address, the target data in the storage unit array is read, and the target data is decrypted using the configured hardware unit to obtain decrypted data; or, the data to be written is received from the DQ data bus, the data to be written is encrypted using the configured hardware unit to obtain encrypted data, and the encrypted data is written to the storage unit array according to the write command and write address.

2. The reconfigurable smart memory chip according to claim 1, characterized in that, The security kernel and cache circuitry also include: An erase and high-voltage control circuit is used to erase data in the memory cell array under the control of a reconfigurable encryption control logic circuit.

3. The reconfigurable smart memory chip according to any one of claims 1 to 2, characterized in that, The reconfigurable encryption control logic circuit and the security kernel and cache circuit are set in the control core, and the storage cell array is formed by vertically stacking at least one storage sub-core. The control core includes: The control core includes a front external interface, a core control circuit connected to the front external interface, a back interface connected to the core control circuit, and a back connection layer connected to the back interface; wherein the core control circuit includes the reconfigurable encryption control logic circuit and the security kernel and cache circuit. The rear interface includes a bus connection and bus expansion circuit connected to the core control circuit, a core rear external connection interface connected to the bus connection and bus expansion circuit, and a core internal connection interface connected to the core control circuit. The core front external connection interface and the core rear external connection interface are both equipped with an anti-static protection circuit and a physical conversion unit from digital signal to analog signal. The core internal connection interface is not equipped with the anti-static protection circuit and the physical conversion unit. The back-side connection layer of the mother core is a perforated connection layer that connects to the mother core inline interface and the mother core back-side outline interface. It is used to connect the mother core back-side outline interface to the physical interface of an external chip through the formed perforations, and / or to connect the mother core inline interface to the front-side inline interface of the storage chip. The storage sub-core includes: The storage sub-core has a front inline interface, a storage function circuit connected to the front inline interface, a back inline interface connected to the storage function circuit, and a back connection layer connected to the back inline interface. Neither the front inline interface nor the back inline interface of the sub-core is equipped with an anti-static protection circuit or a physical conversion unit for digital signals to analog signals. The front inline interface of the sub-core is used to connect to the back inline interface of another storage sub-core, or to connect to the back inline interface of the control mother core through the back connection layer of the control mother core. The sub-core back connection layer is a perforated connection layer that connects to the sub-core back inline interface, and is used to connect the sub-core back inline interface to the sub-core front inline interface of another storage sub-core through the formed perforations. When the first storage sub-core is vertically stacked on top of the control core, the core inline interface of the control core is connected to the sub-core front inline interface of the first storage sub-core. When the second memory chip is vertically stacked on top of the first memory chip, the back inline interface of the first memory chip is connected to the front inline interface of the second memory chip. The external interface on the front side and / or the external interface on the back side of the mother core are connected to an external chip through a metal ball-mounting process or a metal wire connection. The back-side inline interface of the mother core is connected to the front-side inline interface of the storage daughter core through a through-silicon via (TSV) or metal bonding process formed on the back-side connection layer of the mother core. The core control circuit also includes: An interface multiplexing and interface safety control circuit for controlling the connection to the external interface on the front side and / or the external interface on the back side of the core.

4. The reconfigurable smart memory chip according to claim 3, characterized in that, The secure kernel employs a specific instruction set for encryption operations and security control, wherein the specific instruction set is an instruction system with automatic loading of random noise; the secure kernel includes a low-frequency automatic suppression structure, a wear-resistant sensor, and a self-destruct device, and uses a scrambled encryption bus to protect loading instructions and data.

5. The reconfigurable smart memory chip according to claim 4, characterized in that, The external interface on the back of the mother core is connected to the interface multiplexing and switching and interface safety control circuit via a bus connection and bus expansion circuit. The mother core inline interface is connected to the security kernel and cache circuit in the mother core control circuit; The core control circuit also includes: Power management circuitry is used for power management of the memory chip and external chips; The back-side inline interface of the mother core is connected to the front-side inline interface of the storage daughter core through a through-silicon via (TSV) or metal bonding process formed on the back-side connection layer of the mother core. The external interface on the back of the sub-core is connected to the internal interface on the front of another storage sub-core through a through-silicon via (TSV) or metal bonding process formed on the connection layer on the back of the sub-core.

6. The reconfigurable smart memory chip according to claim 5, characterized in that, The external chip includes at least one of the following chips: a security encryption chip for implementing specific security encryption and decryption functions, a specific algorithm chip for implementing specific algorithm operations, and a storage control chip for implementing specific storage control functions.

7. The reconfigurable smart memory chip according to claim 1, characterized in that, The secure kernel, cache circuit, and reconfigurable encryption control logic circuit are housed in an interface control chip, and the storage unit array includes at least one storage unit chip; wherein... The interface control chip and the memory unit chip are fabricated using different process technologies. The reconfigurable smart storage chip is formed by three-dimensionally connecting the storage unit chip and the interface control chip through a three-dimensional stacking process. The interface control chip uses a different manufacturing process than the storage unit chip. In addition to having a standard data transmission interface and data encryption function, it also has one or more functions such as data error correction, data compression, clock retiming, and data transmission acceleration. The data encryption function includes a data channel encryption function that uses key data that changes synchronously with the external control system to scramble the transmitted data. The memory cell chip type is one or more of the following: NOR memory chip, 3D NOR memory chip, NAND memory chip, 3D NAND memory chip, DRAM memory chip, and low-power DRAM memory chip.

8. The reconfigurable smart memory chip according to claim 7, characterized in that, When there is only one memory cell chip, the 3D stacking process refers to the interface control chip being packaged with top metal bumps using the FlipChip process, and then flipped to connect with the memory cell chip; when the metal bumps of the interface control chip cannot completely correspond to the connection points of the memory cell chip, the connection points are first redistributed and arranged through an RDL redistribution layer so that the connection points of the memory cell chip can completely match the metal bumps of the interface control chip; When there are multiple memory cell chips of the same type, the three-dimensional stacking process refers to first vertically connecting each memory cell chip through a through-silicon via (TSV) to form a single memory cell chip, then using the FlipChip process to encapsulate the top bump of the interface control chip, and then flipping it to connect with the single memory cell chip. When there are multiple memory cell chips of different types, the three-dimensional stacking process refers to connecting all the chips, which are arranged vertically and slightly staggered, to an overall base through metal wires.

9. The reconfigurable smart memory chip according to claim 8, characterized in that, In addition to basic error correction implemented through hardware, the data error correction function also includes auxiliary error correction through an external controller.

10. The reconfigurable smart memory chip according to claim 9, characterized in that, The channel encryption function refers to the fact that the external controller and the interface control chip both have a pre-set synchronization key or parameters. When the key and parameters are synchronized, no other additional instructions are required to complete the data channel encryption function through streaming encryption.

11. The reconfigurable smart memory chip according to claim 10, characterized in that, The data transmission acceleration function includes data preloading and multi-channel data transmission acceleration functions.

12. The reconfigurable smart memory chip according to claim 11, characterized in that, The interface control chip has a reconfigurable unit control function; the reconfigurable unit can quickly reconfigure the connection of hardware units through the control instructions of the interface control chip to realize the function of a specific hardware coprocessor. The connection reconfiguration of the hardware units can be changed only once or can be changed dynamically multiple times.

13. The reconfigurable smart memory chip according to claim 12, characterized in that, When the storage unit chip includes both DRAM and 3D NAND chips, the interface control chip supports hierarchical storage. With backup power available, during power-on, data is preferentially stored in the DRAM chip. Only when the DRAM chip is about to be full or a power outage occurs will some or all of the data in the DRAM chip be written to the 3D NAND chip.

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