Method for manufacturing trench-type mos device
By forming a silicon oxide layer on the surface of a polycrystalline silicon material layer and removing residues, the problem of abnormal electrical testing of trench-type MOS devices was solved, thereby improving the electrical performance and yield of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG ELECTRONICS (SHAOXING) CORP
- Filing Date
- 2023-02-28
- Publication Date
- 2026-06-19
AI Technical Summary
Trench-type MOS devices are prone to electrical test abnormalities during manufacturing, leading to a decrease in product yield. The main reason is that the trench gate formed by etching has protrusions and poor morphology.
A silicon oxide layer is formed by performing an oxidation process on the surface of a polysilicon material layer. The silicon oxide layer is then removed to open up voids. Residues are removed by a wet cleaning process. Subsequently, the polysilicon material layer is etched to form a trench gate with a good morphology.
It effectively removes residues from the surface of the polycrystalline silicon material layer, avoids or reduces the generation of protrusions, and improves the electrical performance and product yield of trench MOS devices.
Smart Images
Figure CN116013784B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a trench-type MOS device. Background Technology
[0002] In traditional planar MOS (metal-oxide-semiconductor) devices, the source, gate, and drain of the MOS transistor are all located on the horizontal plane of the silicon wafer. This not only occupies a large area but also results in high on-resistance and power consumption, failing to meet the requirements for miniaturization and low power consumption in power devices. In contrast, trench MOS devices cleverly form the gate of the transistor in a trench perpendicular to the surface of the silicon wafer, thereby shifting the conduction channel to the vertical direction of the silicon wafer. This has three advantages: (1) reducing the device area and further increasing the device integration density; (2) effectively reducing on-resistance and power consumption; and (3) essentially eliminating the lateral flow of holes in the P-well, effectively suppressing the latch-up effect. Therefore, trench MOS devices are widely used in power devices.
[0003] However, existing trench MOS devices are prone to electrical test abnormalities, which reduces product yield. Summary of the Invention
[0004] The purpose of this invention is to provide a method for manufacturing a trench MOS device, so as to solve the problem that trench MOS devices are prone to electrical test abnormalities in the prior art.
[0005] To address the aforementioned technical problems, the present invention provides a method for manufacturing a trench-type MOS device, the method comprising:
[0006] A semiconductor substrate is provided, wherein trenches are formed therein; a dielectric layer is covered on the surface of the trenches, the dielectric layer extending to cover the surface of the semiconductor substrate; and a polysilicon material layer is filled in the trenches, the polysilicon material layer extending to cover the surface of the dielectric layer outside the trenches, and voids are formed in the polysilicon material layer.
[0007] A chemical mechanical polishing process is performed on the polycrystalline silicon material layer to remove the polycrystalline silicon material layer on the surface of the dielectric layer outside the trench;
[0008] An oxidation process is performed on the polycrystalline silicon material layer to form a silicon oxide layer on the surface of the polycrystalline silicon material layer;
[0009] Remove the silicon oxide layer to open the void;
[0010] Clean the polycrystalline silicon material layer; and,
[0011] The polysilicon material layer is etched to form a trench gate.
[0012] Optionally, in the method for manufacturing the trench-type MOS device, the steps of performing an oxidation process on the polysilicon material layer to form a silicon oxide layer on the surface of the polysilicon material layer and removing the silicon oxide layer are performed multiple times, wherein the void is opened after at least the last time the step of removing the silicon oxide layer is performed.
[0013] Optionally, in the method for manufacturing the trench-type MOS device, an oxidation process is performed on the polycrystalline silicon material layer using an oxidizing solution to form a silicon oxide layer on the surface of the polycrystalline silicon material layer.
[0014] Optionally, in the method for manufacturing the trench-type MOS device, the oxide solution includes hydrogen peroxide.
[0015] Optionally, in the manufacturing method of the trench-type MOS device, the silicon oxide layer is removed using an etching solution to open the voids.
[0016] Optionally, in the method for manufacturing the trench-type MOS device, the etching solution includes hydrogen fluoride.
[0017] Optionally, in the method for manufacturing a trench-type MOS device, after the step of performing an oxidation process on the polysilicon material layer to form a silicon oxide layer on the surface of the polysilicon material layer, the method for manufacturing a trench-type MOS device further includes performing a first wet cleaning process on the silicon oxide layer.
[0018] After the step of removing the silicon oxide layer to open the voids, the method for manufacturing the trench MOS device further includes performing a second wet cleaning process on the polysilicon material layer.
[0019] Optionally, in the method for manufacturing the trench-type MOS device, the step of cleaning the polycrystalline silicon material layer is performed using a cleaning solution and / or a cleaning gas.
[0020] Optionally, in the method for manufacturing the trench-type MOS device, in the step of removing the silicon oxide layer to open the void, the bottom of the void is lower than the surface of the semiconductor substrate and the top of the void is higher than the surface of the semiconductor substrate.
[0021] Optionally, in the method for manufacturing the trench-type MOS device, in the step of removing the silicon oxide layer to open the void, the top surface of the polysilicon material layer is flush with or lower than the surface of the dielectric layer, and the top surface of the polysilicon material layer is higher than the surface of the semiconductor substrate.
[0022] In the method for manufacturing a trench-type MOS device provided by the present invention, an oxidation process is performed on a polysilicon material layer to form a silicon oxide layer on the surface of the polysilicon material layer; the silicon oxide layer is removed to open the voids; and the polysilicon material layer is cleaned. This effectively removes residues from the surface of the polysilicon material layer, thereby forming a trench-type gate with a good morphology when etching the polysilicon material layer. This avoids / reduces the problem of electrical test abnormalities that are prone to occur in trench-type MOS devices and improves product yield. Attached Figure Description
[0023] Figures 1 to 3 This is a schematic diagram of a manufacturing process for a trench-type MOS device.
[0024] Figure 4 This is a schematic flowchart of a method for manufacturing a trench-type MOS device according to an embodiment of this application.
[0025] Figures 5 to 10 This is a schematic diagram of the manufacturing process of a trench-type MOS device according to an embodiment of this application.
[0026] The reference numerals in the attached figures are explained as follows:
[0027] 100 - Semiconductor substrate; 102 - Trench; 104 - Dielectric layer; 106 - Polysilicon material layer; 108 - Void; 110 - Trench gate; 112 - Bump; 114 - Residue;
[0028] 200 - Semiconductor substrate; 202 - Trench; 204 - Dielectric layer; 206 - Polysilicon material layer; 208 - Void; 210 - Residue; 212 - Silicon oxide layer; 214 - Trench gate. Detailed Implementation
[0029] The manufacturing method of the trench-type MOS device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0030] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined in this application, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise stated, terms such as "front," "rear," "lower," and / or "upper" are for ease of description only and are not limited to a location or spatial orientation. Terms such as "comprising" or "including" indicate that the element or object preceding "comprising" encompasses the element or object listed following "comprising" or its equivalents, and do not exclude other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0031] Trench MOS devices are popular in the industry due to their ability to reduce device area and increase integration density. However, the industry is also troubled by the problem of electrical test anomalies, which reduce product yield. The inventors conducted in-depth research on this issue and found that the main reason for this problem is that the trench gate formed by etching has protrusions and poor morphology, resulting in poor electrical performance and thus making it prone to electrical test anomalies. For details, please refer to... Figures 1 to 3 :
[0032] like Figure 1 As shown, in a method for manufacturing a trench-type MOS device, a semiconductor substrate 100 is provided, in which trenches 102 are formed; a dielectric layer 104 is covered on the surface of the trenches 102, the dielectric layer 104 extending to cover the surface of the semiconductor substrate 100; a polysilicon material layer 106 is filled in the trenches 102, the polysilicon material layer 106 extending to cover the surface of the dielectric layer 104 outside the trenches 102, and voids 108 are formed in the polysilicon material layer 106.
[0033] like Figure 2As shown, a chemical mechanical polishing process is then performed on the polycrystalline silicon material layer 106 to remove the polycrystalline silicon material layer 106 from the surface of the dielectric layer 104 outside the trench 102.
[0034] Next, as Figure 3 As shown, the polysilicon material layer 106 is etched to form a trench gate 110. As... Figure 3 As shown, a protrusion 112 is formed on the surface of the trench gate 110 formed by the above process, which makes the morphology of the trench gate 110 poor, resulting in poor electrical performance and causing problems such as easy occurrence of abnormal electrical tests.
[0035] Further research by the inventors revealed that the reason for the protrusion 112 on the surface of the formed trench gate 110 is that when the polysilicon material layer 106 is subjected to a chemical mechanical polishing process, the polishing fluid will seep into the cavity 108 to form a residue 114. As a result, when the polysilicon material layer 106 is etched, the polysilicon material layer 106 at the corresponding position is not easily etched, thus leaving the protrusion 112 at the corresponding position.
[0036] Based on this, the inventors proposed a method for manufacturing trench-type MOS devices to mitigate the bump problem and improve the morphology of the formed trench gate. For details, please refer to... Figure 4 This is a schematic flowchart illustrating the manufacturing method of a trench-type MOS device according to an embodiment of this application. Figure 4 As shown, the manufacturing method of the trench-type MOS device includes:
[0037] Step S10: Provide a semiconductor substrate in which trenches are formed; the surface of the trenches is covered by a dielectric layer that extends to cover the surface of the semiconductor substrate; and the trenches are filled with a polysilicon material layer that extends to cover the surface of the dielectric layer outside the trenches, and the polysilicon material layer has voids formed in it.
[0038] Step S11: Perform a chemical mechanical polishing process on the polycrystalline silicon material layer to remove the polycrystalline silicon material layer on the surface of the dielectric layer outside the trench;
[0039] Step S12: Perform an oxidation process on the polycrystalline silicon material layer to form a silicon oxide layer on the surface of the polycrystalline silicon material layer;
[0040] Step S13: Remove the silicon oxide layer to open the void;
[0041] Step S14: Clean the polycrystalline silicon material layer; and,
[0042] Step S15: Etch the polysilicon material layer to form a trench gate.
[0043] For details, please refer to Figures 5 to 10 This is a schematic diagram of the manufacturing process of a trench-type MOS device according to an embodiment of this application.
[0044] like Figure 5 As shown, a semiconductor substrate 200 is provided. The semiconductor substrate 200 may be made of materials such as bulk silicon, silicon-on-insulator, silicon germanium, gallium nitride, or gallium arsenide. Next, trenches 202 are formed in the semiconductor substrate 200, extending from the surface of the semiconductor substrate 200 into the semiconductor substrate 200. The aspect ratio of the trenches 202 may be, for example, 2.5 to 7.
[0045] Next, a dielectric layer 204 is deposited on the surface of the trench 202, and the dielectric layer 204 extends to cover the surface of the semiconductor substrate 200. The dielectric layer 204 can be made of materials such as silicon oxide, silicon nitride, or silicon oxynitride. Specifically, the dielectric layer 204 can be formed using semiconductor processes such as chemical vapor deposition or physical vapor deposition.
[0046] Please continue to refer to this. Figure 5 Next, a polycrystalline silicon material layer 206 is filled into the trench 202, the polycrystalline silicon material layer 206 filling the trench 202 and extending to cover the surface of the dielectric layer 204 outside the trench 202. For example... Figure 5 As shown, voids 208 are formed in the polycrystalline silicon material layer 206. The bottom of the void 208 is below the surface of the semiconductor substrate 200, and the top of the void 208 is above the surface of the semiconductor substrate 200. Further, the top of the void 208 is below the surface of the dielectric layer 204 on the surface of the semiconductor substrate 200, or flush with the surface of the dielectric layer 204, or slightly above the surface of the dielectric layer 204. Figure 5 As shown, the void 208 is spindle-shaped, extending along the thickness direction of the polycrystalline silicon material layer 206, with a relatively narrow top and bottom and a relatively wide middle.
[0047] Please refer to the following: Figure 6 A chemical mechanical polishing (CMP) process is performed on the polysilicon material layer 206 to remove the polysilicon material layer 206 from the surface of the dielectric layer 204 outside the trench 202. Here, the CMP process makes the surface of the polysilicon material layer 206 flush with the surface of the dielectric layer 204. Figure 6As shown, during the chemical mechanical polishing process, some polishing fluid seeps into the cavity 208, forming a residue 210 within the cavity 208. This residue 210 covers a portion of the polysilicon material layer 206 within the cavity 208, making this portion of the polysilicon material layer 206 less susceptible to subsequent etching, thus facilitating the formation of protrusions.
[0048] The inventors discovered that the residue 210 is difficult to remove by the cleaning process because the cavity 208 is basically still closed or has only a tiny gap, making it difficult to wash away the residue 210 by the cleaning process.
[0049] Please refer to Figure 7 In this embodiment, an oxidation process is then performed on the polycrystalline silicon material layer 206 to form a silicon oxide layer 212 on the surface of the polycrystalline silicon material layer 206. Preferably, an oxidation liquid is used to perform the oxidation process on the polycrystalline silicon material layer 206 to form the silicon oxide layer 212 on the surface of the polycrystalline silicon material layer 206. In other embodiments of this application, a furnace tube process can also be used to perform the oxidation process on the polycrystalline silicon material layer 206 to form the silicon oxide layer 212. In this embodiment, by using an oxidation liquid to react with the polycrystalline silicon material layer 206 to form the silicon oxide layer 212, the reaction thickness of the polycrystalline silicon material layer 206 can be more precisely controlled, improving process accuracy. The oxidation liquid includes hydrogen peroxide (H2O2), as shown in Formula 1 (Formula 1 represents the main reactants and products in chemical form for a clearer and more intuitive understanding of this process step), which mainly involves the reaction of hydrogen peroxide with silicon to generate silicon dioxide.
[0050] Si + 2H₂O₂ → SiO₂ + 2H₂O (1)
[0051] In this embodiment, a first wet cleaning process can then be performed on the silicon oxide layer 212. Preferably, deionized water is used to perform the first wet cleaning process to facilitate the execution of subsequent processes.
[0052] Next, as Figure 8As shown, the silicon oxide layer 212 is removed. Preferably, the silicon oxide layer 212 is removed using an etching solution. In other embodiments of this application, the silicon oxide layer 212 can also be removed by a grinding process. Removing the silicon oxide layer 212 using an etching solution allows for more precise control of the removal amount, improving process accuracy and reliability. The etching solution includes hydrogen fluoride (HF), as shown in Formulas 2 and 3 below (Formulas 2 and 3 represent the main reactants and products in chemical formula form for a clearer and more intuitive understanding of this process step). The main process involves the reaction of hydrogen fluoride with silicon dioxide to generate water-soluble H2SiF6.
[0053] SiO2+2HF2-+2H3O→SiF4+4H2O (2)
[0054] SiF4 + 2HF → H2SiF6 (3)
[0055] Furthermore, a second wet cleaning process can be performed on the polycrystalline silicon material layer 206. Preferably, deionized water is used to perform the second wet cleaning process to facilitate the execution of subsequent processes.
[0056] In this embodiment, the void 208 can be opened by performing an oxidation process on the polysilicon material layer 206 and a step of removing the silicon oxide layer 212 once. Preferably, the void 208 can also be opened by performing the oxidation process on the polysilicon material layer 206 and the step of removing the silicon oxide layer 212 multiple times, thereby increasing the degree of opening of the void 208 and effectively and thoroughly removing the residue 210, improving the quality and reliability of the subsequently formed trench gate. Specifically, in the multiple steps of performing the oxidation process on the polysilicon material layer 206 and the step of removing the silicon oxide layer 212, the void 208 is opened after at least the last step of removing the silicon oxide layer 212; after each intermediate step of removing the silicon oxide layer 212, the void 208 may or may not be opened.
[0057] Preferably, performing the oxidation process on the polycrystalline silicon material layer 206 and the removal of the silicon oxide layer 212 two to four times effectively balances process reliability and process efficiency. More preferably, considering the shape of the void 208, performing the oxidation process on the polycrystalline silicon material layer 206 and the removal of the silicon oxide layer 212 three to four times. That is, first performing the oxidation process on the polycrystalline silicon material layer 206, then removing the silicon oxide layer 212, completing one round of these two steps constitutes one cycle of performing the oxidation process on the polycrystalline silicon material layer 206 and the removal of the silicon oxide layer 212. Preferably, this is performed three to four times, which maximizes the opening of the void 208. Typically, the void 208 can be opened in the middle of its spindle shape, thus facilitating the removal of the residue 210.
[0058] Furthermore, in a preferred embodiment of this application, performing the oxidation process on the polysilicon material layer 206 and the removal of the silicon oxide layer 212 once specifically includes: performing an oxidation process on the polysilicon material layer 206; performing a first wet cleaning process; removing the silicon oxide layer 212; and performing a second wet cleaning process. Performing the oxidation process on the polysilicon material layer 206 and the removal of the silicon oxide layer 212 multiple times, i.e., performing one or more rounds of the above four steps, can further improve the removal effect of the residue 210, thereby further improving the morphology of the subsequently formed trench gate.
[0059] By performing an oxidation process on the polycrystalline silicon material layer 206 and removing the silicon oxide layer 212, more than 90% of the protrusions can be avoided during the subsequent formation of the trench gate, thereby greatly improving the morphology of the formed trench gate and thus improving the electrical performance of the formed device.
[0060] Please continue to refer to this. Figure 8 In this embodiment, during the step of removing the silicon oxide layer 212 to open the cavity 208, the bottom of the cavity 208 is lower than the surface of the semiconductor substrate 200, and the top of the cavity 208 is higher than the surface of the semiconductor substrate 200. Further, the top surface of the polysilicon material layer 206 is flush with or lower than the surface of the dielectric layer 204, and the top surface of the polysilicon material layer 206 is higher than the surface of the semiconductor substrate 200.
[0061] In this embodiment, after the above process steps, the surface of the semiconductor substrate 200 is still covered with a dielectric layer 204, which can protect the surface of the semiconductor substrate 200 in subsequent processes. The dielectric layer 204 can be relatively thinned; that is, the thickness of the dielectric layer 204 formed during step S10 is thicker than the thickness of the dielectric layer 204 after step S13. This application does not limit this aspect.
[0062] Next, please refer to Figure 9 The polycrystalline silicon material layer 206 is cleaned to remove the residue 210. Specifically, the polycrystalline silicon material layer 206 can be cleaned using a cleaning solution and / or a cleaning gas. For example, deionized water can be used alone to clean the polycrystalline silicon material layer 206 to remove the residue 210; or an inert gas can be used alone to clean the polycrystalline silicon material layer 206 to remove the residue 210; or both deionized water and an inert gas can be used simultaneously to clean the polycrystalline silicon material layer 206 to remove the residue 210. Here, because the cavity 208 is opened, the residue 210 can be removed very conveniently and effectively by cleaning the polycrystalline silicon material layer 206.
[0063] Next, please refer to Figure 10 The polysilicon material layer 206 is etched to form a trench gate 214. For example... Figure 10 As shown, by removing the obstruction of residue 210, the amount of polysilicon material layer 206 removed can be well controlled, thereby forming the trench gate 214 with a good morphology. This avoids / reduces the problem of electrical test abnormalities that are prone to occur in trench MOS devices, and improves product yield.
[0064] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method of manufacturing a trench MOS device, characterized by, The method for manufacturing the trench-type MOS device includes: A semiconductor substrate is provided, wherein trenches are formed therein; a dielectric layer is covered on the surface of the trenches, the dielectric layer extending to cover the surface of the semiconductor substrate; and a polysilicon material layer is filled in the trenches, the polysilicon material layer extending to cover the surface of the dielectric layer outside the trenches, and voids are formed in the polysilicon material layer, the tops of the voids being flush with or higher than the surface of the dielectric layer. A chemical mechanical polishing process is performed on the polycrystalline silicon material layer to remove the polycrystalline silicon material layer on the surface of the dielectric layer outside the trench and to make the surface of the polycrystalline silicon material layer flush with the surface of the dielectric layer. An oxidation process is performed on the polycrystalline silicon material layer to form a silicon oxide layer on the surface of the polycrystalline silicon material layer; Remove the silicon oxide layer to open the void; Clean the polycrystalline silicon material layer; and, The polysilicon material layer is etched to form a trench gate.
2. The trench-MOS device manufacturing method according to claim 1, wherein The step of performing the oxidation process on the polycrystalline silicon material layer to form a silicon oxide layer on the surface of the polycrystalline silicon material layer and the step of removing the silicon oxide layer are performed multiple times, wherein the void is opened after at least the last execution of the step of removing the silicon oxide layer.
3. The method for manufacturing a trench-type MOS device as described in claim 1, characterized in that, An oxidation process is performed on the polycrystalline silicon material layer using an oxidizing solution to form a silicon oxide layer on the surface of the polycrystalline silicon material layer.
4. The method for manufacturing a trench-type MOS device as described in claim 3, characterized in that, The oxidizing liquid includes hydrogen peroxide.
5. The method for manufacturing a trench-type MOS device as described in claim 1, characterized in that, The silicon oxide layer is removed using an etching solution to open the voids.
6. The method for manufacturing a trench-type MOS device as described in claim 5, characterized in that, The etching solution includes hydrogen fluoride.
7. The method for manufacturing a trench-type MOS device as described in any one of claims 1 to 6, characterized in that, After performing an oxidation process on the polycrystalline silicon material layer to form a silicon oxide layer on the surface of the polycrystalline silicon material layer, the method for manufacturing the trench-type MOS device further includes performing a first wet cleaning process on the silicon oxide layer. After the step of removing the silicon oxide layer to open the voids, the method for manufacturing the trench MOS device further includes performing a second wet cleaning process on the polysilicon material layer.
8. The method for manufacturing a trench-type MOS device as described in any one of claims 1 to 6, characterized in that, The step of cleaning the polycrystalline silicon material layer is performed using a cleaning solution and / or a cleaning gas.
9. The method for manufacturing a trench-type MOS device as described in any one of claims 1 to 6, characterized in that, In the step of removing the silicon oxide layer to open the void, the bottom of the void is below the surface of the semiconductor substrate and the top of the void is above the surface of the semiconductor substrate.
10. A method for manufacturing a trench-type MOS device as described in any one of claims 1 to 6, characterized in that, In the step of removing the silicon oxide layer to open the void, the top surface of the polycrystalline silicon material layer is flush with or lower than the surface of the dielectric layer, and the top surface of the polycrystalline silicon material layer is higher than the surface of the semiconductor substrate.