Stress modulation using sti cap layer to reduce fin bowing

Abstract

The present disclosure generally relates to stress modulation using an STI cap layer to reduce fin bowing. A method includes etching a semiconductor substrate to form a semiconductor strip and a recess, where sidewalls of the semiconductor strip are exposed to the recess; depositing a dielectric layer into the recess; and depositing a cap layer over the dielectric layer. The cap layer extends into the recess and includes silicon oxynitride. The method further includes filling a remaining portion of the recess with a dielectric material; performing an anneal process to remove nitrogen from the cap layer; and recessing the dielectric material, the cap layer, and the dielectric layer. The remaining portions of the dielectric material, the cap layer, and the dielectric layer form an isolation region. A portion of the semiconductor strip protrudes above a top surface of the isolation region to form a semiconductor fin.

Description

Technical Field

[0001] This disclosure generally relates to the use of STI capping layers for stress modulation to reduce fin bending. Background Technology

[0002] As integrated circuits continue to shrink and the demands for integrated circuit speed increase, transistors require higher drive currents and increasingly smaller dimensions. Therefore, the FinFET (Fin Field-Effect Transistor) was developed. A FinFET comprises vertical semiconductor fins located above a bulk substrate. The semiconductor fins are used to form source and drain regions, as well as a channel region between the source and drain regions. Shallow trench isolation (STI) regions are formed to define the semiconductor fins. The FinFET also includes a gate stack formed on the sidewalls and top surface of the semiconductor fins.

[0003] In the formation of the STI region and the corresponding FinFET, the STI region is first formed, then recessed to form a semiconductor fin, upon which the FinFET is formed. The formation of the STI region may include forming an isolation liner, and then forming an oxide region on the isolation liner using flowable chemical vapor deposition. Summary of the Invention

[0004] According to a first embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: etching a semiconductor substrate to form a semiconductor strip and a recess, wherein sidewalls of the semiconductor strip are exposed in the recess; depositing a dielectric layer into the recess; depositing a capping layer over the dielectric layer, wherein the capping layer extends into the recess and the capping layer comprises silicon oxynitride; filling the remaining portion of the recess with a dielectric material; performing an annealing process to remove nitrogen from the capping layer; and recessing the dielectric material, the capping layer, and the dielectric layer, wherein the dielectric material, the capping layer, and the remaining portion of the dielectric layer form an isolation region, and wherein a portion of the semiconductor strip protrudes above the top surface of the isolation region to form a semiconductor fin.

[0005] According to a second embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a semiconductor strip; depositing a first dielectric layer through a plurality of atomic layer deposition (ALD) cycles, wherein each of the ALD cycles comprises: pulsedly delivering hexachlorosilane (HCD) to the semiconductor strip and purging it; pulsedly delivering oxygen to the semiconductor strip and purging it; and pulsedly delivering ammonia to the semiconductor strip and purging it; annealing the first dielectric layer; recessing the first dielectric layer, wherein a remaining portion of the first dielectric layer forms part of an isolation structure, and a portion of the semiconductor strip protrudes above the top surface of the isolation structure to form a semiconductor fin; and forming a gate stack extending on the sidewalls and top surface of the semiconductor fin.

[0006] According to a third embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: depositing a first silicon oxide layer; depositing a silicon oxynitride layer on the first silicon oxide layer; depositing a second silicon oxide layer on the silicon oxynitride layer; and after depositing the second silicon oxide layer, performing a first wet annealing process and a dry annealing process to convert the silicon oxynitride layer into a third silicon oxide layer. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figures 1-2 , Figure 3A , Figure 3B , Figures 4-6 , Figure 7A , Figure 7B , Figure 8 , Figure 9A , Figure 9B , Figure 10A , Figure 10B and Figure 10C Cross-sectional and perspective views of intermediate stages in the formation of a FinFET according to some embodiments are shown.

[0009] Figure 11 An atomic layer deposition (ALD) cycle for forming a SiON film according to some embodiments is shown.

[0010] Figure 12A and Figure 12B A schematic structure of a shallow trench isolation (STI) cap layer deposited according to some embodiments is shown.

[0011] Figure 13A , Figure 13B and Figure 13C A schematic structure of the STI cap layer after performing low-temperature wet annealing and high-temperature wet annealing processes is shown according to some embodiments.

[0012] Figure 14A and Figure 14B A schematic structure of an STI cap layer after a dry annealing process is shown according to some embodiments.

[0013] Figure 15 Two regions with separately formed STI cap layers are shown according to some embodiments.

[0014] Figure 16 A schematic distribution curve of the percentage of nitrogen atoms according to some embodiments is shown.

[0015] Figure 17 A process flow for forming a fin field-effect transistor (FinFET) and dielectric fins according to some embodiments is shown. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) may be used herein to readily describe the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device during use or operation, other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein will be interpreted accordingly.

[0018] FinFETs, isolation regions, and methods for forming them are provided. According to some embodiments of this disclosure, a nitrogen-containing dielectric layer is deposited. The nitrogen-containing dielectric layer may later have its nitrogen removed by annealing. The nitrogen-containing dielectric layer has the ability to apply stress to reduce semiconductor strip / fin bending. After the subsequent removal of nitrogen, the dielectric layer is converted into a silicon oxide layer, which has low leakage due to the low charge trapping ability of silicon oxide. The embodiments discussed herein provide examples to enable the making or use of the subject matter of this disclosure, and modifications that can be made while remaining within the contemplated scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0019] Figures 1-2 , Figure 3A , Figure 3B , Figures 4-6 , Figure 7A , Figure 7B , Figure 8 , Figure 9A , Figure 9B , Figure 10A , Figure 10B and Figure 10C A cross-sectional view is shown illustrating intermediate stages in the formation of a FinFET and adjacent dielectric fins according to some embodiments of this disclosure. Corresponding processes are also schematically reflected in, for example... Figure 17 The process flow shown is 200.

[0020] refer to Figure 1 A substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The semiconductor substrate 20 may be part of a wafer 10, such as a silicon wafer. Typically, the SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include: silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0021] refer to Figure 2 The substrate 20 is etched to form trenches 24. Figure 17In the process flow 200 shown, the corresponding process is shown as process 202. The portion of the substrate 20 between adjacent trenches 24 is hereinafter referred to as semiconductor strip 26. To form the trenches 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of this disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized.

[0022] According to some embodiments of this disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. A photoresist (not shown) is formed on the hard mask layer 30, and then the photoresist is patterned. The patterned photoresist is then used as an etch mask to pattern the hard mask layer 30 to form, for example,... Figure 2 The hard mask 30 is shown. Next, the patterned hard mask layer 30 is used as an etching mask to etch the pad oxide layer 28 and the substrate 20, thereby forming the trench 24.

[0023] refer to Figure 3A A dielectric layer 32 was deposited. Figure 17 In the illustrated process flow 200, the corresponding process is shown as process 204. According to some embodiments of this disclosure, a conformal deposition process such as ALD, chemical vapor deposition (CVD), etc., is used to form the dielectric layer 32. Therefore, the horizontal thickness T1 of the horizontal portion and the vertical thickness T2 of the vertical portion of the dielectric layer 32 are equal to or substantially equal to each other, for example, having a variation of less than about 10%. The material of the dielectric layer 32 can be selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, hafnium oxide, zirconium oxide, aluminum oxide, etc., and combinations thereof. The dielectric layer 32 can also be a composite layer comprising multiple sublayers formed of different materials. Thicknesses T1 and T2 can be greater than about 5 nm and can be in the range of about 2 nm to about 20 nm. According to some example embodiments, the dielectric layer 32 can be formed of silicon oxide, having a nitrogen atom percentage of less than about 5%, less than about 2%, or in the range of about 0.1% to about 2%. The deposited dielectric layer 32 may also be nitrogen-free.

[0024] Figure 3B It shows Figure 3A Section 3B-3B in the middle. It should be realized that... Figure 3A It is illustrative and does not include, for example Figure 3B All the details shown. Throughout the specification, the semiconductor strips 26 that are close to each other are collectively referred to as semiconductor strip group 27, and Figure 3BExample semiconductor stripe groups 27A, 27B1, 27B2, and 27B3 are shown. For example, Figure 3B Several semiconductor strips 26 are shown close to each other to form a group of semiconductor strips 27A. Semiconductor strips in the same group can be used to form the same FinFET. Although... Figure 3B Semiconductor strip group 27A is shown to include two semiconductor strips 26, but there can be more semiconductor strips in a semiconductor strip group. The inter-group spacing S1 between semiconductor strips 26 in the same strip group 27 is smaller than the inter-group spacing S2 between adjacent semiconductor strip groups 27. There can also be some single-fin semiconductor strip groups, where each group includes a single fin. Some example single-fin semiconductor strip groups 27 are shown (e.g., semiconductor strip groups 27B1, 27B2, and 27B3).

[0025] Due to the conformal deposition of the dielectric layer 32, the trenches 24 between the semiconductor strips 26 in the same semiconductor strip group 27 are completely filled. On the other hand, the trenches 24 between the semiconductor strip groups 27 are partially filled. After the STI cap layer 34 is deposited, the dielectric layer 32 may be exposed to moisture in the air. Due to the formation of native oxides and exposure to moisture, Si-OH bonds are formed at the surface of the dielectric layer 32.

[0026] Figure 4 The formation of dielectric layer 34 is shown, which is alternatively referred to as shallow trench isolation (STI) capping layer 34. Figure 17 In the process flow 200 shown, the corresponding process is shown as process 206. At the start of the deposition process, wafer 10 is placed in an atomic layer deposition (ALD) chamber (not shown), in which one or more ALD cycles are performed to conformally grow the STI cap layer 34.

[0027] Figure 11 The intermediate stage of ALD cycle 35 and the repetition of the ALD cycle are schematically illustrated. At the start of the ALD cycle, hexachlorodisilane (HCD) is introduced / pulsed into the ALD chamber (not shown), in which wafer 10 is placed. Figure 3A and Figure 3B ).exist Figure 17 In the process flow 200 shown, the corresponding process is indicated as process 208. HCD has the chemical formula (SiCl3)2, and the chemical structure of the HCD molecule is as follows: Figure 11As shown. The HCD molecule comprises six chlorine atoms bonded to two silicon atoms. When the HCD is pulsed into the ALD chamber, wafer 10 is heated to a temperature, for example, in the range of about 450°C to about 700°C. OH bonds at the surface of dielectric layer 32 break, and silicon atoms, along with chlorine atoms bonded to silicon atoms, are bonded to suspended oxygen atoms to form O-Si-Cl bonds. According to some embodiments, the flow rate of the HCD can be in the range of about 0.1 slm to about 2 slm, for example, in the range of about 0.3 slm to about 0.6 slm. The pressure in the ALD chamber can be in the range of about 60 Pa to about 1000 Pa, and can be in the range of about 100 Pa to about 120 Pa. The duration of the pulse delivery can be in the range of about 5 seconds to about 50 seconds, and can be in the range of about 15 seconds to about 25 seconds.

[0028] Next, purge the HCD from the ALD chamber. (Reference) Figure 11 Oxygen (O2) is delivered to the ALD chamber in a pulsed manner. Figure 17 In the process flow 200 shown, the corresponding process is shown as process 210. The previously formed structure reacts with oxygen, some Si-Cl bonds break, and oxygen atoms connect to form Si-O bonds. According to some embodiments, the oxygen flow rate can be in the range of about 0.5 slm to about 10 slm, and can be in the range of about 2.0 slm to about 8.0 slm. The pressure can be in the range of about 60 Pa to about 2000 Pa, and can be in the range of about 1000 Pa to about 1400 Pa. The duration of the pulse delivery can be in the range of about 30 seconds to about 100 seconds, and can be in the range of about 50 seconds to about 70 seconds. Then, oxygen is purged.

[0029] Next, as Figure 11 As shown, ammonia gas is delivered to the ALD chamber in a pulsed manner. Figure 17 In the process flow 200 shown, the corresponding process is shown as process 212. The previously formed structure reacts with ammonia. Some Si-Cl bonds break and connect with NH2 to form Si-NH2 bonds. According to some embodiments, the ammonia flow rate can be in the range of about 0.5 slm to about 10 slm, and can be in the range of about 2.0 slm to about 8.0 slm. The pressure can be in the range of about 100 Pa to about 1200 Pa, and can be in the range of about 800 Pa to about 1000 Pa. The duration of the pulse delivery can be in the range of about 30 seconds to about 100 seconds, and can be in the range of about 15 seconds to about 20 seconds. Then the ammonia is purged. Thus, an atomic layer of STI capping layer 34 is deposited.

[0030] After purging ammonia, the ALD cycle 35 can be repeated to deposit multiple atomic layers to form the STI cap layer 34, such as... Figure 4 As shown. Each ALD cycle of 35 results in the deposition of a SiON layer. For example, the thickness of the deposited SiON atomic layer can be approximately... To date Within the range between, and can be in approximately To date Within the range of approximately 1 nm to approximately 5 nm. When the deposition process is complete, the deposited STI capping layer 34 can have a thickness in the range of approximately 1 nm to approximately 5 nm.

[0031] refer to Figure 5 This forms a dielectric capping layer 36. Figure 17 In the process flow 200 shown, the corresponding process is shown as process 214. According to some embodiments of this disclosure, a conformal deposition method such as atomic layer deposition (ALD) or CVD is used to form the dielectric cap layer 36. Therefore, the horizontal thickness T3 of the horizontal portion and the vertical thickness T4 of the vertical portion of the dielectric cap layer 36 are equal to or substantially equal to each other, for example, having a variation of less than about 10%. The material of the dielectric cap layer 36 can be selected from the following: silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. The nitrogen atom percentage of the dielectric cap layer 36 can be significantly lower than the nitrogen atom percentage of the STI cap layer 34. For example, the nitrogen atom percentage of the dielectric cap layer 36 can be less than about 2% or 1%. The dielectric cap layer 36 has a dielectric mixing fin 46 that is subsequently formed ( Figure 7A The function of width.

[0032] Then, a dielectric fin layer 38 is formed on top of the dielectric cap layer 36. Figure 17 In the process flow 200 shown, the corresponding process is shown as process 216. A method with good gap-filling capability is used to form the dielectric fin layer 38. According to some embodiments of this disclosure, the dielectric fin layer 38 is formed by high-density plasma chemical vapor deposition (HDPCVD), PECVD, ALD, etc. The material of the dielectric fin layer 38 is different from the materials of the dielectric layers 34 and 36. According to some embodiments, the dielectric fin layer 38 is formed of or includes high-k dielectric materials such as: hafnium oxide, zirconium oxide, aluminum oxide, aluminum nitride, titanium nitride, etc., combinations thereof, or multiples thereof. Alternatively, the dielectric fin layer 38 may be formed of: silicon oxide, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, BSG, PSG, BPSG, etc. The dielectric fin layer 38 completely fills the trench 24 ( Figure 4 ).

[0033] Figure 5 The formation of a dielectric region 42 is also shown, which can be formed to fill very wide trenches that are difficult to fill by the dielectric fin layer 38. According to some embodiments, the formation process includes depositing the dielectric fin layer 38A by a conformal deposition process such as ALD, CVD, etc., wherein the trench 24B ( Figure 4 The remaining trench 24C is completely filled, while the remaining trench 24C is partially filled. Next, the remaining trench 24C is filled with a dielectric material such as a flowable oxide, which completely fills the remaining trench 24C. A planarization process and an etch-back process are then performed to recess the dielectric material and leave dielectric regions 42. In a subsequent process, a dielectric fin layer 38B is deposited to completely fill the trench 24C. Figure 4 ).

[0034] Next, as Figure 6 As shown, planarization processes such as CMP or mechanical polishing are performed to make the top surface of the dielectric fin layer 38 flat. Figure 17 In the illustrated process flow 200, the corresponding process is shown as process 218. A planarization process then continues to remove excess portions of the dielectric fins 38 and dielectric layers 36, 34, and 32 above the top surface of the semiconductor strip 26. The hard mask 30 and the pad layer 28 are also removed. As a result, the top edges of the sidewall (vertical) portions of the dielectric layers 32, 34, 36, and 38 are exposed. According to an alternative embodiment, the planarization process is completed when the top surface of the hard mask 30 is exposed.

[0035] After planarization, annealing process 220 is performed. Figure 17 In the illustrated process flow 200, the corresponding process is shown as process 220. According to some embodiments of this disclosure, annealing process 220 includes a low-temperature wet annealing process 222, a high-temperature wet annealing process 224, and a dry annealing process 226. Low-temperature wet annealing process 222 and high-temperature wet annealing process 224 can be performed using steam (H2O) as the process gas. Dry annealing process 226 can be performed using nitrogen (N2), argon, or the like as the carrier gas. References below... Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 13C , Figure 14A and Figure 14B Let's discuss the annealing process.

[0036] Figure 12A The chemical structure of the STI cap layer 34 deposited prior to annealing process 220 is schematically shown, with two atomic layers shown. Figure 12BAnother representation is schematically shown, illustrating some example bonding in the two vertical sidewall portions of the STI cap layer 34. According to some embodiments of this disclosure, a low-temperature wet annealing process is first performed. Figure 17 In the process flow 200 shown, the corresponding process is indicated as process 222. The low-temperature wet annealing process 222 is performed at a relatively low temperature, which can be in the range of approximately 440°C to approximately 460°C. The low-temperature wet annealing process can last for a period of time ranging from approximately 3 hours to approximately 5 hours. The pressure during low-temperature annealing can be approximately 1 atmosphere.

[0037] The low-temperature wet annealing process has two functions. The first function is to allow water / water vapor (H2O) molecules to diffuse through the exposed top edge of the STI cap layer 34 throughout the entire STI cap layer 34, where... Figure 13B The solid dots represent H2O molecules. The second function is to partially convert the Si-N, Si-CH3, and Si-N-Si bonds in the STI cap layer 34 into Si-OH bonds, such as... Figure 13B As shown. The temperature is controlled high enough to induce at least a partial conversion.

[0038] After the low-temperature wet annealing process 222, a high-temperature wet annealing process is performed. Figure 17 In the process flow 200 shown, the corresponding process is designated as process 224. The high-temperature wet annealing process 224 is performed at a higher temperature than the low-temperature wet annealing process. The annealing temperature can be in the range of approximately 525°C to approximately 575°C. The high-temperature wet annealing process 224 can last for a period of time ranging from approximately 1.5 hours to approximately 2.5 hours. The pressure of the high-temperature wet annealing process 224 can be approximately 1 atmosphere. The temperature is high enough to effectively convert the Si-N bonds in the STI cap layer 34 to Si-OH bonds, such as... Figure 13A and Figure 13B The diagram illustrates this schematically. The high-temperature wet annealing process 224 leads to the formation of Si-N bonds (…). Figure 12B The Si-O bond is broken. Furthermore, the OH groups in H2O attach to the broken bonds. Figure 13A and Figure 13C The structure of the STI cap layer 34 after a low-temperature wet annealing process is schematically shown.

[0039] After the high-temperature wet annealing process 224, a dry annealing process is performed. Figure 17In the illustrated process flow 200, the corresponding process is shown as process 226. In dry annealing process 226, an oxygen-free process gas such as nitrogen (N2) or argon can be used as the process gas. According to some embodiments of this disclosure, dry annealing process 226 is performed at a temperature in the range of about 650°C to about 750°C. The dry annealing process can last for a period of time in the range of about 0.5 hours to about 1.5 hours. The pressure can be about 1 atmosphere.

[0040] In the dry annealing process 226, the OH bonds and Si-O bonds in the STI cap layer 34 break, and the broken H and OH bonds combine to form H2O molecules, such as Figure 14B As shown in the diagram, oxygen atoms (whose bonds become suspended due to the loss of H atoms) can bond with Si to form silicon oxide (SiO2). The corresponding chemical structure is also shown in... Figure 14A and Figure 14B The diagram illustrates this schematically. Therefore, wet and dry annealing processes convert the deposited silicon oxynitride layer into a silicon oxide layer. The generated H₂O molecules are carried away by the carrier gas.

[0041] As previously mentioned, the deposited STI capping layer 34 comprises SiON or SiONH, such as Figure 12A As shown. The inclusion of nitrogen in the STI cap layer 34 can... Figure 5 and Figure 6 The structure shown applies stress that prevents the semiconductor strip 26 from bending. Otherwise, without the formation of the nitrogen-containing STI capping layer 34, the semiconductor strips in the semiconductor strip group 27 would bend. The semiconductor strips 26 in the same fin group 27 (especially the outer strips) would bend outwards, a bending caused by any annealing process performed. By forming the nitrogen-containing STI capping layer 34, bending of the semiconductor strip 26 is avoided.

[0042] An advantageous feature of the STI cap layer 34 is that its nitrogen can be removed through an annealing process. Therefore, during the annealing process, the STI cap layer 34 already achieves its anti-bending function. Simultaneously, as the annealing process proceeds, its nitrogen is removed to form a silicon oxide layer. Although the silicon oxide layer no longer has the anti-bending function, the stress on the semiconductor strip 26 has been released after the annealing process, and the semiconductor strip 26 will not bend. Converting the SiON-containing STI cap layer 34 to a silicon oxide-containing STI cap layer 34 is beneficial for reducing leakage current through the STI region, because silicon oxide has low leakage, while nitrogen-containing materials such as SiN and SiON have higher leakage. For example, after annealing process 220, the effective charge density Qeff of the STI cap layer 34 can be reduced to below approximately 5E11 C / cm². 2 Therefore, the leakage is low.

[0043] According to some embodiments, prior to annealing process 220 (and during deposition), the STI cap layer 34 may have a silicon atomic percentage in the range of about 20% to about 40% (e.g., about 18% to 22%). The oxygen atomic percentage may be in the range of about 30% to about 50%. The carbon atomic percentage may be less than about 10% (e.g., 0% (carbon-free)). The nitrogen atomic percentage may be in the range of about 5% to about 30% (e.g., about 10% to 20%).

[0044] Annealing process 220 results in an increase in the percentage of oxygen atoms and a decrease in the percentage of nitrogen atoms. For example, after annealing process 220, the STI cap layer 34 may have a silicon atom percentage in the range of about 20% to about 40% (e.g., about 18% to 22%). The oxygen atom percentage may be in the range of about 50% to about 80%, and may be in the range of about 65% to about 75%. The carbon atom percentage may be below about 10% (e.g., 0%). The nitrogen atom percentage may be reduced to below about 10% (e.g., below about 2%). For example, 70%, 90%, or more of the nitrogen may be removed.

[0045] Figure 7A and Figure 7B This illustrates recessing dielectric layers 32, 34, and 36 to form a recess 45. Figure 17 In the illustrated process flow 200, the corresponding process is shown as process 228. The recess can be performed using an isotropic etching process (e.g., wet etching or dry etching) or an anisotropic etching process (e.g., dry etching). The etching chemicals (etching solution or etching gas) are selected such that dielectric layers 32, 34, and 36 are etched, while dielectric fin layer 38 is not etched.

[0046] Due to the recesses in dielectric layers 32, 34, and 36, portions of dielectric fin layer 38 protrude above the top surfaces of the remaining dielectric layers 32, 34, and 36 to form dielectric fins 46. Furthermore, some top portions of semiconductor strip 26 protrude above the top surface of the remaining dielectric layer 32 to form protruding semiconductor fins 26'. Throughout this specification, the portions of dielectric layers 32, 34, and 36, and dielectric fin layer 38 below the corresponding protruding semiconductor fins 26' and 46 are referred to as shallow trench isolation (STI) regions 48.

[0047] Figure 7B A perspective view is schematically shown, in which Figure 7A It shows Figure 7B The cross-sections of some parts of the structure are shown, and these cross-sections are obtained in a vertical plane.

[0048] refer to Figure 8 The dummy gate stack 58 is formed to extend on the top surface and sidewalls of the protruding semiconductor fin 26' and the protruding dielectric fin 46. Figure 17 In the illustrated process flow 200, the corresponding process is shown as process 230. A dummy gate stack 58 may include a dummy gate dielectric 52 and a dummy gate electrode 54 located on the dummy gate dielectric 52. The dummy gate dielectric 52 may be formed of or comprise silicon oxide, and the dummy gate electrode 54 may be formed of or comprise amorphous silicon or polycrystalline silicon, or other suitable materials may be used. Each dummy gate stack 58 may also include one (or more) hard mask layers 56 located on the dummy gate electrode 54. The hard mask layer 56 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon carbonitride oxyacetate, or multiple layers thereof. The dummy gate stack 58 may span a plurality of protruding semiconductor fins 26' and one or more protruding dielectric fins 46. The dummy gate stack 58 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding semiconductor fins 26' and the protruding dielectric fins 46.

[0049] The formation of the dummy gate stack 58 may include: depositing a conformal gate dielectric layer, depositing a dummy gate electrode layer to completely fill the recess 45 ( Figure 7B The process involves planarizing the top surface of the dummy gate electrode layer, depositing a hard mask layer on the planarized dummy gate electrode layer, and patterning the deposited layer.

[0050] Gate spacer 60 is formed on the sidewalls of the dummy gate stack 58. According to some embodiments of this disclosure, gate spacer 60 is formed of one or more dielectric materials such as silicon nitride, silicon oxynitride, silicon carbonitride, etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers. According to some embodiments of this disclosure, the formation of gate spacer 60 includes depositing a conformal spacer layer (which may be a single layer or a composite layer, not shown) on wafer 10, and then performing an anisotropic etching process to remove horizontal portions of the spacer layer. The spacer layer is formed on the top surface and sidewalls of the dummy gate stack 58, the protruding semiconductor fin 26', and the protruding dielectric fin 46. Gate spacer 60 also has portions extending into the recess 45.

[0051] Next, as Figure 9A and Figure 9B As shown, an epitaxial region (source / drain region) 62 is formed. Figure 17In the illustrated process flow 200, the corresponding process is shown as process 232. According to some embodiments, the formation process includes etching the portion of the protruding semiconductor fin 26' that is not protected by the dummy gate stack 58 and gate spacer 60 to form a recess, followed by selective growth (by epitaxy) of semiconductor material in the recess 45. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be doped in situ as epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc., can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbon phosphide (SiCP), etc., can be grown. In the epitaxial process, the protruding dielectric fin 46 is used to limit the lateral growth of the epitaxial source / drain region 62 and to prevent adjacent source / drain regions 62 from merging together.

[0052] Figure 10A and Figure 10C Perspective and cross-sectional views of the structure after the formation of the contact etch stop layer (CESL) 64 and the interlayer dielectric (ILD) 66 are shown, respectively. Figure 17 In the process flow 200 shown, the corresponding process is shown as process 234. CESL 64 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 66 can include a dielectric material formed using deposition methods such as FCVD, spin coating, CVD, etc. ILD 66 can be formed from an oxygen-containing dielectric material, which can be silicon oxide, PSG, BSG, BPSG, etc. Planarization processes such as CMP or mechanical polishing can be performed to make the top surfaces of ILD 66, dummy gate stack 58, and gate spacer 60 flush with each other.

[0053] Next, as Figure 10A , Figure 10B and Figure 10C As shown, replace the gate stack 76 with a replacement gate stack. Figure 9B The dummy gate stack 58 is shown. Figure 17 In the process flow 200 shown, the corresponding process is shown as process 236. Figure 10B and Figure 10C They are shown respectively Figure 10A The cross sections are 10B-10B and 10C-10C. In the replacement process, a dummy gate stack of 58 ( Figure 9B The electrodes are etched to form trenches between the gate spacers 46. The top surfaces and sidewalls of the protruding semiconductor fins 26' and dielectric fins 46 are exposed to the trenches. Next, a replacement gate stack 76 is formed in the trenches. The replacement gate stack 76 includes a gate dielectric 72 and a gate electrode 74.

[0054] According to some embodiments of this disclosure, the gate dielectric 72 includes an interface layer (IL) as its lower portion. The IL is formed on the exposed surfaces of the protruding semiconductor fin 26' and the protruding dielectric fin 46. The IL may include an oxide layer, such as a silicon oxide layer, which is formed by a chemical oxidation process, a deposition process, or thermal oxidation of the protruding semiconductor fin 26'. The gate dielectric 72 may also include a high-k dielectric layer formed on the IL. The high-k dielectric layer includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and may be greater than about 7.0. The high-k dielectric layer is located on the IL and may contact the IL. The high-k dielectric layer is formed as a conformal layer. According to some embodiments of this disclosure, the high-k dielectric layer is formed using ALD, CVD, PECVD, molecular beam deposition (MBD), etc.

[0055] A gate electrode 74 is formed on a corresponding gate dielectric 72. The gate electrode 74 may include a plurality of metal-containing layers, which may be formed as conformal layers and may (or may not) include fill metal regions that fill any remaining trenches not filled by the plurality of metal-containing layers. The metal-containing layers may include a barrier layer, a work function layer above the barrier layer, and one or more metal capping layers above the work function layer.

[0056] Figure 10B The cross-section of the gate stack 76 is shown. The gate stacks 76 of adjacent FinFETs are spaced apart by an isolation region 78, which cuts the originally long gate stack into shorter gate stacks 76. Figure 10C The cross-section showing the source / drain region 62 is illustrated. The top surface horizontal 48T and bottom surface horizontal 48B of the STI region 48 (they are not...) Figure 10C The location of STI region 48 is shown in the plane shown in the diagram.

[0057] According to some embodiments, the STI capping layer 34 covering the entire wafer 10 is formed in the same process. According to alternative embodiments, the STI capping layer 34 in different device regions can be deposited in different processes. For example... Figure 15FinFET regions 100A and 100B are shown, wherein the STI capping layer 34A in FinFET region 100A and the STI capping layer 34B in FinFET region 100B are formed in separate deposition processes. Dielectric layers 32, 34, and 38 in FinFET regions 100A and 100B can share a common process for formation. These embodiments can be used when the curvature of the fins in FinFET regions 100A and 100B differs from each other, thus the STI capping layers 34A and 34B are configured to apply different stresses. For example, when the inter-group spacing S1A differs from the inter-group spacing S1B, and / or the materials of semiconductor strips 26A and 26B differ from each other, the curvature of semiconductor strip 26A can differ from the curvature of semiconductor strip 26B, and their curvature is fixed by the STI capping layers 34A and 34B.

[0058] According to some embodiments, the first thickness T3A of the STI cap layer 34A can be less than the thickness T3B of the STI cap layer 34B. Therefore, the stress applied by the STI cap layer 34A is less than the stress applied by the STI cap layer 34B. Alternatively, the STI cap layer 34B has a higher percentage of nitrogen atoms than the STI cap layer 34A. This can be achieved, for example, by increasing the nitrogen atom percentage... Figure 11 The flow rate and partial pressure of ammonia in the ALD cycle 35 shown are used to achieve this. Therefore, in such a way... Figure 15 In the structure shown, the percentage of nitrogen atoms in the STI cap layer 34B is also higher than the percentage of nitrogen atoms in the STI cap layer 34A.

[0059] Figure 16 The nitrogen distribution according to some embodiments is illustrated schematically. The X-axis represents the distribution along... Figure 10B The depth of arrow 80 is shown. The Y-axis represents the percentage of nitrogen atoms. According to some embodiments, nitrogen has a peak nitrogen atom percentage in the STI cap layer 34, and the nitrogen atom percentage decreases from the STI cap layer 34 to the dielectric cap layer 36 and the dielectric fin layer 38. The nitrogen atom percentage may also decrease from the STI cap layer 34 to the dielectric layer 32 and the substrate 20.

[0060] The embodiments of this disclosure have several advantageous features. By forming a nitrogen-containing dielectric layer that also has the ability to remove nitrogen through annealing, the nitrogen-containing dielectric layer has the ability to apply stress to reduce semiconductor strip / fin bending, and after nitrogen removal through annealing, the resulting silicon oxide layer has low leakage due to low charge trapping. This differs from related structures that form silicon oxide or silicon nitride (or silicon oxynitride). If silicon oxide is formed, it does not have the ability to reduce fin bending. If related methods are used to form silicon nitride or silicon oxynitride, it will remain as silicon nitride or silicon oxynitride and cannot be converted to silicon oxide. Therefore, the leakage current will be higher.

[0061] According to some embodiments of this disclosure, a method includes: etching a semiconductor substrate to form a semiconductor strip and a recess, wherein sidewalls of the semiconductor strip are exposed in the recess; depositing a dielectric layer into the recess; depositing a capping layer over the dielectric layer, wherein the capping layer extends into the recess and the capping layer comprises silicon oxynitride; filling the remaining portion of the recess with a dielectric material; performing an annealing process to remove nitrogen from the capping layer; and recessing the dielectric material, the capping layer, and the dielectric layer, wherein the remaining portions of the dielectric material, the capping layer, and the dielectric layer form an isolation region, and wherein a portion of the semiconductor strip protrudes above the top surface of the isolation region to form a semiconductor fin.

[0062] In one embodiment, depositing the capping layer includes an ALD cycle, the ALD cycle including: pulsed delivery of HCD to the semiconductor substrate and purging; pulsed delivery of oxygen to the semiconductor substrate and purging; and pulsed delivery of ammonia to the semiconductor substrate and purging. In one embodiment, the method further includes: after filling the recess with the dielectric material, performing a planarization process on the dielectric material, the capping layer, and the dielectric layer, wherein the annealing process is performed through the exposed top edge of the capping layer. In one embodiment, the annealing process is performed before the recess. In one embodiment, the annealing process includes: a low-temperature wet annealing process performed at a first temperature; a high-temperature wet annealing process performed at a second temperature higher than the first temperature; and a dry annealing process performed after the high-temperature wet annealing process.

[0063] In one embodiment, the dry annealing process is performed at a third temperature higher than the first and second temperatures. In one embodiment, the low-temperature wet annealing process is performed at the first temperature, which is in the range of about 440°C to about 460°C. In one embodiment, the high-temperature wet annealing process is performed at the second temperature, which is in the range of about 525°C to about 575°C. In one embodiment, the dry annealing process is performed at the third temperature, which is in the range of about 650°C to about 750°C.

[0064] According to some embodiments of this disclosure, a method includes: forming a semiconductor strip; depositing a first dielectric layer through a plurality of ALD cycles, wherein each of the ALD cycles includes: pulsedly delivering HCD to the semiconductor strip and purging it; pulsedly delivering oxygen to the semiconductor strip and purging it; pulsedly delivering ammonia to the semiconductor strip and purging it; annealing the first dielectric layer; recessing the first dielectric layer, wherein a remaining portion of the first dielectric layer forms part of an isolation structure, and a portion of the semiconductor strip protrudes above the top surface of the isolation structure to form a semiconductor fin; and forming a gate stack extending on the sidewalls and top surface of the semiconductor fin.

[0065] In one embodiment, in each of the ALD cycles, the oxygen is pulsed after the HCD is pulsed, and the ammonia is pulsed after the oxygen is pulsed. In one embodiment, the method further includes depositing an additional dielectric layer over the first dielectric layer, wherein, during annealing of the first dielectric layer, the top edge of the vertical portion of the first dielectric layer is exposed, and the horizontal portion of the first dielectric layer lies beneath the additional dielectric layer. In one embodiment, the additional dielectric layer comprises silicon oxide and has a lower nitrogen atom percentage than the first dielectric layer.

[0066] In one embodiment, the method further includes depositing a second dielectric layer before depositing the first dielectric layer, wherein the second dielectric layer comprises silicon oxide and has a lower nitrogen atom percentage than the first dielectric layer. In one embodiment, annealing the first dielectric layer includes a low-temperature wet annealing process, a high-temperature wet annealing process, and a dry annealing process. In one embodiment, before the annealing, the first dielectric layer has a first nitrogen atom percentage, and after the annealing, the first dielectric layer has a second nitrogen atom percentage lower than the first nitrogen atom percentage.

[0067] According to some embodiments of this disclosure, a method includes: depositing a first silicon oxide layer; depositing a silicon oxynitride layer over the first silicon oxide layer; depositing a second silicon oxide layer over the silicon oxynitride layer; and after depositing the second silicon oxide layer, performing a first wet annealing process and a dry annealing process to convert the silicon oxynitride layer into a third silicon oxide layer. In one embodiment, the method further includes: performing a second wet annealing process at a temperature different from the temperatures of the first wet annealing process and the dry annealing process, after the first wet annealing process and before the dry annealing process.

[0068] In one embodiment, the method further includes: etching back the first silicon oxide layer, the silicon oxynitride layer, and the second silicon oxide layer after the first wet annealing process and the dry annealing process. In one embodiment, after the first wet annealing process and the dry annealing process, the nitrogen atom percentage of the third silicon oxide layer is higher than the nitrogen atom percentage of the first silicon oxide layer and the second silicon oxide layer.

[0069] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will recognize that they can readily use this disclosure as the basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to this document without departing from the spirit and scope of the invention.

[0070] Example 1 is a method of manufacturing a semiconductor device, comprising: etching a semiconductor substrate to form a semiconductor strip and a recess, wherein sidewalls of the semiconductor strip are exposed in the recess; depositing a dielectric layer into the recess; depositing a capping layer over the dielectric layer, wherein the capping layer extends into the recess and the capping layer comprises silicon oxynitride; filling the remaining portion of the recess with a dielectric material; performing an annealing process to remove nitrogen from the capping layer; and recessing the dielectric material, the capping layer, and the dielectric layer, wherein the dielectric material, the capping layer, and the remaining portion of the dielectric layer form an isolation region, and wherein a portion of the semiconductor strip protrudes above the top surface of the isolation region to form a semiconductor fin.

[0071] Example 2 is the method described in Example 1, wherein depositing the capping layer includes an atomic layer deposition (ALD) cycle, the ALD cycle including: pulsed delivery of hexachlorosilane (HCD) to the semiconductor substrate and purging; pulsed delivery of oxygen to the semiconductor substrate and purging; and pulsed delivery of ammonia to the semiconductor substrate and purging.

[0072] Example 3 is the method of Example 1, further comprising: after filling the recess with the dielectric material, performing a planarization process on the dielectric material, the cap layer and the dielectric layer, wherein the annealing process is performed through the exposed top edge of the cap layer.

[0073] Example 4 is the method described in Example 3, wherein the annealing process is performed before the depression.

[0074] Example 5 is the method described in Example 1, wherein the annealing process includes: a low-temperature wet annealing process performed at a first temperature; a high-temperature wet annealing process performed at a second temperature higher than the first temperature; and a dry annealing process performed after the high-temperature wet annealing process.

[0075] Example 6 is the method described in Example 5, wherein the dry annealing process is performed at a third temperature higher than the first temperature and the second temperature.

[0076] Example 7 is the method described in Example 5, wherein the low-temperature wet annealing process is performed at the first temperature in the range of about 440°C to about 460°C.

[0077] Example 8 is the method described in Example 5, wherein the high-temperature wet annealing process is performed at the second temperature in the range of about 525°C to about 575°C.

[0078] Example 9 is the method described in Example 5, wherein the dry annealing process is performed at a third temperature in the range of about 650°C to about 750°C.

[0079] Example 10 is a method of manufacturing a semiconductor device, comprising: forming a semiconductor strip; depositing a first dielectric layer through a plurality of atomic layer deposition (ALD) cycles, wherein each of the ALD cycles comprises: pulsedly delivering hexachlorosilane (HCD) to the semiconductor strip and purging it; pulsedly delivering oxygen to the semiconductor strip and purging it; and pulsedly delivering ammonia to the semiconductor strip and purging it; annealing the first dielectric layer; recessing the first dielectric layer, wherein a remaining portion of the first dielectric layer forms part of an isolation structure, and a portion of the semiconductor strip protrudes above the top surface of the isolation structure to form a semiconductor fin; and forming a gate stack extending on the sidewalls and top surface of the semiconductor fin.

[0080] Example 11 is the method of Example 10, wherein, in each of the ALD cycles, the oxygen is pulsed after the HCD is pulsed, and the ammonia is pulsed after the oxygen is pulsed.

[0081] Example 12 is the method of 10, further comprising: depositing an additional dielectric layer over the first dielectric layer, wherein, during annealing of the first dielectric layer, the top edge of a vertical portion of the first dielectric layer is exposed, and a horizontal portion of the first dielectric layer is located below the additional dielectric layer.

[0082] Example 13 is the method of Example 12, wherein the additional dielectric layer comprises silicon oxide and has a lower percentage of nitrogen atoms than the first dielectric layer.

[0083] Example 14 is the method of Example 10, further comprising: depositing a second dielectric layer prior to depositing the first dielectric layer, wherein the second dielectric layer comprises silicon oxide and has a lower percentage of nitrogen atoms than the first dielectric layer.

[0084] Example 15 is the method described in Example 10, wherein annealing the first dielectric layer includes a low-temperature wet annealing process, a high-temperature wet annealing process, and a dry annealing process.

[0085] Example 16 is the method of Example 10, wherein, prior to the annealing, the first dielectric layer has a first nitrogen atom percentage, and after the annealing, the first dielectric layer has a second nitrogen atom percentage lower than the first nitrogen atom percentage.

[0086] Example 17 is a method of manufacturing a semiconductor device, comprising: depositing a first silicon oxide layer; depositing a silicon oxynitride layer over the first silicon oxide layer; depositing a second silicon oxide layer over the silicon oxynitride layer; and after depositing the second silicon oxide layer, performing a first wet annealing process and a dry annealing process to convert the silicon oxynitride layer into a third silicon oxide layer.

[0087] Example 18 is the method of Example 17, further comprising: performing a second wet annealing process at a temperature different from the temperatures of the first wet annealing process and the dry annealing process, after the first wet annealing process and before the dry annealing process.

[0088] Example 19 is the method of Example 17, further comprising: etching back the first silicon oxide layer, the silicon oxynitride layer, and the second silicon oxide layer after the first wet annealing process and the dry annealing process.

[0089] Example 20 is the method described in Example 17, wherein, after the first wet annealing process and the dry annealing process, the nitrogen atom percentage of the third silicon oxide layer is higher than the nitrogen atom percentage of the first silicon oxide layer and the second silicon oxide layer.

Claims

1. A method for manufacturing a semiconductor device, comprising: Etching a semiconductor substrate to form a semiconductor strip and a recess, wherein the sidewalls of the semiconductor strip are exposed in the recess; A dielectric layer is deposited into the recess; A capping layer is deposited on the dielectric layer, wherein the capping layer extends into the recess, and the capping layer comprises silicon oxynitride; The remaining portion of the recess is filled with a dielectric material; Perform an annealing process to remove nitrogen from the cap layer; and The dielectric material, the capping layer, and the dielectric layer are recessed, wherein the remaining portions of the dielectric material, the capping layer, and the dielectric layer form an isolation region, and wherein a portion of the semiconductor strip protrudes above the top surface of the isolation region to form a semiconductor fin. The deposition of the cap layer includes an atomic layer deposition (ALD) cycle, wherein the atomic layer deposition (ALD) cycle includes: Hexachlorosilane HCD is delivered to the semiconductor substrate in a pulsed manner and then purged. Oxygen is pulsed onto the semiconductor substrate and purged; and Ammonia gas is delivered to the semiconductor substrate in a pulsed manner and purged.

2. The method according to claim 1, further comprising: After the recess is filled with the dielectric material, a planarization process is performed on the dielectric material, the cap layer, and the dielectric layer, wherein the annealing process is performed through the exposed top edge of the cap layer.

3. The method according to claim 2, wherein, The annealing process is performed before the depression.

4. The method according to claim 1, wherein, The annealing process includes: The low-temperature wet annealing process performed at the first temperature; A high-temperature wet annealing process performed at a second temperature higher than the first temperature; and A dry annealing process performed after the aforementioned high-temperature wet annealing process.

5. The method according to claim 4, wherein, The dry annealing process is performed at a third temperature higher than the first temperature and the second temperature.

6. The method according to claim 4, wherein, The low-temperature wet annealing process is performed at the first temperature, which is in the range of 440°C to 460°C.

7. The method according to claim 4, wherein, The high-temperature wet annealing process is performed at the second temperature, which is in the range of 525°C to 575°C.

8. The method according to claim 4, wherein, The dry annealing process is performed at a third temperature within the range of 650°C to 750°C.

9. A method for manufacturing a semiconductor device, comprising: Forming semiconductor strips; The first dielectric layer is deposited by means of multiple atomic layer deposition (ALD) cycles, wherein each of the multiple atomic layer deposition (ALD) cycles includes: Hexachlorosilane HCD is pulsed onto the semiconductor strip and then purged. Oxygen is pulsed onto the semiconductor strip and purged; and Ammonia gas is pulsed onto the semiconductor strip and purged. Annealing the first dielectric layer; The first dielectric layer is recessed, wherein the remaining portion of the first dielectric layer forms part of an isolation structure, and a portion of the semiconductor strip protrudes above the top surface of the isolation structure to form a semiconductor fin; and Gate stacks are formed extending on the sidewalls and top surface of the semiconductor fin.

10. The method according to claim 9, wherein, In each of the plurality of atomic layer deposition (ALD) cycles, the oxygen is pulsed after the hexachlorosilane (HCD) is pulsed, and the ammonia is pulsed after the oxygen is pulsed.

11. The method of claim 9, further comprising: An additional dielectric layer is deposited on top of the first dielectric layer, wherein, during the annealing of the first dielectric layer, the top edge of the vertical portion of the first dielectric layer is exposed, and the horizontal portion of the first dielectric layer is located below the additional dielectric layer.

12. The method according to claim 11, wherein, The additional dielectric layer comprises silicon oxide and has a lower percentage of nitrogen atoms than the first dielectric layer.

13. The method of claim 9, further comprising: Before depositing the first dielectric layer, a second dielectric layer is deposited, wherein the second dielectric layer comprises silicon oxide and has a lower percentage of nitrogen atoms than the first dielectric layer.

14. The method according to claim 9, wherein, Annealing the first dielectric layer includes low-temperature wet annealing, high-temperature wet annealing, and dry annealing.

15. The method according to claim 9, wherein, Before the annealing, the first dielectric layer has a first nitrogen atom percentage, and after the annealing, the first dielectric layer has a second nitrogen atom percentage lower than the first nitrogen atom percentage.

16. A method for manufacturing a semiconductor device, comprising: Deposit the first silicon oxide layer; A silicon oxynitride layer is deposited on top of the first silicon oxide layer; A second silicon oxide layer is deposited on top of the silicon oxynitride layer; as well as After depositing the second silicon oxide layer, a first wet annealing process and a dry annealing process are performed to convert the silicon oxynitride layer into a third silicon oxide layer. The deposition of the silicon oxynitride layer includes an atomic layer deposition (ALD) cycle, which includes: Hexachlorosilane (HCD) is delivered to the semiconductor substrate in a pulsed manner and then purged. Oxygen is pulsed onto the semiconductor substrate and purged; and Ammonia gas is delivered to the semiconductor substrate in a pulsed manner and purged.

17. The method of claim 16, further comprising: A second wet annealing process is performed after the first wet annealing process and before the dry annealing process, using a temperature different from the temperatures of the first wet annealing process and the dry annealing process.

18. The method of claim 16, further comprising: After the first wet annealing process and the dry annealing process, the first silicon oxide layer, the silicon oxynitride layer and the second silicon oxide layer are etched back.

19. The method of claim 16, wherein, After the first wet annealing process and the dry annealing process, the nitrogen atom percentage of the third silicon oxide layer is higher than that of the first silicon oxide layer and the second silicon oxide layer.

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