Fuse element, semiconductor element, and method for producing fuse element

Abstract

The present disclosure provides a fuse element, a semiconductor element, and a method for manufacturing a fuse element. The fuse element includes an active region having a surface, a fuse dielectric layer extending from the surface of the active region into the active region, and a gate metal layer surrounded by the fuse dielectric layer.

Description

[0001] This invention claims priority and benefits to U.S. Patent Applications No. 17 / 508,965 and No. 17 / 510,747 (i.e., priority dates of October 22, 2021 and October 26, 2021), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a fuse element, a semiconductor element, and a method for fabricating a fuse element. More particularly, it relates to a fuse element having a three-dimensional structure. Background Technology

[0003] Multiple fuses and multiple antifuses are widely used in the manufacture of multiple semiconductor devices, such as dynamic random access memory (DRAM) or other memory devices for fault tolerance, or as multiple programmable links in multiple programmable circuits. For example, activating a fuse (e.g., blowing, melting, etc.) breaks or cuts off an initially conductive circuit path. Conversely, activating an antifuse (e.g., via breakdown, metal diffusion, switching characteristics, etc.) can short-circuit a non-conductive circuit path.

[0004] However, multiple antifuse wires may occupy a large area or space on multiple semiconductor substrates. When multiple semiconductor devices become highly integrated, multiple antifuse wires with suitable dimensions and multiple breakdown conditions are required.

[0005] The above description of "prior art" is merely a background description and does not acknowledge that the subject matter of this disclosure is disclosed. It does not constitute prior art in this disclosure, and no description of the above "prior art" should be considered part of this invention. Summary of the Invention

[0006] The purpose of this invention is to provide a fuse element, a semiconductor element, and a method for preparing the fuse element, so as to solve at least one of the above-mentioned problems.

[0007] One embodiment of this disclosure provides a fuse element. The fuse element includes an active region having a surface; a fuse dielectric layer extending from the surface of the active region into the active region; and a gate metal layer surrounded by the fuse dielectric layer.

[0008] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having an active region; a fuse dielectric layer disposed in the active region; and a gate metal layer disposed in the active region and surrounded by the fuse dielectric layer. The gate metal layer is configured to receive a voltage, thereby changing a resistivity between the gate metal layer and the active region.

[0009] Another embodiment of this disclosure provides a method for fabricating a fuse element. The method includes providing a substrate having an active region; forming a recessed region in the active region; disposing a fuse dielectric layer in the recessed region; and filling the recessed region with a gate metal material.

[0010] By forming a fuse element with a three-dimensional structure, the area consumption of the fuse element of this disclosure is increasingly smaller. The overlap perimeter between the active region and the gate metal layer of the fuse element of this disclosure can be increased without occupying additional areas. A longer overlap perimeter reduces the breakdown voltage and thus increases the likelihood of successful melting of the fuse element of this disclosure.

[0011] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0012] The disclosure of the present invention can be more fully understood by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0013] Figure 1 This is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0014] Figure 2 This is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0015] Figure 3 This is a top view schematic diagram illustrating semiconductor elements of some embodiments of this disclosure.

[0016] Figure 4 This is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0017] Figure 5This is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0018] Figure 6A This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0019] Figure 6B This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0020] Figure 6C This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0021] Figure 6D This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0022] Figure 6E This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0023] Figure 6F This is a cross-sectional schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0024] Figure 7 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0025] The attached figures are labeled as follows:

[0026] 1: Semiconductor components

[0027] 2: Semiconductor components

[0028] 3: Semiconductor components

[0029] 4: Semiconductor components

[0030] 5: Semiconductor components

[0031] 10: Base

[0032] 11: Insulation Structure

[0033] 12: Insulation Structure

[0034] 13: Active region

[0035] 13r: Depression area

[0036] 14: Fuse Dielectric Layer

[0037] 14a: Fuse dielectric layer

[0038] 14b: Fuse dielectric layer

[0039] 14p: Conductive path

[0040] 15: Gate metal layer

[0041] 16: Interlayer dielectric layer

[0042] 17: Conductive embolism

[0043] 18: Conductive layer

[0044] 19: Conductive embolism

[0045] 20: Conductive layer

[0046] 21: Doped region

[0047] 70: Preparation method

[0048] 101: Surface

[0049] 102: Surface

[0050] 111: Surface

[0051] 121: Surface

[0052] 131: Surface

[0053] 141: Surface

[0054] 151: Surface

[0055] 152: Surface

[0056] 153: Side surface

[0057] S71: Steps

[0058] S72: Steps

[0059] S73: Steps

[0060] S74: Steps

[0061] X: Direction

[0062] Y: direction Detailed Implementation

[0063] The various embodiments (or examples) of this disclosure described in the accompanying drawings are now described using specific language. It should be understood that this is not intended to limit the scope of the disclosure. Any changes or modifications to the various embodiments described, and any further application of the principles described herein, are considered to be common practice for those skilled in the art to which this disclosure pertains. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0064] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0065] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, the plurality of terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0066] Figure 1 This is a cross-sectional schematic diagram illustrating a semiconductor element 1 according to some embodiments of the present disclosure.

[0067] In some embodiments, semiconductor element 1 may be disposed adjacent to a circuit. For example, semiconductor element 1 may be disposed adjacent to a memory element, such as dynamic random access memory (DRAM) or the like. In some embodiments, semiconductor element 1 may include a fuse array structure or a portion thereof. In some embodiments, semiconductor element 1 may include a fuse element. As used herein, the term fuse element refers to a semiconductor element that functions as an antifuse, is normally open, and can be melted to become a short circuit when a voltage is applied.

[0068] like Figure 1As shown, in some embodiments, the semiconductor element 1 may include a substrate 10, insulating structures 11 and 12, an active region 13, a fuse dielectric layer 14, a gate metal layer 15, an interlayer dielectric layer 16, a conductive plug 17, and a conductive layer 18.

[0069] In some embodiments, the substrate 10 may include a surface 101 and a surface 102, with the surface 102 disposed opposite to the surface 101. In some embodiments, the surface 101 may be an active surface of the substrate 10, and the surface 102 may be a rear surface of the substrate 10.

[0070] In some embodiments, for example, the substrate 10 may include Si, Ge, SiGe, SiC, SiGeC, Ga, GaAs, In, InAs, InP, or other group IV-IV, III-V, or II-VI semiconductor materials. In some other embodiments, the substrate 10 includes a layered semiconductor, such as silicon / silicon-germanium, silicon-on-insulator, or silicon-germanium-on-insulator.

[0071] In some embodiments, insulating structures 11 and 12 may be disposed on or within substrate 10. In some embodiments, insulating structures 11 and 12 may be disposed within active region 13. In some embodiments, insulating structures 11 and 12 may include shallow trench isolation (STI).

[0072] In some embodiments, the insulating structure 11 may have a surface (or an upper surface) 111 that is substantially coplanar with the surface 101 of the substrate 10. Similarly, the insulating structure 12 may have a surface (or an upper surface) 121 that is substantially coplanar with the surface 101 of the substrate 10. In some embodiments, surfaces 111 and 121 may be exposed from the substrate 101 (e.g., exposed from the surface 101 of the substrate 10). In some embodiments, surfaces 111 and 121 may be exposed from the active region 13 (e.g., exposed from a surface 131 of the active region 13).

[0073] In some embodiments, each of the insulating structures 11 and 12 may include an insulating material, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), or fluorine-doped silicon oxide. In some embodiments, the insulating structures 11 and 12 may define one or more active regions or multiple active regions of the substrate 10.

[0074] In some embodiments, the active region 13 may be disposed on or within the substrate 10. In some embodiments, the active region 13 may be disposed on or near the surface 101 of the substrate 10. In some embodiments, the active region 13 may have a surface (or an upper surface) 131 exposed from the surface 101 of the substrate 10. In some embodiments, the surface 131 of the active region 13 may be substantially coplanar with the surface 101 of the substrate 10. In some embodiments, the active region 13 may be disposed between the insulating structures 11 and 12. For example, a portion of the active region 13 may be disposed between the insulating structures 11 and 12.

[0075] In some embodiments, the active region 13 may be doped with an N-type dopant, such as P, As, or Sb. In some embodiments, the active region 13 may be doped with a P-type dopant, such as B or In. In some embodiments, the substrate 10 may be or include an unimplanted region. In some embodiments, the active region may have a higher doping concentration than the substrate 10.

[0076] In some embodiments, the active region 13 may include a substantially constant doping concentration. For example, a fuse dielectric layer 14 may be surrounded by the active region 13, which has a substantially constant doping concentration. In some embodiments, the doping concentration of the active region 13 between the insulating structure 11 and the fuse dielectric layer 14 may be substantially constant or uniform. In some embodiments, the doping concentration of the active region 13 between the insulating structure 12 and the fuse dielectric layer 14 may be substantially constant or uniform. In other words, the doping concentration around the fuse dielectric layer 14 may be substantially constant or uniform.

[0077] In some embodiments, the active region 13 may include a step, gradient, or other doping profile. For example, the active region 13 may include a gradient doping concentration. For example, the doping concentration of the active region 13 may gradually decrease toward the surface 102 of the substrate 10. Thus, in some embodiments, the fuse dielectric layer 14 may be surrounded by the active region 13, and the active region 13 has a step, gradient, or other doping profile. For example, in some embodiments, the doping concentration of the active region 13 between the insulating structure 11 and the fuse dielectric layer 14 may be substantially gradient. In some embodiments, the doping concentration of the active region 13 between the insulating structure 12 and the fuse dielectric layer 14 may be substantially gradient.

[0078] According to some embodiments of this disclosure, a fuse element (including an active region 13, a fuse dielectric layer 14, and a gate metal layer 15) may have a structure different from that of a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or a metal-insulator-semiconductor field-effect transistor (MISFET). For example, the fuse element may not be or may include a transistor. For example, the fuse element may be surrounded by a doped region (e.g., active region 13) having a uniform step, slope, or other doped profile. For example, the fuse element may not have two additional terminals (e.g., a source and a drain) connected to individual highly doped regions, the plurality of highly doped regions being separated by a body region (e.g., a block-shaped substrate). For example, the fuse element may not have a depletion region extending between the source and drain. For example, the fuse element may not have a conducting channel extending between the source and drain.

[0079] In some embodiments, the fuse dielectric layer 14 may be disposed in the active region 13. In some embodiments, the fuse dielectric layer 14 may be at least partially surrounded by the active region 13. In some embodiments, the fuse dielectric layer 14 may at least partially penetrate or extend into the active region 13. In some embodiments, the fuse dielectric layer 14 may extend from the surface 131 of the active region 13 into the active region 13. In some embodiments, the active region 13 may include a recess (e.g., in...). Figure 6B The recessed region 13r is recessed or recessed into the substrate 10, and the fuse dielectric layer 14 can be disposed in the recess.

[0080] In some embodiments, the fuse dielectric layer 14 may have a surface (or an upper surface) 141 that is exposed from the surface 131 of the active region 13. In some embodiments, the surface 141 of the fuse dielectric layer 14 may be substantially coplanar with the surface 131 of the active region 13.

[0081] In some embodiments, the fuse dielectric layer 14 may include silicon monoxide (SiO2), metal oxide, or the like.

[0082] In some embodiments, a fuse dielectric layer 14 may be formed during a manufacturing process, for example, during which a gate dielectric layer of a buried gate structure of an adjacent circuit is formed. In these embodiments, the fuse dielectric layer 14 may include a material identical to that of the gate dielectric layer, such as HfO2, HfSiO4, La2O3, LaAlO3, ZrO2, ZrSiO4, Al2O3, other materials, or combinations thereof.

[0083] In some embodiments, a gate metal layer 15 may be disposed in an active region 13. In some embodiments, the gate metal layer 15 may be at least partially surrounded by a fuse dielectric layer 14 and also surrounded by the active region 13. In some embodiments, the gate metal layer 15 may at least partially penetrate or extend into the fuse dielectric layer 14. In some embodiments, the gate metal layer 15 may extend from the surface 141 of the fuse dielectric layer 14 into the fuse dielectric layer 14. In some embodiments, the fuse dielectric layer 14 may include a recess (e.g., in...). Figure 6B and Figure 6C The recessed region 13r is recessed or recessed into the substrate 10, and the gate metal layer 15 may be disposed in the recess.

[0084] In some embodiments, the gate metal layer 15 may have a surface (or an upper surface) 151, a surface (or a lower surface) 152 and a side surface 153, the surface 151 being away from the substrate 10, the surface 152 being disposed opposite to the surface 151, and the side surface 153 extending between the surface 151 and the surface 152.

[0085] In some embodiments, the surface 151 of the gate metal layer 15 may be exposed from the surface 131 of the active region 13. In some embodiments, the surface 151 of the gate metal layer 15 may be substantially coplanar with the surface of the active region 1312. In some embodiments, the surface 151 of the gate metal layer 15 may be substantially coplanar with the surface 141 of the fuse dielectric layer 14.

[0086] In some embodiments, the surface 152 of the gate metal layer 15 may face the substrate 10. In some embodiments, the surface 152 of the gate metal layer 15 may include a bowl-shaped profile, a U-shaped profile, or other possible profiles, but is not limited thereto.

[0087] In some embodiments, the surface 153 of the gate metal layer 15 may be non-parallel to the surface 101 of the substrate 10 or may be at an angle to the surface 101 of the substrate 10. In some embodiments, the surface 153 of the gate metal layer 15 may be surrounded by the fuse dielectric layer 14. In some embodiments, the surface 153 of the gate metal layer 15 may be covered by the fuse dielectric layer 14. In some embodiments, the surface 153 of the gate metal layer 15 may contact (e.g., directly contact) the fuse dielectric layer 14.

[0088] In some embodiments, the gate metal layer 15 may be disposed adjacent to the insulating structure 11 and / or the insulating structure 12. In some embodiments, the surface 153 of the gate metal layer 15 may face the insulating structures 11 and 12.

[0089] In some embodiments, the gate metal layer 15 may include polysilicon, TiN, W, or the like. In some embodiments, the gate metal layer 15 may be formed during a manufacturing process, for example, to manufacture a gate electrode of a buried gate structure for an adjacent circuit. In this embodiment, the fuse dielectric layer 14 may include a material that is the same as the material of the gate electrode.

[0090] In some embodiments, the interlayer dielectric layer 16 may be disposed on the substrate 10 and contact a portion of the surface 101 of the substrate 10. In some embodiments, the interlayer dielectric layer 16 may contact the surface 111 of the insulating structure 11 and the surface 121 of the insulating structure 12. In some embodiments, the interlayer dielectric layer 16 may contact the surface 131 of the active region 13. In some embodiments, the interlayer dielectric layer 16 may contact the surface 141 of the fuse dielectric layer 14. In some embodiments, the interlayer dielectric layer 16 may contact the surface 151 of the gate metal layer 15.

[0091] In some embodiments, the interlayer dielectric layer 16 may include a suitable dielectric material. For example, the interlayer dielectric layer 16 may include Si3N4, N2OSi2, N2OSi2, Ta2O5, Al2O3, SrBi2Ta2O9, BaSrTiO3, or a combination thereof.

[0092] In some embodiments, the conductive plug 17 may penetrate or extend into the interlayer dielectric layer 16. In some embodiments, the conductive plug 17 may be disposed on the surface 151 of the gate metal layer 15. In some embodiments, the conductive plug 17 may contact the surface 151 of the gate metal layer 15. For example, a portion of the surface 151 of the gate metal layer 15 may be covered by the conductive plug 17, while another portion of the surface 151 of the gate metal layer 15 may be covered by the interlayer dielectric layer 16. In some embodiments, the conductive plug 17 may be electrically connected to the gate metal layer 15.

[0093] In some embodiments, the conductive plug 17 may include a suitable conductive material. For example, the conductive plug 17 may include W, Cu, Al, Ag, alloys thereof, or combinations thereof.

[0094] In some embodiments, the conductive layer 18 may be disposed on the interlayer dielectric layer 16 and electrically connected to the conductive plug 17.

[0095] In some embodiments, the conductive layer 18 may include a suitable conductive material. For example, the conductive layer 18 may include W, Cu, Al, Ag, alloys thereof, or combinations thereof. In some embodiments, the conductive layer 18 and the conductive plug 17 may include the same conductive material. In some embodiments, the conductive layer 18 and the conductive plug 17 may include different conductive materials.

[0096] Figure 2This is a cross-sectional schematic diagram illustrating a semiconductor element 2 according to some embodiments of the present disclosure. Figure 2 Semiconductor element 2 is similar to Figure 1 Semiconductor element 1, except for the differences described below.

[0097] In some embodiments, such as Figure 1 As shown, the active region 13 may be deeper than the insulating structures 11 and 12. For example, the bottom of the insulating structures 11 and 12 may be covered or surrounded by the active region 13. However, in some other embodiments, such as Figure 2 As shown, the insulating structures 11 and 12 can extend beyond the active region 13 and into the substrate 10.

[0098] In some embodiments, the doping depth of the active region 13 can be adjusted to suit various applications using the semiconductor element 2. For example, the doping depth of the active region 13 may be shallower than the insulating structures 11, 12, but deeper than the fuse dielectric layer 14, so as to cover or surround the fuse dielectric layer 14.

[0099] Figure 3 This is a top view schematic diagram illustrating a semiconductor element 3 according to some embodiments of the present disclosure. In some embodiments, Figure 1 Semiconductor element 1 and Figure 2 Semiconductor element 2 can be Figure 3 A schematic diagram of the cross section as seen by section line AA'.

[0100] like Figure 3 As shown, insulating structures 11 and 12 can be formed on the substrate ( Figure 3 Not shown in the text, for example Figure 1 A strip-like structure extending along a first direction on a base 10). The first direction is, for example... Figure 3 The direction Y is shown. Similarly, the active region 13 can be formed on the substrate ( Figure 3 Not shown in the text, for example Figure 1 A strip-like structure extending along the Y direction on the substrate 10. The active region 13 may be disposed between the insulating structures 11 and 12.

[0101] Conductive layers 18 and 20 may be formed on the interlayer dielectric layer 16 in a strip-like structure extending along a second direction, such as... Figure 2 The direction X is shown. In some embodiments, the conductive layer 18 may be formed on the conductive plug 17 and electrically connected to the gate metal layer ( Figure 3 Not shown in the text, for example Figure 1 (Gate metal layer 15 in the middle). In some embodiments, the conductive layer 20 may be formed on a conductive plug 19 and electrically connected to the active region 13.

[0102] In some embodiments, conductive plug 19 may be similar to conductive plug 17. In some embodiments, conductive layer may be similar to conductive layer 18.

[0103] In some embodiments, conductive layers 18 and 20 may be, or be a portion thereof, of bit lines and / or word lines arranged in multiple rows and columns. In some instances, the bit lines and / or word lines arranged in multiple rows and columns may be generally orthogonal. For example, bit lines may be generally orthogonal to word lines. In some embodiments, bit lines may be electrically insulated from each other. In some embodiments, word lines may be electrically insulated from each other.

[0104] Figure 4 This is a cross-sectional schematic diagram illustrating a semiconductor element 4 according to some embodiments of the present disclosure. In some embodiments, Figure 4 Semiconductor element 4 can be Figure 3 A schematic diagram of the cross section as seen by section line BB'.

[0105] like Figure 4 As shown, the semiconductor device 4 includes a doped region 21 disposed within the active region 13. In some embodiments, the doped region 21 may have a depth less than or shallower than a depth of the active region 13. For example, the doped region 21 may be located within the active region 13. In some embodiments, a conductive plug 19 may be disposed on the doped region 21. In some embodiments, the conductive plug 19 and the doped region 21 may form a low-impedance ohmic contact.

[0106] In some embodiments, the doped region 21 and the active region 13 may be doped with different dopants. For example, the doped region 21 may be a P-type doped region, and the active region 13 may be an N-type doped region.

[0107] In some embodiments, the doped region 21 may be omitted. For example, a conductive plug 19 may be disposed on the active region 13.

[0108] In some embodiments, the gate metal layer 15 may be connected to or coupled to a voltage Vcc (e.g., a pumped voltage, a programmed power supply voltage, a bias voltage, etc.). In some embodiments, the active region 13 may be grounded or maintained at a substrate potential. In some embodiments, the semiconductor device 4 may be activated when the voltage exceeds a threshold voltage (e.g., a breakdown voltage). For example, a conductive path 14p may be formed across the fuse dielectric layer 14, thereby creating an open circuit in the semiconductor device to become a short circuit or a relatively low impedance link or node.

[0109] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0110] In some embodiments, after a breakdown voltage is applied between the gate metal layer 15 and the active region 13, the fuse dielectric layer 14 may undergo a dielectric breakdown process or a characteristic transition. In some embodiments, the fuse dielectric layer 14 may be damaged. In some embodiments, the lattice structure of the fuse dielectric layer 14 may be altered. In some embodiments, a defect may be formed in the fuse dielectric layer 14. In some embodiments, the gate metal layer 15 and the active region 13 may be electrically connected via the fuse dielectric layer 14. In some embodiments, after a breakdown voltage is applied between the gate metal layer 15 and the active region 13, the conductivity of the fuse dielectric layer 14 may increase by approximately 1000 times, approximately 10000 times, or more. In some embodiments, after a breakdown voltage is applied between the gate metal layer 15 and the active region 13, the resistivity of the fuse dielectric layer 14 may be reduced.

[0111] It should be understood that the conductive path 14p across the fuse dielectric layer 14 is described only for better understanding and may not be observed when a breakdown voltage is applied.

[0112] In some embodiments, the voltage applied to the gate metal layer 15 can be controlled by a voltage controlled by a switching circuit, for example, which may include one or more pass gates, one or more select gates, etc. According to some embodiments of this disclosure, the multiple select gates can be configured to select and control the multiple pass gates. For example, the multiple pass gates can be controlled by a logic signal that can be output from the multiple select gates.

[0113] Figure 5 This is a cross-sectional schematic diagram illustrating a semiconductor element 5 according to some embodiments of the present disclosure. Figure 5 The semiconductor element 5 is similar to Figure 1 Semiconductor element 1, except for the differences described below.

[0114] In some embodiments, such as Figure 1 As shown, the fuse dielectric layer 14 may comprise a single layer or a single layer. However, in some other embodiments, such as Figure 5 As shown, the fuse dielectric layer 14 may include multiple dielectric layers stacked on top of each other.

[0115] For example, in some embodiments, the active region 13 may include a recess that is recessed into or recessed into the substrate 10, and fuse dielectric layers 14a, 14b may be disposed in the recess. In some embodiments, dielectric layer 14b may be disposed on dielectric layer 14a. In some embodiments, dielectric layer 14b is disposed between dielectric layer 14a and gate metal layer 15. In some embodiments, dielectric layer 14a may contact (e.g., directly contact) the active region 13. In some embodiments, dielectric layer 14b may contact (e.g., directly contact) the gate metal layer 15.

[0116] In some embodiments, dielectric layers 14a and 14b may be made of the same material but formed using different processes. In some embodiments, dielectric layers 14a and 14b may be made of different materials. In some embodiments, according to some embodiments of this disclosure, dielectric layers 14a and 14b may be adjusted to obtain different dielectric breakdown characteristics.

[0117] In a comparative embodiment, a fuse element may include a metal-oxide-semiconductor structure (e.g., a MOS structure). The MOS structure is a planar structure (or a two-dimensional structure) consisting of a planar metal layer and a planar oxide layer stacked on an active region. Such a planar structure occupies a large area on the semiconductor substrate. As semiconductor devices become highly integrated, fuse elements with suitable dimensions and breakdown conditions are required.

[0118] By forming a fuse element with a three-dimensional structure, the area occupied by the fuse element of this disclosure is gradually reduced. For example, the overlap region between the active region 13 and the gate metal layer 15 can be reduced by more than 40 times, for example from about 60nm*120 to about 26nm*17nm.

[0119] Furthermore, the overlap between the active region 13 and the gate metal layer 15 of the fuse element (or fuse element, fuse element, fuse element, fuse element) of this disclosure can be increased without occupying other areas. A longer overlap can reduce the breakdown voltage and thus increase the likelihood of successful fusing of the fuse element of this disclosure.

[0120] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F These are cross-sectional schematic diagrams illustrating various stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure. For the purpose of better understanding the present disclosure, at least some of these figures have been simplified. In some embodiments, Figure 1 Semiconductor element 1 in the middle can be used relative to Figure 6A , Figure 6B , Figure 6C, Figure 6D , Figure 6E , Figure 6F It is manufactured by following the steps described below.

[0121] Please refer to Figure 6A A substrate 10 may be provided. Insulating structures 11 and 12 may be disposed on or within the substrate 10. An active region 13 may be defined by the insulating structures 11 and 12. In some embodiments, the fabrication technique of the insulating structures 11 and 12 may include trench etching followed by filling the trenches with a dielectric material. In some embodiments, the fabrication technique of the active region 13 may include doping impurities via ion implantation or thermal diffusion. In some embodiments, the active region 13 may be formed on or near the surface 101 of the substrate 10. In some embodiments, the active region 13 may be formed after the insulating structures 11 and 12 are formed. In some other embodiments, the active region 13 may be formed before the insulating structures 11 and 12 are formed.

[0122] Please refer to Figure 6B A recessed region 13r may be formed in the active region 13. In some embodiments, the fabrication technique of the recessed region 13r may include photolithography and etching techniques. In some embodiments, the recessed region 13r may have a depth that is shallower than the depth of the active region 13. In some embodiments, the recessed region 13r may have a depth that is shallower than the depth of the insulating structures 11, 12. In some embodiments, the recessed region 13r is formed in a manner such that the substrate 10 is not exposed through the recessed region 13r.

[0123] Please refer to Figure 6C The fuse dielectric layer 14 may be disposed in the recessed region 13r of the active region 13. In some embodiments, the fabrication technique of the fuse dielectric layer 14 may include a thermal oxidation process. In some embodiments, the fabrication technique of the fuse dielectric layer 14 may include an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a combination thereof. For example, the fabrication technique of the fuse dielectric layer 14 may include forming one layer via an ALD process and then forming another layer via a CVD process. In some embodiments, the fuse dielectric layer 14 may be disposed on the surface 131 of the active region 13, on the surface 1212 of the insulating structure 12, on the surface 111 of the insulating structure 11, and / or on the surface 101 of the substrate 10.

[0124] Please refer to Figure 6DFor example, a gate metal material can be formed by CVD or low-pressure chemical vapor deposition (LPCVD) to fill the recessed region 13r in the active region 13, thus forming a gate metal layer 15. The surface 153 of the gate metal layer 15 may be non-parallel to the surface 101 of the substrate 10 or at an angle to the surface 101 of the substrate 10. In some embodiments, the surface 153 of the gate metal layer 15 may be surrounded by a fuse dielectric layer 14. In some embodiments, the surface 153 of the gate metal layer 15 may be covered by the fuse dielectric layer 14. In some embodiments, the surface 15 of the gate metal layer 15 may contact (e.g., directly contact) the fuse dielectric layer 14.

[0125] Please refer to Figure 6E A planarization process, such as chemical mechanical polishing (CMP), can be performed. After the planarization process, the surface 151 of the gate metal layer 15, the surface 141 of the fuse dielectric layer 14, the surface 131 of the active region 13, the surface 121 of the insulating structure 12, the surface 111 of the insulating structure 11, and / or the surface 101 of the substrate 10 may be substantially coplanar.

[0126] Please refer to Figure 6F For example, the interlayer dielectric layer 16 can be formed by ALD, CVD, physical vapor deposition (PVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), coating, etc. An opening can be formed in the interlayer dielectric layer 16 by photolithography and etching techniques. A conductive material of the conductive plug 17 can be formed in the opening in the interlayer dielectric layer 16. The fabrication techniques for the conductive material can include suitable techniques such as electroplating or an electroless plating process, CVD, PVD, etc. Similar processes can be repeated to form the conductive layer 18 and other conductive elements (if any) on the conductive plug 17.

[0127] In some embodiments, after forming the conductive plug 17 and the conductive layer 18, the method may further include connecting the gate metal layer 15 to a power supply to apply a voltage to the gate metal layer 15, thereby causing an open circuit in the semiconductor device to become a short circuit or a relatively low impedance link or node.

[0128] In some embodiments, during a manufacturing process, operations relative to... Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6FThe described steps, for example, involve fabricating a buried gate structure for an adjacent circuit. For example, during a fabrication process, a recessed region 13r may be formed; for example, this fabrication process involves fabricating a gate trench. For example, during a fabrication process, a fuse dielectric layer 14 may be formed; for example, this fabrication process involves fabricating a gate dielectric layer for a buried gate structure. For example, during a fabrication process, a gate metal layer 15 may be formed; for example, this fabrication process involves fabricating a gate electrode for a buried gate structure.

[0129] Figure 7 This is a flowchart illustrating a method 70 for fabricating a semiconductor element according to some embodiments of this disclosure.

[0130] In some embodiments, the fabrication method 70 may include a step S71, providing a substrate having an active region disposed on or near a surface of the substrate. For example, such as Figure 6A As shown, a substrate 10 may be provided, the substrate 10 having an active region 13 disposed on or near the surface 101 of the substrate 10.

[0131] In some embodiments, the fabrication method 70 may include a step S72, forming a recessed region in the active region. For example, such as Figure 6B As shown, the recessed region 13r can be formed in the active region 13.

[0132] In some embodiments, the fabrication method 70 may include a step S73, which involves depositing a fusible dielectric layer in the recessed region. For example, such as Figure 6C As shown, the fuse dielectric layer 14 can be disposed in the recessed region 13r.

[0133] In some embodiments, the fabrication method 70 may include a step S74, in which a gate metal material is used to fill the recessed region. For example, such as Figure 6D As shown, a gate metal material can be deposited to fill the recessed region 13r.

[0134] One embodiment of this disclosure provides a fuse element. The fuse element includes an active region having a surface; a fuse dielectric layer extending from the surface of the active region into the active region; and a gate metal layer surrounded by the fuse dielectric layer.

[0135] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate having an active region; a fuse dielectric layer disposed in the active region; and a gate metal layer disposed in the active region and surrounded by the fuse dielectric layer. The gate metal layer is configured to receive a voltage, thereby changing a resistivity between the gate metal layer and the active region.

[0136] Another embodiment of this disclosure provides a method for fabricating a fuse element. The method includes providing a substrate having an active region; forming a recessed region in the active region; disposing a fuse dielectric layer in the recessed region; and filling the recessed region with a gate metal material.

[0137] By forming a fuse element with a three-dimensional structure, the area consumption of the fuse element of this disclosure is increasingly smaller. The overlap perimeter between the active region and the gate metal layer of the fuse element of this disclosure can be increased without occupying additional areas. A longer overlap perimeter reduces the breakdown voltage and thus increases the likelihood of successful melting of the fuse element of this disclosure.

[0138] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0139] Furthermore, the scope of this invention is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this invention.

Claims

1. A fuse element, comprising: An active region has a surface; A fused dielectric layer extends from the surface of the active region into the active region; as well as A gate metal layer is surrounded by the fuse dielectric layer. The gate metal layer has a side surface that is angled to the surface of the active region and contacts the fuse dielectric layer. An insulating structure is disposed within the active region, wherein the side surface of the gate metal layer faces the insulating structure. The doping concentration between the insulating structure of the active region and the dielectric layer of the fuse is gradient.

2. The fuse element of claim 1, wherein the gate metal layer includes an upper surface that is coplanar with the surface of the active region.

3. The fuse element of claim 2 further includes a substrate disposed around the active region, wherein the upper surface of the gate metal layer, the surface of the active region, and an upper surface of the substrate are coplanar with each other.

4. The fuse element of claim 1, wherein the insulating structure has an upper surface that is coplanar with the surface of the active region.

5. The fuse element of claim 1, wherein the fuse dielectric layer includes an upper surface exposed from the active region and is coplanar with the surface of the active region.

6. The fuse element of claim 1 further includes a substrate disposed around the active region, wherein the active region includes a higher doping concentration than the substrate.

7. The fuse element as claimed in claim 1, further comprising: A first conductive plug is electrically connected to the gate metal layer; as well as A second conductive plug is electrically connected to the active region.

8. The fuse element as claimed in claim 7 further includes a doped region disposed in the active region, wherein the doped region and the active region are doped with different dopants, and the second conductive plug is disposed on the doped region.

9. A method for preparing a fuse element, comprising: A substrate is provided, the substrate having an active region; A depression is formed in the active region; A fusible dielectric layer is disposed in the recessed area; as well as The recessed area is filled with a gate metal material, wherein the gate metal layer has a side surface that is angled to the surface of the active region and contacts the fuse dielectric layer. It also includes forming an insulating structure in the active region, wherein the side surface of the gate metal layer faces the insulating structure; The doping concentration between the insulating structure of the active region and the dielectric layer of the fuse is gradient.

10. The method of fabricating a fuse element as claimed in claim 9, wherein the active region includes a higher doping concentration than the substrate, and the recessed region is formed in a manner such that the substrate is not exposed through the recessed region.

11. The method for preparing a fuse element as described in claim 9, wherein the fabrication technique of the fuse dielectric layer includes an atomic layer deposition process, a chemical vapor deposition process, or a combination thereof.

12. The method for fabricating a fuse element as claimed in claim 9 further includes forming a gate metal layer having an upper surface that is coplanar with an upper surface of the active region.

13. The method for fabricating a fuse element as described in claim 12 further includes forming a conductive plug for electrical connection with the gate metal layer.

14. A semiconductor element, comprising: A substrate with an active region; A fusible dielectric layer is disposed in the active region; as well as A gate metal layer is disposed in the active region and surrounded by the fuse dielectric layer; The gate metal layer is configured to receive a voltage, thereby changing the resistivity between the gate metal layer and the active region. The gate metal layer has a side surface that is angled to the surface of the active region and contacts the fuse dielectric layer. It also includes an insulating structure disposed within the active region, wherein the side surface of the gate metal layer faces the insulating structure; The doping concentration between the insulating structure of the active region and the dielectric layer of the fuse is gradient.

15. The semiconductor device of claim 14, wherein the gate metal layer is configured to be electrically connected to the active region via the fuse dielectric layer when the voltage is above a threshold voltage.

16. The semiconductor device of claim 14, wherein the gate metal layer includes an upper surface that is coplanar with the surface of the active region.

17. The semiconductor device of claim 16, wherein the upper surface of the gate metal layer, the surface of the active region, and an upper surface of the substrate are coplanar with each other.

18. The semiconductor device of claim 14, wherein the insulating structure has an upper surface that is coplanar with the surface of the active region.

19. The semiconductor device of claim 14, wherein the fuse dielectric layer includes an upper surface exposed from the active region and is coplanar with the surface of the active region.

20. The semiconductor device of claim 14, wherein the active region includes a higher doping concentration than the substrate.

21. The semiconductor device of claim 14, further comprising: A first conductive plug is electrically connected to the gate metal layer; as well as A second conductive plug is electrically connected to the active region.

22. The semiconductor device of claim 21 further includes a doped region disposed in the active region, wherein the doped region and the active region are doped with different dopants, and the second conductive plug is disposed on the doped region.

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