Electronic device and method of manufacturing the same

Abstract

A method of manufacturing an electronic device is provided. The method includes providing a substrate, forming a thin film transistor layer on the substrate, forming a first passivation layer on the substrate, forming an organic layer on the substrate, patterning the organic layer to expose a first region, forming a second passivation layer on the substrate, patterning the first passivation layer to expose a second region, forming a bonding pad on the substrate and corresponding to an overlapping region of the first region and the second region, and bonding an electronic component on the bonding pad. An electronic device is also provided.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing an electronic device, and more particularly to a method for manufacturing an electronic device that can improve the structural reliability of the electronic device, and an electronic device formed by such method. Background Technology

[0002] Electronic products, including display panels, such as tablets, laptops, smartphones, monitors, and televisions, have become indispensable necessities in modern society. With the rapid development of various electronic products, consumers have high expectations for their quality, functionality, and price.

[0003] Electronic components in electronic devices are typically bonded or electrically connected to the substrate via bonding pads, solder pads, or other conductive components. However, due to the difference in the coefficient of thermal expansion (CTE) between the substrate and the light-emitting component, the joint between the substrate and the light-emitting component is easily affected by stress when the temperature changes, resulting in cracks or peeling, which in turn causes problems such as abnormal electrical connection of the driving circuit.

[0004] As mentioned above, existing electronic devices that include display panels still do not meet the requirements in all aspects. Therefore, developing manufacturing methods that can further improve the structural reliability of electronic devices remains one of the topics that the industry is currently focusing on researching. Summary of the Invention

[0005] According to some embodiments of the present disclosure, a method for manufacturing an electronic device is provided, comprising the following steps: providing a substrate; forming a thin-film transistor layer on the substrate; forming a first passivation layer on the substrate; forming an organic layer on the substrate; patterning the organic layer to expose a first region; forming a second passivation layer on the substrate; patterning the first passivation layer to expose a second region; forming a bonding pad on the substrate and corresponding to an overlapping region of the first and second regions; and bonding an electronic component to the bonding pad.

[0006] According to some embodiments of this disclosure, an electronic device is provided, comprising a substrate, a thin-film transistor layer, a first passivation layer, an organic layer, a second passivation layer, a bonding pad, and an electronic component. The thin-film transistor layer is disposed on the substrate. The first passivation layer is disposed on the thin-film transistor layer and has a first portion and a second portion, the first portion being an opening or a recess, and the second portion being adjacent to the first portion. The organic layer is disposed on the first passivation layer and has an opening. The second passivation layer is disposed on the organic layer. The bonding pad is disposed on the thin-film transistor layer and corresponds to the overlapping area of ​​the first portion of the first passivation layer and the opening of the organic layer. The electronic component is bonded to the bonding pad. Attached Figure Description

[0007] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0008] Figure 1 This diagram shows a cross-sectional structural schematic of an electronic device according to some embodiments of the present disclosure;

[0009] Figure 2 This diagram shows a cross-sectional structural schematic of an electronic device according to some embodiments of the present disclosure;

[0010] Figure 3 This diagram shows a cross-sectional structural schematic of an electronic device according to some embodiments of the present disclosure;

[0011] Figure 4 This diagram shows a cross-sectional structural schematic of an electronic device according to some embodiments of the present disclosure;

[0012] Figures 5 to 11B This diagram shows a cross-sectional view of an electronic device at an intermediate stage of manufacturing, according to some embodiments of the present disclosure.

[0013] Figure 12A as well as Figure 12B This diagram shows a cross-sectional view of an electronic device at an intermediate stage of manufacturing, according to some embodiments of the present disclosure.

[0014] Figure 1-12B The numbering is explained as follows:

[0015] 10A, 10B, 10C, 10D: Electronic devices

[0016] 100: Substrate

[0017] 100T: Thin-film transistor layer

[0018] 100s: Semiconductor layer

[0019] 102: First insulating layer

[0020] 104: Second insulating layer

[0021] 104t: Top surface

[0022] 106: Buffer layer

[0023] 202: First passivation layer

[0024] 202R: Region

[0025] 202P-1: Part One

[0026] 202P-2: Part Two

[0027] 204: Second passivation layer

[0028] 206: Third passivation layer

[0029] 302: Organic layer

[0030] 302R: Area

[0031] 302p: Opening

[0032] 400a, 400b, 400c: Conductive layers

[0033] 402: Joint pad

[0034] 402v: Guide hole

[0035] 404: solder pad

[0036] 406: Welding materials

[0037] 500: Electronic Components

[0038] 502: Conductor frame

[0039] 504: Conductive structure

[0040] A1: Circuit Area

[0041] A2: Junction area

[0042] CP: Contact Zone

[0043] D1: Distance

[0044] D2: Thickness difference

[0045] E1, E2: Edges

[0046] NP: Non-contact area

[0047] V1, V2, V3: Through holes Detailed Implementation

[0048] The following provides a detailed description of an electronic device and a method for manufacturing the electronic device according to embodiments of the present disclosure. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of the present disclosure. The specific components and arrangements described below are merely for simple and clear description of some embodiments of the present disclosure. Of course, these are merely examples and not limitations of the present disclosure. Furthermore, similar and / or corresponding reference numerals may be used in different embodiments to identify similar and / or corresponding components for clear description of the present disclosure. However, the use of these similar and / or corresponding reference numerals is only for simple and clear description of some embodiments of the present disclosure and does not represent any association between the different embodiments and / or structures discussed.

[0049] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in the embodiments to describe the relative relationship of one component of the figures to another. It is understood that if the apparatus in the figures is flipped upside down, the component described as being on the "lower" side will become the component on the "higher" side. Embodiments of this disclosure can be used in conjunction with the accompanying drawings. Figure 1 It should be understood that the accompanying drawings of this disclosure are also considered part of the disclosure. It should be understood that the drawings of this disclosure are not drawn to scale, and in fact, the dimensions of components may be arbitrarily enlarged or reduced to clearly show the features of this disclosure.

[0050] Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it may include situations where the first material layer and the second material layer are in direct contact, or situations where the first material layer and the second material layer are not in direct contact, that is, situations where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is located directly on the second material layer, it indicates that the first material layer and the second material layer are in direct contact.

[0051] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify components, do not in themselves imply any prior ordinal number for that (or those) component, nor do they represent the order of one component with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named component from another component with the same name. The claims and specification may not use the same terminology; for example, the first component in the specification may be the second component in the claims.

[0052] In some embodiments of this disclosure, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding engagement and connection may also include cases where both structures are movable or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect electrical connection means.

[0053] In this text, the terms "approximately" and "substantially" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantities are approximate; that is, even without specific mention of "approximately" or "substantially," their meaning is implied. The phrase "the range is between the first and second values" indicates that the range includes the first value, the second value, and other values ​​in between.

[0054] It should be understood that the features described below can be replaced, reorganized, or combined in several different embodiments to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that such terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in embodiments of this disclosure.

[0056] According to embodiments of this disclosure, a method for manufacturing an electronic device is provided, which can improve the structural strength of the bonding pad and electronic component joint in the formed electronic device, reduce the risk of substrate cracking or electronic component peeling off from the substrate, thereby improving the reliability of the electronic device.

[0057] According to embodiments of this disclosure, the electronic device may include a display device, a backlight device, a touch device, a sensing device, an antenna device, or a splicing device (a splicing device having any or a combination of the above functions), but is not limited thereto. The electronic device may include a bendable electronic device or a flexible electronic device, but is not limited thereto. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing device may be a sensing device for sensing capacitance, light, heat, or ultrasound, but is not limited thereto. The electronic device may, for example, include liquid crystal, quantum dot (QD), fluorescence, phosphorescence, other suitable materials, or combinations thereof. According to some embodiments, the electronic device may include electronic components, which may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, or combinations thereof, but are not limited thereto. The diode may, for example, include an organic light-emitting diode (OLED), a micro-LED (mini-LED), or a quantum dot light-emitting diode (QLED, QDLED), but is not limited thereto. According to some embodiments, the electronic device may include a panel and / or a backlight module, the panel including, for example, a liquid crystal panel, but not limited thereto. It should be understood that the electronic device of this disclosure will be described below using a display device as an example, but this disclosure is not limited thereto.

[0058] Please refer to Figure 1 , Figure 1The figures show a cross-sectional view of electronic device 10A according to some embodiments of the present disclosure. It should be understood that, for clarity, some components of electronic device 10A are omitted from the figures, and only some components are schematically shown. According to some embodiments, additional features may be added to electronic device 10A as described below. According to other embodiments, some features of electronic device 10A as described below may be replaced or omitted.

[0059] According to some embodiments, the electronic device 10A may include a display panel, which may include a substrate 100, a first passivation layer 202, an organic layer 302, a second passivation layer 204, a bonding pad 402, and an electronic component 500.

[0060] The substrate 100 can serve as a driving substrate, and a driving circuit (not shown) can be disposed on the substrate 100. The driving circuit may include an active driving circuit and / or a passive driving circuit. According to some embodiments, the driving circuit may include thin-film transistors (TFTs) (e.g., switching transistors, driving transistors, reset transistors, or other thin-film transistors), data lines, scan lines, conductive pads, dielectric layers, or other lines, but is not limited thereto. According to some embodiments, the display panel may include a thin-film transistor layer 100T (e.g., see reference...). Figure 5 The thin-film transistor layer 100T can be disposed on the substrate 100. For example... Figure 1 As shown, according to some embodiments, the display panel may include a first insulating layer 102 and a second insulating layer 104, which may be part of the thin-film transistor layer 100T. The structure of the thin-film transistor layer 100T will be described in detail below.

[0061] Substrate 100 may comprise a rigid substrate or a flexible substrate. According to some embodiments, the material of substrate 100 may include glass, semiconductor materials, quartz, sapphire, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the semiconductor material may include silicon (Si), germanium (Ge), other suitable semiconductor materials, or combinations thereof, but is not limited thereto. According to some embodiments, substrate 100 may comprise a flexible printed circuit board (FPC).

[0062] A first passivation layer 202 may be disposed on the substrate 100 and the thin-film transistor layer 100T. The first passivation layer 202 may have a first portion 202P-1 and a second portion 202P-2. The first portion 202P-1 may be an opening or a recess, and the second portion 202P-2 is adjacent to the first portion 202P-1 and may surround the first portion 202P-1. Figure 1 In the embodiment shown, the first portion 202P-1 is an opening, that is, the first passivation layer 202 has an opening or a hollow portion.

[0063] In addition, such as Figure 1 As shown, according to some embodiments, the distance D1 between the edge E1 of the bonding pad 402 and the edge E2 of the first passivation layer 202 can be greater than or equal to 5 micrometers and less than or equal to 100 micrometers (i.e., 5 μm ≤ distance D1 ≤ 100 μm), or greater than or equal to 10 micrometers and less than or equal to 20 micrometers (i.e., 10 μm ≤ distance D1 ≤ 20 μm).

[0064] According to the embodiments of this disclosure, distance D1 refers to the minimum distance between the edge E1 of the bonding pad 402 and the edge E2 of the first passivation layer 202 in a direction perpendicular to the normal direction of the substrate 100 (e.g., the X direction in the figures). The edge E1 of the bonding pad 402 may be the bottom edge of the bonding pad 402, and the edge E2 of the first passivation layer 202 may be the bottom edge of the second portion 202P-2 closest to the bonding pad 402.

[0065] Furthermore, according to some embodiments, the thickness of the first portion 202P-1 is less than the thickness of the second portion 202P-2. Specifically, in this embodiment, the first portion 202P-1 is an opening, and the thickness of the first portion 202P-1 is 0, while the thickness of the second portion 202P-2 of the first passivation layer 202 can be greater than or equal to 0.01 μm and less than or equal to 5 μm (i.e., 0.01 μm ≤ the thickness of the second portion 202P-2 ≤ 5 μm), or greater than or equal to 0.1 μm and less than or equal to 0.3 μm (i.e., 0.1 μm ≤ the thickness of the second portion 202P-2 ≤ 0.3 μm).

[0066] According to an embodiment of this disclosure, the thickness of the second portion 202P-2 of the first passivation layer 202 refers to the maximum thickness of the second portion 202P-2 of the first passivation layer 202 that can be measured in a cross-sectional image in the normal direction of the substrate 100 (e.g., the Z direction in the figures).

[0067] According to some embodiments, the material of the first passivation layer 202 may include, but is not limited to, inorganic materials. For example, the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, other suitable materials, or combinations thereof, but is not limited to.

[0068] It should be understood that, according to embodiments of this disclosure, the thickness, width, or height of each component, or the spacing or distance between components, can be measured using an optical microscope (OM), a scanning electron microscope (SEM), an alpha-step thickness gauge, an ellipsometry, or other suitable methods. More specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional image containing the components to be measured, and the thickness, width, or height of each component, or the spacing or distance between components, can be measured.

[0069] Furthermore, the organic layer 302 may be disposed on the first passivation layer 202, and the organic layer 302 may have an opening 302p. According to some embodiments, the area of ​​the opening 302p may be larger than the area of ​​the first portion 202P-1 of the first passivation layer 202, and the first portion 202P-1 may be located within the opening 302p. According to some embodiments, in the normal direction of the substrate 100 (e.g., the Z direction in the figures), the first portion 202P-1 of the first passivation layer 202 overlaps with the area of ​​the opening 302p of the organic layer 302. Figure 1 As shown, the first passivation layer 202 may protrude from the organic layer 302 and extend toward the bonding pad 402.

[0070] According to some embodiments, the organic layer 302 may be a photoresist material, for example, it may include epoxy resins, acrylic resins (such as polymethyl methacrylate (PMMA), benzocyclobutene (BCB), polyimide, perfluoroalkoxy alkane (PFA), other suitable materials, or combinations thereof, but is not limited thereto.

[0071] Furthermore, the second passivation layer 204 may be disposed on the organic layer 302 and at least partially cover the first passivation layer 202. Specifically, the second passivation layer 204 may be conformally formed on the surfaces of the organic layer 302 and the first passivation layer 202, and may be in contact with both the organic layer 302 and the first passivation layer 202. Figure 1 As shown, according to some embodiments, the second passivation layer 204 also has an opening (not shown) in the normal direction of the substrate 100 (e.g., the Z direction in the figures), and the opening of the second passivation layer 204 substantially overlaps with the first portion 202P-1 of the first passivation layer 202. Furthermore, the area of ​​the opening 302p of the organic layer 302 is also larger than the area of ​​the opening of the second passivation layer 204.

[0072] According to some embodiments, the material of the second passivation layer 204 may be the same as or similar to the material of the first passivation layer 202 described above, and will not be repeated here.

[0073] It is worth noting that since the first passivation layer 202, the organic layer 302, and the second passivation layer 204 are formed sequentially, the organic layer 302 remaining between the first passivation layer 202 and the second passivation layer 204 after the patterning process can easily cause interface peeling between the first passivation layer 202 and the second passivation layer 204. With the structure described in this embodiment, the interface between the first passivation layer 202 and the second passivation layer 204 is located outside the area of ​​the bonding pad 402, that is, it does not overlap with the bonding position of the bonding pad 402. Therefore, the risk of cracks in the substrate 100 or the electronic component 500 peeling off from the substrate 100 can be reduced, thereby improving the reliability of the electronic device.

[0074] Furthermore, the electronic device 10A may include a third passivation layer 206, which may serve as a pixel definition layer (PDL). The third passivation layer 206 may be disposed on the second passivation layer 204 and at least partially cover the bonding pad 402. Specifically, the third passivation layer 206 may compliantly cover the second passivation layer 204, the first passivation layer 202, the second insulating layer 104, and the bonding pad 402. Figure 1 As shown, in this embodiment, in the first part 202P-1, a portion of the third passivation layer 206 is in direct contact with the second insulating layer 104.

[0075] According to some embodiments, the material of the third passivation layer 206 may be the same as or similar to the material of the first passivation layer 202 or the second passivation layer 204, which will not be repeated here.

[0076] Please refer to Figure 1 The bonding pad 402 can be disposed on the substrate 100 and the thin-film transistor layer 100T. The bonding pad 402 can be disposed corresponding to the overlapping area of ​​the first portion 202P-1 of the first passivation layer 202 and the opening 302p of the organic layer 302. In other words, the bonding pad 402 can be disposed in the overlapping area of ​​the first portion 202P-1 of the first passivation layer 202 and the opening 302p of the organic layer 302. Figure 1 As shown, according to some embodiments, the bonding pad 402 can be in direct contact with the thin-film transistor layer 100T.

[0077] Furthermore, the electronic component 500 can be bonded to the bonding pad 402. Specifically, the bonding pad 402 overlaps with the electronic component 500 in the normal direction of the substrate 100 (e.g., the Z direction in the figures). The bonding pad 402 can be electrically connected to the driving circuit (e.g., the thin-film transistor layer 100T) on the substrate 100, and the bonding pad 402 can be electrically connected to the electronic component 500 via the solder pad 404 and the soldering material 406, so that the signals of the driving circuit can be transmitted to the electronic component 500.

[0078] According to some embodiments, the material of the bonding pad 402 includes a conductive material, such as a metallic material, but is not limited thereto. For example, the metallic material may include copper (Cu), aluminum (Al), indium (In), ruthenium (Ru), tin (Sn), gold (Au), platinum (Pt), zinc (Zn), silver (Ag), titanium (Ti), lead (Pb), nickel (Ni), chromium (Cr), magnesium (Mg), palladium (Pd), copper alloys, aluminum alloys, indium alloys, ruthenium alloys, tin alloys, gold alloys, platinum alloys, zinc alloys, silver alloys, titanium alloys, lead alloys, nickel alloys, chromium alloys, magnesium alloys, palladium alloys, other suitable conductive materials, or combinations thereof, but is not limited thereto.

[0079] According to some embodiments, electronic component 500 may include a light-emitting component, a chip-on-film (COF) structure, or other components that need to be bonded to a substrate. According to some embodiments, electronic component 500 (taking a light-emitting component as an example) may include a leadframe 502 and a conductive structure 504. The light-emitting unit (not shown) of the light-emitting component may be disposed in the leadframe 502, and the leadframe 502 may be electrically connected to the conductive structure 504. Furthermore, the conductive structure 504 may be electrically connected to the bonding pad 402 via solder pads 404 and soldering material 406. Solder pads 404 and soldering material 406 may be disposed between electronic component 500 and bonding pad 402, and soldering material 406 may be used to bond electronic component 500 and bonding pad 402. Specifically, soldering material 406 may be used to bond conductive structure 504 and solder pad 404.

[0080] According to some embodiments, the light-emitting unit may include a light-emitting diode or a light-emitting package. The light-emitting diode may include, for example, an organic light-emitting diode, an inorganic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode or a quantum dot light-emitting diode (e.g., a QLED or a QDLED), other suitable light-emitting units or combinations thereof, but is not limited thereto.

[0081] In detail, according to some embodiments, the light-emitting unit may include, for example, a first semiconductor layer (not shown), a second semiconductor layer (not shown), and a quantum well layer (not shown) disposed between the first semiconductor layer and the second semiconductor layer, but this disclosure is not limited thereto. Furthermore, the first and second semiconductor layers may be formed of III-V compound dopants having p-type and n-type conductivity types (e.g., gallium nitride having p-type and n-type conductivity types). In addition, the quantum well layer may comprise a single quantum well (SQW) or a multiple quantum well (MQW). According to some embodiments, the III-V compound may comprise gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum gallium indium nitride (AlGaInN), other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the quantum well layer may comprise indium gallium nitride, gallium nitride, other suitable materials, or combinations thereof, but is not limited thereto.

[0082] According to some embodiments, the conductive structure 504 may be, for example, the anode electrode and the cathode electrode of the light-emitting unit. According to some embodiments, the conductive structure 504 may comprise a metallic material, such as copper, aluminum, indium, ruthenium, tin, gold, platinum, zinc, silver, titanium, lead, nickel, chromium, magnesium, palladium, copper alloys, aluminum alloys, indium alloys, ruthenium alloys, tin alloys, gold alloys, platinum alloys, zinc alloys, silver alloys, titanium alloys, lead alloys, nickel alloys, chromium alloys, magnesium alloys, palladium alloys, other suitable metallic materials, or combinations thereof, but is not limited thereto.

[0083] According to some embodiments, the material of solder pad 404 may include nickel (Ni), copper (Cu), nickel alloys, copper alloys, other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, solder material 406 may include tin (Sn), aluminum (Al), tin alloys, aluminum alloys, other suitable solder materials, or combinations thereof, but is not limited thereto. According to other embodiments, solder material 406 may include anisotropic conductive film (ACF), but is not limited thereto.

[0084] Next, please refer to Figure 2 , Figure 2 This diagram shows a cross-sectional view of the electronic device 10B according to other embodiments of this disclosure. It should be understood that components or components that are the same or similar to those described above will be indicated by the same or similar reference numerals in the following text, and their materials and functions will be the same or similar to those described above; therefore, this part will not be repeated hereafter.

[0085] Figure 2The electronic device 10B shown is generally similar to the aforementioned electronic device 10A. The differences between them include that, in electronic device 10B, a first portion 202P-1 of the first passivation layer 202 is a recess, a portion of the first portion 202P-1 is disposed between the second insulating layer 104 and the bonding pad 402, and a portion of the first portion 202P-1 is disposed between the second insulating layer 104 and the third passivation layer 206. In this embodiment, the bonding pad 402 is in direct contact with the first passivation layer 202; more specifically, the bottom surface of the bonding pad 402 is in direct contact with the first passivation layer 202.

[0086] Furthermore, in this embodiment, the first portion 202P-1 includes a contact area CP and a non-contact area NP. The contact area CP contacts the bonding pad 402, while the non-contact area NP is connected to the contact area CP and surrounds the contact area CP. In this embodiment, the contact area CP is disposed between the second insulating layer 104 and the bonding pad 402, and the non-contact area NP is disposed between the second insulating layer 104 and the third passivation layer 206. As mentioned above, the distance D1 between the edge E1 of the bonding pad 402 and the edge E2 of the first passivation layer 202 can be greater than or equal to 5 micrometers and less than or equal to 100 micrometers (i.e., 5 μm ≤ distance D1 ≤ 100 μm), or greater than or equal to 10 micrometers and less than or equal to 20 micrometers (i.e., 10 μm ≤ distance D1 ≤ 20 μm). In this embodiment, the edge E2 of the first passivation layer 202 can also be regarded as the outer edge of the non-contact area NP. Therefore, the distance D1 between the edge E1 of the bonding pad 402 and the outer edge of the non-contact area NP can be greater than or equal to 5 micrometers and less than or equal to 100 micrometers (that is, 5 μm ≤ distance D1 ≤ 100 μm), or greater than or equal to 10 micrometers and less than or equal to 20 micrometers (that is, 10 μm ≤ distance D1 ≤ 20 μm).

[0087] Furthermore, the thickness of the first portion 202P-1 is less than the thickness of the second portion 202P-2. In this embodiment, the thickness difference D2 between the thickness of the first portion 202P-1 and the thickness of the second portion 202P-2 can be greater than or equal to 0.01 μm and less than or equal to 5 μm (i.e., 0.01 μm ≤ thickness difference D2 ≤ 5 μm). Specifically, in this embodiment, the first portion 202P-1 is a recess, and the thickness of the first portion 202P-1 can be greater than or equal to 0.01 μm and less than or equal to 4.99 μm (i.e., 0.01 μm ≤ thickness of the first portion 202P-1 ≤ 4.99 μm), while the thickness of the second portion 202P-2 of the first passivation layer 202 can be greater than or equal to 0.01 μm and less than or equal to 10 μm (i.e., 0.01 μm ≤ thickness of the second portion 202P-2 ≤ 10 μm).

[0088] According to an embodiment of this disclosure, the thickness of the first portion 202P-1 of the first passivation layer 202 refers to the maximum thickness of the first portion 202P-1 of the first passivation layer 202 that can be measured in a cross-sectional image in the normal direction of the substrate 100 (e.g., the Z direction in the figures).

[0089] Next, please refer to Figure 3 , Figure 3 This diagram shows a cross-sectional view of the electronic device 10C according to other embodiments of the present disclosure. Figure 3 The electronic device 10C shown is generally similar to the aforementioned electronic device 10A. The difference lies in that, in electronic device 10C, the second passivation layer 204 extends further onto the second insulating layer 104, in addition to being disposed on the organic layer 302 and the first passivation layer 202. Specifically, a portion of the second passivation layer 204 is disposed between the second insulating layer 104 and the third passivation layer 206, and another portion of the second passivation layer 204 is disposed between the second insulating layer 104 and the bonding pad 402. In this embodiment, the first portion 202P-1 of the first passivation layer 202 is open, and the bonding pad 402 is in direct contact with the second passivation layer 204.

[0090] Next, please refer to Figure 4 , Figure 4 This diagram shows a cross-sectional view of the electronic device 10D according to other embodiments of the present disclosure. Figure 4 The illustrated electronic device 10D is generally similar to the aforementioned electronic device 10B. The difference lies in that, in electronic device 10D, the second passivation layer 204, in addition to being disposed on the organic layer 302 and the second portion 202P-2 of the first passivation layer 202, further extends onto the first portion 202P-1 of the second insulating layer 104. Specifically, a portion of the second passivation layer 204 is disposed between the first passivation layer 202 and the third passivation layer 206, and another portion is disposed between the first passivation layer 202 and the bonding pad 402. In this embodiment, the first portion 202P-1 of the first passivation layer 202 is a recess, and the bonding pad 402 is in direct contact with the second passivation layer 204.

[0091] Next, please refer to Figures 5 to 11B , Figures 5 to 11B The figures show cross-sectional structural schematics of an electronic device at an intermediate stage of manufacturing according to some embodiments of the present disclosure. The figures also show cross-sectional structural schematics of the electronic device in circuit region A1 and junction region A2, with junction region A2 substantially corresponding to the aforementioned... Figures 1 to 4The area shown. It should be understood that, according to some embodiments, additional operational steps may be provided before, during, and / or after the manufacturing method of the electronic device. According to some embodiments, some of the operational steps may be replaced or omitted, and the order of some of the operational steps is interchangeable.

[0092] According to some embodiments, a method of manufacturing an electronic device may include providing a display panel, please refer to... Figure 5 First, a substrate 100 can be provided, on which a thin-film transistor layer 100T is formed. According to some embodiments, the thin-film transistor layer 100T may include a buffer layer 106, a first insulating layer 102, a second insulating layer 104, a conductive layer 400a, a conductive layer 400b, a conductive layer 400c, and a semiconductor layer 100s. Specifically, the conductive layer 400a can be formed on the substrate 100 first, followed by the sequential formation of the buffer layer 106, the semiconductor layer 100s, and the first insulating layer 102 on the substrate 100. Next, a portion of the buffer layer 106 and the first insulating layer 102 can be removed by a patterning process to form a via, followed by the formation of the conductive layer 400b in the via and on the first insulating layer 102, and then the formation of the second insulating layer 104 over the first insulating layer 102 and the conductive layer 400b. Next, a portion of the first insulating layer 102 and the second insulating layer 104 can be removed by a patterning process to form a via, and then a conductive layer 400c is formed in the via and on the second insulating layer 104.

[0093] The aforementioned first insulating layer 102, second insulating layer 104, conductive layer 400a, conductive layer 400b, conductive layer 400c, and semiconductor layer 100s can serve as driving circuits for electronic devices. These driving circuits may include thin-film transistors (e.g., switching transistors, driving transistors, reset transistors, or other thin-film transistors), data lines, scan lines, conductive pads, dielectric layers, or other lines, but are not limited thereto. It should be understood that the configuration of the driving circuit and the number of thin-film transistors are not limited to those shown in the figures. Depending on the embodiment, the thin-film transistor layer 100T may have other suitable driving circuit configurations or other suitable numbers or types of thin-film transistors.

[0094] Furthermore, the thin-film transistor can be a top-gate thin-film transistor, a bottom-gate thin-film transistor, or a dual-gate or double-gate thin-film transistor. The thin-film transistor includes at least one semiconductor layer 100s, which includes, but is not limited to, amorphous silicon, low-temp polysilicon (LTPS), metal oxides, other suitable materials, or combinations thereof, but is not limited thereto. The metal oxide may include indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc tin oxide (IGZTO), other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, different thin-film transistors may have the aforementioned different semiconductor materials.

[0095] According to some embodiments, the buffer layer 106, the first insulating layer 102, the second insulating layer 104, and the semiconductor layer 100s can be formed by coating processes, chemical vapor deposition processes, physical vapor deposition processes, coating processes, evaporation processes, sputtering processes, other suitable processes, or combinations thereof. Chemical vapor deposition processes may include, for example, low-pressure chemical vapor deposition (LPCVD), low-temperature chemical vapor deposition (LTCVD), rapid-rise chemical vapor deposition (RTCVD), plasma-assisted chemical vapor deposition (PECVD), or atomic layer deposition (ALD), but are not limited thereto. Physical vapor deposition processes may include, for example, sputtering processes, evaporation processes, pulsed laser deposition, etc., but are not limited thereto.

[0096] According to some embodiments, conductive layers 400a, 400b, and 400c can be formed by chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, other suitable processes, or combinations thereof.

[0097] Furthermore, vias can be formed using one or more photolithography and / or etching processes. According to some embodiments, the photolithography process may include, but is not limited to, photoresist coating (e.g., spin coating), soft baking, hard baking, shielding alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may include, but is not limited to, dry etching or wet etching processes.

[0098] Please continue to refer to Figure 5Next, a first passivation layer 202 can be formed on the substrate 100 and the aforementioned thin film transistor layer 100T. The first passivation layer 202 can cover the second insulating layer 104 and the conductive layer 400c.

[0099] According to some embodiments, the first passivation layer 202 can be formed by coating process, chemical vapor deposition process, physical vapor deposition process, printing process, vapor deposition process, sputtering process, other suitable process, or combination thereof.

[0100] Next, please refer to Figure 6 An organic layer 302 can be formed on the substrate 100 and the first passivation layer 202. According to some embodiments, before forming the organic layer 302, a portion of the first passivation layer 202 can be removed by one or more photolithography processes and / or etching processes to form a via V1, which can expose a portion of the conductive layer 400c.

[0101] Next, please refer to Figure 7 The organic layer 302 can be patterned to expose region 302R, which can be a recess in the organic layer 302. Specifically, the organic layer 302 can be patterned using one or more photolithography and / or etching processes, removing a portion of the organic layer 302 to form a recess within it. For example... Figure 7 As shown, the patterned organic layer 302 is still disposed on the top surface of the first passivation layer 202. However, according to some other embodiments, region 302R may be the top surface of the first passivation layer 202, that is, a portion of the organic layer 302 may be removed by the patterning process to expose the top surface of the first passivation layer 202.

[0102] According to some embodiments, when the organic layer 302 is patterned in the bonding region A2 to expose the region 302R, a portion of the organic layer 302 can also be removed by one or more photolithography processes and / or etching processes to form a via V2 in the circuit region A1. The via V2 can expose a portion of the conductive layer 400c again.

[0103] Next, please refer to Figure 8 A second passivation layer 204 can be formed on the substrate 100 and the organic layer 302. The second passivation layer 204 is compliantly formed on the organic layer 302 and covers the region 302R. In addition, in the circuit region A1, the second passivation layer 204 also fills the via V2.

[0104] According to some embodiments, the method for forming the second passivation layer 204 may be the same as or similar to the process for forming the aforementioned first passivation layer 202, and will not be repeated here.

[0105] Next, please refer to Figure 9AAccording to some embodiments, after the second passivation layer 204 is formed on the substrate 100, the second passivation layer 204 and the first passivation layer 202 can be patterned to expose a region 202R, which may be the top surface 104t of the second insulating layer 104 of the thin-film transistor layer 100T. Specifically, the second passivation layer 204 and the first passivation layer 202 can be patterned by one or more photolithography and / or etching processes, removing a portion of the second passivation layer 204 and the first passivation layer 202 (and the organic layer 302) to expose the top surface 104t of the second insulating layer 104.

[0106] According to some embodiments, when the step of patterning the second passivation layer 204 and the first passivation layer 202 in the bonding region A2 to expose the region 202R is performed, a portion of the second passivation layer 204 can also be removed by one or more photolithography processes and / or etching processes to form a via V3 in the circuit region A1. The via V3 can expose a portion of the conductive layer 400c again.

[0107] However, according to some other embodiments, please refer to Figure 9B After forming the second passivation layer 204 on the substrate 100, the second passivation layer 204 and the first passivation layer 202 are patterned to expose region 202R, which may be a recess in the first passivation layer 202. Specifically, the second passivation layer 204 and the first passivation layer 202 can be patterned by one or more photolithography and / or etching processes, removing a portion of the second passivation layer 204 and the first passivation layer 202 (and the organic layer 302), and forming a recess in the first passivation layer 202. Figure 9B As shown, in this embodiment, the patterned first passivation layer 202 is still disposed on the top surface 104t of the second insulating layer 104, and the patterning process does not expose the top surface 104t of the second insulating layer 104. Furthermore, according to some embodiments, the steps of patterning the first passivation layer 202 and patterning the second passivation layer 204 can be performed simultaneously.

[0108] Similarly, in this embodiment, when the step of patterning the second passivation layer 204 and the first passivation layer 202 in the bonding region A2 to expose the region 202R is performed, a portion of the second passivation layer 204 can also be removed by one or more photolithography processes and / or etching processes to form a via V3 in the circuit region A1. The via V3 can expose a portion of the conductive layer 400c again.

[0109] It is worth noting that, through such Figure 9A as well as Figure 9B The steps shown reduce the likelihood of organic layer 302 (e.g., photoresist material) remaining at the location where bonding pad 402 will subsequently form, which can then be directly formed on the second insulating layer 104 (e.g., ...). Figure 10A or Figure 1 (as shown) or directly formed on the first passivation layer 202 (e.g.) Figure 10B or Figure 2 (As shown). Therefore, the risk of cracks forming on the substrate 100 at the corresponding bonding pads 402 or the electronic components 500 peeling off the substrate 100 can be reduced, thereby improving the process yield of electronic devices.

[0110] Next, please refer to Figure 10A as well as Figure 10B , Figure 10A as well as Figure 10B Separately continue Figure 9A as well as Figure 9B The steps are shown. (As indicated) Figure 10A as well as Figure 10B As shown, bonding pads 402 can be formed on the substrate 100. More specifically, as... Figure 10A As shown, according to some embodiments, a bonding pad 402 may be formed on the second insulating layer 104, and the bonding pad 402 is in direct contact with the second insulating layer 104. For example... Figure 10B As shown, according to some embodiments, a bonding pad 402 may be formed on the recess of the first passivation layer 202, and the bonding pad 402 is in direct contact with the first passivation layer 202.

[0111] In detail, for Figure 10A First, a conductive material can be formed to cover the second passivation layer 204, the first passivation layer 202, and the second insulating layer 104. Then, the conductive material can be patterned using one or more photolithography and / or etching processes to form the bonding pad 402. For... Figure 10B First, a conductive material can be formed to cover the second passivation layer 204 and the first passivation layer 202. Then, the conductive material can be patterned by one or more photolithography processes and / or etching processes to form the bonding pad 402.

[0112] It is worth noting that the formed bonding pad 402 can be disposed corresponding to the overlapping area of ​​the aforementioned region 302R and region 202R. In other words, in the normal direction of the substrate 100 (e.g., the Z direction in the figure), the bonding pad 402 is disposed in the overlapping area of ​​region 302R and region 202R, and the area of ​​the bonding pad 402 is smaller than the area of ​​region 202R. Furthermore, as with... Figure 1 as well as Figure 2 As described above, the distance D1 between the edge E1 (not shown) of the bonding pad 402 and the edge E2 (not shown) of the first passivation layer 202 can be greater than or equal to 5 micrometers and less than or equal to 100 micrometers (i.e., 5 μm ≤ distance D1 ≤ 100 μm).

[0113] Furthermore, such as Figure 10BAs shown, the thickness difference D2 between the thickness of the first portion 202P-1 (not shown) and the thickness of the second portion 202P-2 (not shown) of the first passivation layer 202 can be greater than or equal to 0.01 μm and less than or equal to 5 μm (i.e., 0.01 μm ≤ thickness difference D2 ≤ 5 μm). In other words, the depth to which the first passivation layer 202 is etched away can be greater than or equal to 0.01 μm and less than or equal to 5 μm.

[0114] In addition, during the step of forming bonding pad 402 in bonding region A2, via 402v can also be formed in circuit region A1. Via 402v can be electrically connected to the conductive layer 400c of thin film transistor layer 100T.

[0115] According to some embodiments, the bonding pad 402 and the via 402v can be formed by chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, other suitable processes, or combinations thereof. Furthermore, the bonding pad 402 and the via 402v can be formed by one or more photolithography and / or etching processes.

[0116] Next, please refer to Figure 11A as well as Figure 11B , Figure 11A as well as Figure 11B Separately continue Figure 10A as well as Figure 10B The steps are shown. (As indicated) Figure 11A as well as Figure 11B As shown, after forming the bonding pad 402, a third passivation layer 206 can be formed on the second passivation layer 204 and the bonding pad 402. Furthermore, a portion of the third passivation layer 206 can be removed to expose a portion of the bonding pad 402, for example, exposing a portion of the top surface of the bonding pad 402. Then, a solder pad 404 is formed on the bonding pad 402, covering the exposed bonding pad 402 and electrically connected to it. According to some embodiments, the solder pad 404 may partially cover the third passivation layer 206.

[0117] According to some embodiments, the method for forming the third passivation layer 206 may be the same as or similar to the process for forming the aforementioned first passivation layer 202 or second passivation layer 204, and will not be repeated here. According to some embodiments, the solder pad 404 may be formed by chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, other suitable processes, or combinations thereof.

[0118] Next, the electronic component 500 can be bonded to the contact pad 402. Specifically, according to some embodiments, such as... Figure 1 or Figure 2 As shown, the electronic component 500 can then be bonded to the solder pad 404 on the bonding pad 402 using solder material 406. Furthermore, by using… Figures 5 to 8 , Figure 9A , Figure 10A as well as Figure 11A The electronic device formed by the steps shown will have a similar Figure 1 The structure shown. By Figures 5 to 8 , Figure 9B , Figure 10B as well as Figure 11B The electronic device formed by the steps shown will have a similar function to Figure 2 The structure shown.

[0119] Please refer to Figure 12A as well as Figure 12B , Figure 12A as well as Figure 12B This diagram shows a cross-sectional view of an electronic device at an intermediate stage of manufacturing, according to some other embodiments of the present disclosure. Specifically, Figure 12A as well as Figure 12B Can be continued Figure 7 The steps are shown. According to... Figure 12A as well as Figure 12B In the illustrated embodiment, the step of forming the second passivation layer 204 on the substrate 100 is performed after the step of patterning the first passivation layer 202. In contrast, according to... Figure 9A as well as Figure 9B In the embodiment shown, the step of forming the second passivation layer 204 on the substrate 100 is performed before the step of patterning the first passivation layer 202.

[0120] In detail, such as Figure 12A As shown, according to some embodiments, after patterning the organic layer 302 to expose region 302R, the first passivation layer 202 can then be patterned to expose region 202R, where region 202R may be the top surface 104t of the second insulating layer 104 of the thin-film transistor layer 100T. Specifically, the first passivation layer 202 can be patterned by one or more photolithography and / or etching processes, removing a portion of the first passivation layer 202 to expose the top surface 104t of the second insulating layer 104.

[0121] According to some embodiments, when the first passivation layer 202 is patterned in the bonding region A2 to expose the region 202R, a portion of the first passivation layer 202 can also be removed by one or more photolithography processes and / or etching processes to form a via V2 in the circuit region A1. The via V2 can expose a portion of the conductive layer 400c.

[0122] On the other hand, such as Figure 12BAs shown, according to other embodiments, after patterning the organic layer 302 to expose region 302R, the first passivation layer 202 can then be patterned to expose region 202R, where region 202R may be a recess in the first passivation layer 202. Specifically, the first passivation layer 202 can be patterned by one or more photolithography and / or etching processes, removing a portion of the first passivation layer 202 and forming a recess in the first passivation layer 202. For example... Figure 12B As shown, in this embodiment, the patterned first passivation layer 202 is still disposed on the top surface 104t of the second insulating layer 104, and the patterning process does not expose the top surface 104t of the second insulating layer 104.

[0123] Similarly, in this embodiment, when the first passivation layer 202 is patterned in the bonding region A2 to expose the region 202R, a portion of the first passivation layer 202 can also be removed by one or more photolithography processes and / or etching processes to form a via V2 in the circuit region A1. The via V2 can expose a portion of the conductive layer 400c.

[0124] At Figure 12A as well as Figure 12B Following the steps shown, a second passivation layer 204 can then be formed on the organic layer 302, the first passivation layer 202, and the second insulating layer 104 (for FIG. 12). The second passivation layer 204 can also fill the via V2. Afterwards, the second passivation layer 204 located in the via V2 can be removed, and a conductive material is formed on the second passivation layer 204 and in the via V2. The conductive material can then be patterned using one or more photolithography and / or etching processes to form the bonding pad 402 and the via 402v. Then, refer to... Figure 10A , Figure 10B , Figure 11A as well as Figure 11B The steps are carried out accordingly. Furthermore, through... Figure 12A as well as Figure 12B The electronic devices formed by the steps shown will each have similar characteristics to... Figure 3 as well as Figure 4 The structure shown.

[0125] In summary, according to the embodiments of this disclosure, a method for manufacturing an electronic device is provided, which can improve the structural strength of the bonding pad and electronic component joint in the formed electronic device. For example, it can reduce the risk of substrate cracking or electronic component peeling off from the substrate, thereby improving the overall reliability of the electronic device.

[0126] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Features between embodiments of this disclosure can be freely combined and used as long as they do not violate the spirit of the invention or conflict with it. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand from the disclosure of this disclosure that current or future developed processes, machines, manufacturing, material composition, apparatus, methods, and steps can be used according to this disclosure as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. The scope of protection of this disclosure shall be determined by the scope of the appended claims. No embodiment or claim of this disclosure needs to achieve all the purposes, advantages, and features disclosed in this disclosure.

Claims

1. A method for manufacturing an electronic device, characterized in that, include: Provide a substrate; A thin-film transistor layer is formed on the substrate; A first passivation layer is formed on the substrate; An organic layer is formed on the substrate; The organic layer is patterned to expose a first region; A second passivation layer is formed on the substrate; The first passivation layer is patterned to expose a second region; The second passivation layer is patterned to expose the second region; A bonding pad is formed on the substrate and corresponds to the overlapping area of ​​the first region and the second region; as well as An electronic component is bonded to the bonding pad. The first passivation layer and the second passivation layer have a contact surface, and the contact surface does not overlap with the bonding position of the bonding pad.

2. The method for manufacturing an electronic device as claimed in claim 1, characterized in that, The steps of patterning the first passivation layer and patterning the second passivation layer are performed simultaneously.

3. The method for manufacturing an electronic device as claimed in claim 1, characterized in that, The step of forming the second passivation layer on the substrate is performed before the step of patterning the first passivation layer.

4. The method for manufacturing an electronic device as claimed in claim 1, characterized in that, The step of forming the second passivation layer on the substrate is performed after the step of patterning the first passivation layer.

5. The method for manufacturing an electronic device as claimed in claim 1, characterized in that, The step of forming the first passivation layer on the substrate is performed after the step of patterning the organic layer.

6. An electronic device, characterized in that, include: One substrate; A thin-film transistor layer is disposed on the substrate; A first passivation layer is disposed on the thin film transistor layer, and the first passivation layer has a first portion and a second portion, the first portion being an opening or a recess, and the second portion being adjacent to the first portion; An organic layer is disposed on the first passivation layer, and the organic layer has an opening; A second passivation layer is disposed on the organic layer; A bonding pad is disposed on the thin-film transistor layer and corresponds to the overlapping area of ​​the first portion of the first passivation layer and the opening of the organic layer; as well as An electronic component is bonded to the bonding pad. The first portion is the opening, and the bonding pad is in direct contact with the thin-film transistor layer. The first passivation layer and the second passivation layer have a contact surface, and the contact surface does not overlap with the bonding position of the bonding pad.

7. The electronic device as claimed in claim 6, characterized in that, The thickness of the first part is less than the thickness of the second part.

8. The electronic device as claimed in claim 6, characterized in that, The difference between the thickness of the first part and the thickness of the second part is greater than or equal to 0.01 micrometers and less than or equal to 5 micrometers.

9. The electronic device as claimed in claim 6, characterized in that, The first part includes a contact area and a non-contact area. The contact area contacts the bonding pad, and the non-contact area surrounds the contact area. The distance between an edge of the bonding pad and an outer edge of the non-contact area is greater than or equal to 5 micrometers and less than or equal to 100 micrometers.

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