GaN field effect transistor with high power figure of merit and excellent on-state characteristics

Abstract

The application relates to a field effect transistor, in particular a GaN field effect transistor with high power figure of merit and excellent conduction characteristics. According to the technical scheme provided by the application, the GaN field effect transistor with high power figure of merit and excellent conduction characteristics comprises a GaN field effect transistor body, the GaN field effect transistor body comprises a C-doped buffer layer and a device structure arranged on the C-doped buffer layer; a P-type buried layer for depleting background carriers and channel carriers is arranged in the C-doped buffer layer, and an N-type buried layer for supplementing the channel carriers depleted by the P-type buried layer is arranged in the C-doped buffer layer; in the C-doped buffer layer, the N-type buried layer is located between the P-type buried layer and a device channel layer structure. When the transistor withstand voltage and the Baliga power figure of merit are improved, the conduction characteristics of the transistor can be improved simultaneously.

Description

Technical Field

[0001] This invention relates to a field-effect transistor, and more particularly to a GaN field-effect transistor with high power figure of merit and excellent conduction characteristics. Background Technology

[0002] With the accelerated development of my country's modernization, power semiconductor devices based on silicon (Si) and compound semiconductor materials are widely used in new energy vehicles, marine electrification and marine power, consumer electronics, and high-power propulsion. Meanwhile, high efficiency, high power density, high reliability, high speed, and lightweight design have become the main development trends in power management.

[0003] Gallium nitride (GaN), as a third-generation semiconductor material, is currently in a phase of rapid development and has become one of the preferred materials for high-temperature, high-frequency, and high-power devices. GaN semiconductor technology is a new generation of semiconductor chip technology with significant strategic and pioneering characteristics.

[0004] Compared with traditional Si-based power electronic devices, GaN power electronic devices can meet the requirements of high frequency, high power density, high temperature and high pressure resistance, radiation resistance, small size and light weight in practical applications. They have shown great potential in power management and conversion, and have been recognized as one of the disruptive components that will transform military electronic systems and architectures.

[0005] P-GaN gate AlGaN / GaN HEMT devices are a type of conventional GaN-enhanced power device. Theoretically, GaN material has excellent breakdown voltage capability. However, due to varying degrees of lattice mismatch between GaN and substrates such as Si, SiC, and sapphire, GaN epitaxy suffers from high-density defects. The total dislocation density of GaN epitaxy on commonly used Si substrates is approximately 10-1. 9 ~10 10 cm -3 .

[0006] Due to the presence of unintentional doping impurities and defects, GaN epitaxy on Si substrates exhibits weak N-type doping, with a background carrier concentration reaching ~10⁻⁶. 12 cm -3 This results in a large leakage current in the buffer layer of GaN power devices based on Si, which easily leads to device performance degradation, and premature breakdown of GaN devices is a common phenomenon. The presence of background charge carriers means that the breakdown voltage of GaN transistors with Si substrates is far from reaching the theoretical value.

[0007] Therefore, it is necessary to optimize the structure of conventional P-GaN gate AlGaN / GaN HEMT power devices to improve the device's breakdown voltage and Baliga power figure of merit (V). 2BR / R ON,sp At the same time, it also takes into account the conduction characteristics of transistors. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a GaN field-effect transistor with high power figure of merit and excellent conduction characteristics, which can improve the transistor's conduction characteristics while increasing the transistor's voltage withstand capability.

[0009] According to the technical solution provided by the present invention, the GaN field-effect transistor that can improve the voltage withstand and conduction characteristics of the transistor includes a GaN field-effect transistor body, the GaN field-effect transistor body includes a C-doped buffer layer and a device structure disposed on the C-doped buffer layer.

[0010] A P-type buried layer that can deplete background carriers and channel carriers is provided in the C-doped buffer layer, and an N-type buried layer is provided in the C-doped buffer layer to replenish the channel carriers depleted by the P-type buried layer.

[0011] Within the C-doped buffer layer, the N-type buried layer is located between the P-type buried layer and the device channel layer structure.

[0012] The N-type buried layer is separated from the P-type buried layer by a C-doped buffer layer, and the N-type buried layer is in contact with the channel layer in the device structure.

[0013] Within the C-doped buffer layer, the P-type buried layer includes a first P-type buried region and a second P-type buried region that corresponds to the first P-type buried region.

[0014] The N-type buried layer includes an N-type first buried area and an N-type second buried area that corresponds to the N-type first buried area;

[0015] The first buried area of ​​type N corresponds exactly to the first buried area of ​​type P, and the second buried area of ​​type N corresponds exactly to the second buried area of ​​type P.

[0016] The first end of the N-type first buried region is located inside the first end of the P-type first buried region, and the first end of the N-type first buried region is flush with the end of the P-GaN gate adjacent to the drain in the device structure. The second end of the N-type first buried region does not exceed the second end of the P-type first buried region, and the two ends of the N-type second buried region are located inside the corresponding two ends of the P-type second buried region.

[0017] The device structure also includes a barrier layer on the channel layer, a passivation layer on the barrier layer, a gate field plate on the P-GaN gate, a source electrode for forming the source electrode, and a source field plate corresponding to the source electrode, wherein,

[0018] The source and drain are all in ohmic contact with the channel layer and barrier layer. The P-GaN gate is located between the source and drain. The source corresponds to the adjacent P-type first buried region and the drain corresponds to the adjacent P-type second buried region.

[0019] The P-GaN gate and gate field plate are located within the passivation layer, and the P-GaN gate is supported on the barrier layer.

[0020] The source field plate is connected to the source body and covers the passivation layer, and the lateral length of the source field plate on the passivation layer is less than the corresponding lateral length of the passivation layer.

[0021] The doping concentration of the N-type buried layer is in the range of 6 × 10⁻⁶. 17 cm -3 ~2×10 18 cm -3 The spacing H between the N-type and P-type buried layers NP =0.05μm≦H NP ≤0.25μm;

[0022] The N-type first buried region and the N-type second buried region are located between the drain electrode and the end of the P-GaN gate adjacent to the drain electrode, wherein...

[0023] The first buried region of the N-type overlaps with the source field plate space on the cover passivation layer, while the second buried region of the N-type overlaps with the source field plate space.

[0024] The first and second buried areas of type N have the same thickness T. N And the thickness T of the N-type buried layer N =0.1μm≦T N ≤0.15μm;

[0025] The transverse length L of the first buried area of ​​type N N1 =0.8μm≦L N1 ≤1.3μm; Lateral length L of the second buried zone of type N N2 =5.2μm≦L N2 ≤5.7μm.

[0026] The doping concentration range of the P-type buried layer is 5 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 ;

[0027] The first and second buried areas of type P have the same thickness T. P And the thickness T of the P-type buried layer P 0.1μm≦T P ≤0.15μm;

[0028] The first end of the P-type first buried region is adjacent to the source electrode, the second end of the P-type first buried region is adjacent to the drain electrode, and the lateral distance between the first end of the P-type first buried region and the source electrode is 0.5μm to 1μm.

[0029] The first end of the P-type second buried region is adjacent to the source electrode, the second end of the P-type second buried region is adjacent to the drain electrode, the second end of the P-type second buried region is adjacent to the first end of the P-type first buried region, and the lateral distance between the second end of the P-type second buried region and the drain electrode is 0.5μm to 1μm.

[0030] The transverse length L of the first buried area of ​​type P is... P1 =4.3μm≦L P1 ≤6.8μm;

[0031] The transverse length L of the second buried area of ​​type P P2 =5.5μm≦L P2 ≤6.5μm.

[0032] Length L of the grid plate GFP =1μm≦L GFP ≤1.5μm; Lateral distance L between drain and P-GaN gate GD =16μm≦L GD ≤19μm

[0033] The length L of the source field plate covering the passivation layer SFP =14μm≦L SFP ≤15.8μm.

[0034] The C doping concentration range of the C-doped buffer layer is 2 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The length L of the C-doped buffer layer SD 21μm≦L SD ≤24μm, thickness T of the C-doped buffer layer B =4.5μm≦T B <5μm.

[0035] The advantages of this invention are: by simultaneously setting a P-type buried layer and an N-type buried layer within a C-doped buffer layer, the P-type buried layer depletes both the background carriers and channel carriers within the C-doped buffer layer. The N-type buried layer replenishes the channel carriers depleted by the P-type buried layer, thus compensating for the channel carrier loss caused by the P-type buried layer. It also alleviates the depletion effect of the C-doped buffer layer between the N-type and P-type buried layers. Therefore, while improving the transistor's breakdown voltage and Baliga power figure of merit, the transistor's conduction characteristics can be improved simultaneously. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of one embodiment of the present invention.

[0037] Figure 2 This is a schematic diagram comparing drain current curves.

[0038] Figure 3 This is a schematic diagram comparing the transfer characteristic curves.

[0039] Figure 4 This is a schematic diagram comparing the output characteristic curves.

[0040] Explanation of reference numerals in the attached figures: 301-Source electrode, 302-Source field plate, 303-P-GaN gate, 304-Gate field plate, 305-Drain electrode, 306-Passivation layer, 307-Barrier layer, 308-Channel layer, 309-C-doped buffer layer, 310-N-type second buried region, 311-P-type second buried region, 312-P-type first buried region, 313-N-type first buried region, 314-Drain metal. Detailed Implementation

[0041] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0042] In order to improve the power figure of a transistor (Baliga) while simultaneously enhancing its conduction characteristics, an embodiment of the present invention includes a GaN field-effect transistor body, wherein the GaN field-effect transistor body includes a C-doped buffer layer 309 and a device structure disposed on the C-doped buffer layer 309.

[0043] A P-type buried layer capable of depleting background carriers is provided within the C-doped buffer layer 309, and an N-type buried layer for replenishing channel carriers depleted by the P-type buried layer is provided within the C-doped buffer layer 309.

[0044] Within the C-doped buffer layer 309, the N-type buried layer is located between the P-type buried layer and the device channel layer structure.

[0045] Specifically, the GaN field-effect transistor body can adopt the form of existing common GaN field-effect transistors. The specific structural form of the GaN field-effect transistor body can be matched according to actual needs. Generally, the GaN field-effect transistor needs to include a C-doped buffer layer 309 and a device structure fabricated on the C-doped buffer layer 309. The C-doped buffer layer 309 is specifically carbon-doped GaN. Figure 1 The image shows an embodiment where the device structure is located on a C-doped buffer layer 309.

[0046] In order to improve the Baliga power figure of merit of the field-effect transistor and at the same time improve the conduction characteristics of the field-effect transistor, in one embodiment of the present invention, a P-type buried layer and an N-type buried layer are provided in the C-doped buffer layer 309, wherein the N-type buried layer is located between the P-type buried layer and the device channel layer structure in the C-doped buffer layer 309.

[0047] During operation, the P-type buried layer depletes the background carriers within the C-doped buffer layer 309, improving the leakage current of the C-doped buffer layer 309 when the field-effect transistor is in the off-state with high drain voltage bias. Simultaneously, because the P-type buried layer also has a certain depletion effect on channel carriers, the saturation current of the transistor under conduction bias decreases, while the characteristic on-resistance increases. In one embodiment of the invention, an N-type buried layer is used to replenish the channel carriers depleted by the P-type buried layer, improving the impact of the P-type buried layer on the transistor's saturation current and characteristic on-resistance. Based on the definition of Baliga power figure of merit V... 2 BR / R ON,sp It can be seen that for a field-effect transistor, due to the breakdown voltage V of the field-effect transistor... BR Stable, when the characteristic on-resistance R ON,sp When the value is reduced, the field-effect transistor (FET) can have excellent conduction characteristics and the high power figure of merit of the FET can be improved.

[0048] In one embodiment of the present invention, the N-type buried layer is separated from the P-type buried layer by a C-doped buffer layer 309, and the N-type buried layer is in contact with the channel layer 308 in the device structure.

[0049] Within the C-doped buffer layer 309, the P-type buried layer includes a first P-type buried region 312 and a second P-type buried region 311 that corresponds to the first P-type buried region 312.

[0050] The N-type buried layer includes an N-type first buried area 313 and an N-type second buried area 310 that corresponds to the N-type first buried area 313;

[0051] The first buried area 313 of type N corresponds to the first buried area 312 of type P, and the second buried area 310 of type N corresponds to the second buried area 311 of type P.

[0052] The first end of the N-type first buried region 313 is located inside the first end of the P-type first buried region 312, and the first end of the N-type first buried region 313 is flush with the end of the P-GaN gate 303 adjacent to the drain 305 in the device structure. The second end of the N-type first buried region 313 does not exceed the second end of the P-type first buried region 312, and the two ends of the N-type second buried region 310 are located inside the corresponding two ends of the P-type second buried region 311.

[0053] Depend on Figure 1As can be seen from the above description, since both the N-type buried layer and the P-type buried layer are disposed within the C-doped buffer layer 309, the N-type buried layer and the P-type buried layer are separated by the C-doped buffer layer 309, and the N-type buried layer is in contact with the channel layer 308 in the device structure. Figure 1 In the middle, the N-type buried layer and the P-type buried layer are parallel to each other.

[0054] Figure 1 In the P-type buried layer, there are two types of buried layers: a first buried area 312 and a second buried area 311. The first buried area 312 and the second buried area 311 are generally prepared using the same process. The first buried area 312 and the second buried area 311 correspond to each other, which generally means that they have the same thickness and are on the same horizontal plane. That is, the upper surface of the first buried area 312 and the upper surface of the second buried area 311 are on the same horizontal plane, and the lower surface of the second buried area 312 and the lower surface of the second buried area 311 are on the same horizontal plane.

[0055] Figure 1 In the N-type buried layer, there are N-type first buried area 313 and N-type second buried area 310. For the case where N-type first buried area 313 and N-type second buried area 310 correspond to each other, please refer to the description of P-type first buried area 312 and P-type second buried area 311. It will not be repeated here.

[0056] The N-type first buried area 313 corresponds directly to the P-type first buried area 312. Specifically, when the N-type first buried area 313 is projected orthogonally onto the P-type first buried area 312, the projection area of ​​the N-type first buried area 313 is always within the P-type first buried area 312. Similarly, the N-type second buried area 310 corresponds directly to the P-type second buried area 311, which will not be elaborated further here.

[0057] Figure 1 In the illustrated embodiment, both the N-type first buried region 313 and the N-type second buried region 310 are in contact with the channel layer 308. The second end of the N-type first buried region 313 and the first end of the N-type second buried region 310 are adjacent to each other, and the second end of the N-type first buried region 313 and the first end of the N-type second buried region 310 are separated by a C-doped buffer layer 309.

[0058] Similarly, the second end of the P-type first buried region 312 is adjacent to the first end of the P-type second buried region 311, and the second end of the P-type first buried region 312 is separated from the first end of the P-type second buried region 311 by the C-doped buffer layer 309.

[0059] In one embodiment of the present invention, both ends of the N-type first buried region 313 are located inside the corresponding ends of the P-type first buried region 312, and for the N-type first buried region 313, the first end of the N-type first buried region 313 is flush with the end of the P-GaN gate 303 adjacent to the drain 305 in the device structure.

[0060] For the N-type second buried area 310, the two ends of the N-type second buried area 310 are located inside the corresponding two ends of the P-type second buried area 311. Therefore, the lateral length of the N-type first buried area 313 is less than the lateral length of the corresponding P-type first buried area 312, and the lateral length of the N-type second buried area 310 is less than the lateral length of the corresponding P-type second buried area 311. Furthermore, there is no spatial overlap between the N-type first buried area 313 and the P-type second buried area 311. The spatial overlap specifically refers to the case where there is overlap when projected orthographically. Therefore, based on the case of spatial overlap, an embodiment without spatial overlap can be obtained.

[0061] In one embodiment of the present invention, the device structure further includes a barrier layer 307 located on the channel layer 308, a passivation layer 306 located on the barrier layer, a gate field plate 304 located on the P-GaN gate 303, a source electrode 301 for forming a source electrode, and a source field plate 302 corresponding to the source electrode 301, wherein,

[0062] The source electrode 301, drain electrode 302, channel layer 308, and barrier layer 307 all form ohmic contacts. The P-GaN gate 303 is located between the source electrode 301 and drain electrode 305. The source electrode 301 corresponds to the adjacent P-type first buried region 312, and the drain electrode 305 corresponds to the adjacent P-type second buried region 311.

[0063] The P-GaN gate 303 and the gate field plate 304 are located within the passivation layer 306, and the P-GaN gate 303 is supported on the barrier layer 307.

[0064] The source field plate 302 is connected to the source body 301 and covers the passivation layer 306, and the lateral length of the source field plate 306 on the passivation layer 306 is less than the corresponding lateral length of the passivation layer 306.

[0065] Figure 1 In the illustrated embodiment, the channel layer 308 is adjacent to the C-doped buffer layer 309, the barrier layer 307 is disposed on the channel layer 308, the P-GaN gate 303 is supported on the barrier layer 307, and the gate field plate 304 is located on the P-GaN gate 303 to lead out the P-GaN gate to form the gate terminal of the field-effect transistor. The specific configuration of the channel layer 308 and the barrier layer 307 can be consistent with existing designs. On both sides of the P-GaN gate 303, a two-dimensional electron gas (2DEG) is formed at the junction of the channel layer 308 and the barrier layer 307. The P-GaN gate 303 and the gate field plate 304 are encapsulated on the barrier layer 307 using a passivation layer 306.

[0066] To form the source and drain electrodes of the field-effect transistor, an ohmic contact is formed between the source electrode 301, the channel layer 308, and the barrier layer 307, and an ohmic contact is formed between the drain electrode 305, the channel layer 308, and the barrier layer 307. Figure 1 In the process, the source electrode 301 and the drain electrode 305 are located at both ends of the barrier layer 307, and the source electrode 301 is electrically connected to the source electrode 302 to form the source electrode; at the same time, the drain electrode 314 is electrically connected to the drain electrode 305 to form the drain electrode.

[0067] The source field plate 302 includes a portion corresponding to the side of the passivation layer 306 and a portion laterally covering the passivation layer 306. The portion laterally covering the passivation layer 306 is smaller than the lateral width of the passivation layer 306; that is, in the lateral direction, the length of the source field plate 302 is less than the length of the passivation layer 306. In this case, the source field plate 302 does not contact the drain metal 314. Specifically, "lateral" refers to the direction perpendicular to the N-type buried layer towards the P-type buried layer.

[0068] To effectively compensate for channel carriers, in one embodiment of the present invention, the N-type buried layer doping concentration ranges from 6 × 10⁻⁶. 17 cm -3 ~2×10 18 cm -3 The spacing H between the N-type and P-type buried layers NP =0.05μm≦H NP ≤0.25μm;

[0069] The N-type first buried region 313 and the N-type second buried region 310 are located between the drain body 305 and the end of the P-GaN gate 303 adjacent to the drain body 305, wherein,

[0070] The N-type first buried region 313 spatially overlaps with the source field plate 302 on the cover passivation layer 306, while the N-type second buried region 310 spatially does not overlap with the source field plate 302.

[0071] Depend on Figure 1 As can be seen from the embodiments shown, the spacing between the N-type buried layer and the P-type buried layer specifically refers to the spacing between the N-type first buried area 313 and the P-type first buried area 312, or the spacing between the N-type second buried area 310 and the P-type second buried area 311.

[0072] Figure 1In the cross-section, the P-GaN gate 303 is blocky. The first end of the N-type first buried region 313 specifically refers to the end relative to the adjacent source 301, and the second end of the N-type first buried region 313 is the end relative to the adjacent drain 305. Therefore, based on the first and second ends of the N-type first buried region 313, the corresponding first and second ends of the N-type second buried region 310, the P-type first buried region 312, and the P-type second buried region 311 can be determined.

[0073] In specific implementation, the N-type first buried region 313 and the N-type second buried region 310 need to be located between the drain body 305 and the end of the P-GaN gate 303 adjacent to the drain body 305. Of course, in the N-type first buried region 313 and the second N-type second buried region 310, the N-type first buried region 313 is relatively adjacent to the P-GaN gate 303 and the source body 301, while the N-type second buried region 310 is relatively adjacent to the drain body 305.

[0074] As explained above, since the source field plate 302 partially covers the passivation layer 306, in one embodiment of the present invention, the N-type first buried region 313 spatially overlaps with the source field plate 302 covering the passivation layer 306, while the N-type second buried region 310 spatially does not overlap with the source field plate 302. Spatial overlap specifically means that when the N-type first buried region 313 projects onto the source field plate 302 covering the passivation layer 306, the projected area is located on the source field plate 302. Similarly, spatial non-overlap means that when the N-type second buried region 310 projects onto the source field plate 302 covering the passivation layer 306, the projected area does not intersect with the source field plate 302, meaning that there is no source field plate 302 directly above the N-type second buried region 310.

[0075] Furthermore, the N-type first buried area 313 and the N-type second buried area 310 have the same thickness T. N And the thickness T of the N-type buried layer N =0.1μm≦T N ≤0.15μm;

[0076] The lateral length L of the first buried area 313 of type N N1 =0.8μm≦L N1 ≤1.3μm; Lateral length L of the second buried zone 310 of type N N2 =5.2μm≦L N2 ≤5.7μm.

[0077] In practice, by adjusting the thickness of the N-type buried layer and the corresponding lateral lengths of the N-type first buried area 313 and the N-type second buried layer 310, the stability and reliability of the N-type buried layer when replenishing channel carriers can be improved.

[0078] In one embodiment of the present invention, the doping concentration of the P-type buried layer is in the range of 5 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 ;

[0079] The first buried area 311 and the second buried area 312 of type P have the same thickness T. P And the thickness T of the P-type buried layer P 0.1μm≦T P ≤0.15μm;

[0080] The first end of the P-type first buried region 312 is adjacent to the source electrode 301, the second end of the P-type first buried region 312 is adjacent to the drain electrode 305, and the lateral distance between the first end of the P-type first buried region 312 and the source electrode 301 is 0.5μm to 1μm.

[0081] The first end of the P-type second buried region 311 is adjacent to the source electrode 301, the second end of the P-type second buried region 311 is adjacent to the drain electrode 305, the second end of the P-type second buried region 311 is adjacent to the first end of the P-type first buried region 311, and the lateral distance between the second end of the P-type second buried region 311 and the drain electrode 305 is 0.5μm to 1μm.

[0082] In specific implementation, the lateral length L of the first buried area 312 of type P is... P1 =4.3μm≦L P1 ≤6.8μm; Lateral length L of P-type second buried zone 311 P2 =5.5μm≦L P2 ≤6.5μm. Figure 1 In the middle, the first buried region 312 of the P type is adjacent to the source electrode 301, but does not contact the source electrode 301, and the second buried region 311 of the P type is adjacent to the drain electrode 305, but does not contact the drain electrode 305.

[0083] The lateral distance between the first end of the P-type first buried region 312 and the source electrode 301 specifically refers to the vertical distance between the second end of the P-type first buried region 312 and the source electrode 301 in the lateral direction. For the lateral distance between the second end of the P-type second buried region 311 and the drain electrode 305, please refer to the explanation of the lateral distance between the first end of the P-type first buried region 312 and the source electrode 301.

[0084] In specific implementation, the first buried region 312 of the P-type overlaps with part of the space on the passivation layer 306 covered by the source field plate 302, the first end of the second buried region 311 overlaps with part of the space on the passivation layer 306 covered by the source field plate 302, and the second end of the second buried region 311 does not overlap with part of the space on the passivation layer 306 covered by the source field plate 302.

[0085] In one embodiment of the present invention, the length L of the gate plate 304 is... GFP =1μm≦L GFP ≤1.5μm; Lateral distance L between drain 305 and P-GaN gate 303 GD =16μm≦L GD ≤19μm.

[0086] The length L of the source field plate 302 covering the passivation layer 306 SFP =14μm≦L SFP ≤15.8μm.

[0087] In specific implementation, the C doping concentration of the C-doped buffer layer 309 is in the range of 2 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The length L of the C-doped buffer layer 309 SD 21μm≦L SD ≤24μm, thickness T of C-doped buffer layer 309 B =4.5μm≦T B <5μm. The characteristic parameters of the C-doped buffer layer 309, etc., can be selected and determined according to the actual application scenario, so as to meet the usage requirements of the field-effect transistor.

[0088] For the aforementioned device structure and N-type and P-type buried layers, when the drain electrode is under high voltage bias, a high electric field distribution exists below the P-GaN gate 303 adjacent to the drain body 305, and in the area between the P-GaN gate 303 and the drain body 305 not covered by the extended source field plate 302. Under the action of the vertical component of the high electric field, the N-type buried layer, the P-type buried layer, and the corresponding C-doped buffer layer 309 can form a reverse-biased PIN diode. The formed PIN diode can modulate the electric field distribution between the gate and drain and suppress leakage current in the aforementioned two regions. This achieves the goal of improving the transistor's withstand voltage while avoiding device saturation current and characteristic on-resistance (R0) caused by the introduction of the P-type buried layer. ON,sp The degradation of ).

[0089] In practice, simulations were conducted to compare three structural cases within the C-doped buffer layer 309: no P-type buried layer, no N-type buried layer, only P-type buried layer, and both P-type and N-type buried layers.

[0090] During the simulation comparison, the three structural cases were modeled and simulated using Sentaurus TCAD software. Based on the models calibrated with experimental data, the pressure resistance and conductivity characteristics of the three structures were compared.

[0091] Figure 2 The curves show the comparison of source and drain currents in the off state under the same device structure and parameters. The bias conditions are: the gate electrode and source electrode are zero biased, the drain electrode bias is gradually increased, and the drain-source current increases to 0.1mA / mm, which is the breakdown termination condition of the field-effect transistor. Figure 2 In the diagram, the horizontal axis represents the drain voltage, and the vertical axis represents the drain-source current. The comparison shows that without P-type and N-type buried layers within the C-doped buffer layer 309, the device structure has a breakdown voltage of 1210V (V). BR Based on this structure, by adding a P-type buried layer to the C-doped buffer layer 309, V can be... BR Upgraded to 1716V.

[0092] When both a P-type buried layer and an N-type buried layer are simultaneously formed within the C-doped buffer layer 309, the V-type structure of the device is... BR The voltage rating is 1504V. The reason for this result is that when there is only a P-type buried layer in the C-doped buffer layer 309, the P-type buried layer has a depletion effect on both the background carriers and channel carriers in the C-doped buffer layer 309. By reducing the concentration of background carriers, the leakage current of the C-doped buffer layer 309 is improved, thereby improving the off-state breakdown voltage of the field-effect transistor. However, when both N-type and P-type buried layers are provided, the N-type buried layer alleviates the depletion effect of the C-doped buffer layer 309 between the P-type and N-type buried layers, resulting in a breakdown voltage lower than that when there is only a P-type buried layer.

[0093] Depend on Figure 2 Simulation comparisons show that both setting only a P-type buried layer in the C-doped buffer layer 309 and setting both P-type and N-type buried layers can improve the VT of the field-effect transistor. BR However, the main difference between the two lies in the huge difference in the conduction characteristics of field-effect transistors.

[0094] Figure 3 In the simulation, the horizontal axis represents the gate voltage and the vertical axis represents the drain-source current. The bias conditions are: zero bias at the source electrode, a fixed bias of 12V at the drain electrode, and the gate electrode bias is increased from 0V to 6V. Figure 4 In the diagram, the horizontal axis represents the drain voltage, and the vertical axis represents the drain-source current. The simulation bias conditions are: zero bias at the source electrode, a fixed bias of 6V at the gate electrode, and a drain electrode bias increasing from 0V to 15V. Through observation and analysis... Figure 3 and Figure 4 It can be seen that when no P-type or N-type buried layer is provided in the C-doped buffer layer 309, the corresponding device saturation current and characteristic on-resistance are 0.274 A / mm and 5.26 mΩ·cm, respectively. 2 The Baliga power figure of merit is 0.278 GW / cm². 2When only a P-type buried layer is set within the C-doped buffer layer 309, the corresponding device saturation current and characteristic on-resistance are 0.194 A / mm and 5.36 mΩ·cm, respectively. 2 The Baliga power figure of merit is 0.704 GW / cm². 2 Compared to embodiments without P-type and N-type buried layers, the saturation current is reduced by 29.2%, the characteristic on-resistance is increased by 1.9%, and the Baliga power figure of merit is increased by 153%, which means that the device's current carrying capacity is reduced and the conduction loss is increased, as well as having a higher Baliga power figure of merit.

[0095] When both a P-type buried layer and an N-type buried layer are simultaneously formed within the C-doped buffer layer 309, the corresponding device saturation current and characteristic on-resistance are 0.269 A / mm and 4.18 mΩ·cm, respectively. 2 The Baliga power figure of merit is 0.541 GW / cm². 2 Compared to implementations without P-type and N-type buried layers, the saturation current is reduced by 1.8%, the characteristic on-resistance is reduced by 20.4%, and the Baliga power figure of merit is increased by 95%. This indicates that the device's current carrying capacity remains almost unchanged, while the conduction loss decreases as the characteristic on-resistance decreases, and it also has a high Baliga power figure of merit.

[0096] In summary, through comparative analysis of the above data, when the C-doped buffer layer 309 contains only a P-type buried layer, the P-type buried layer depletes both the background carriers and channel carriers within the C-doped buffer layer 309, thus reducing the improvement in VL of the field-effect transistor. BR While achieving the Baliga power figure of merit, the current-carrying capacity and characteristic on-resistance of the field-effect transistor also degrade.

[0097] This invention introduces both an N-type buried layer and a P-type buried layer within the C-doped buffer layer 309. The N-type buried layer compensates for the channel carrier loss caused by the P-type buried layer and also alleviates the depletion effect of the C-doped buffer layer 309 between the N-type and P-type buried layers. For the formed field-effect transistor, the breakdown voltage and Baliga power figure of merit of the field-effect transistor are between those of field-effect transistors with only a P-type buried layer and those without a P-type or N-type buried layer. Compared with field-effect transistors without a P-type or N-type buried layer, the conduction characteristics of the field-effect transistor can be improved.

[0098] The above description is merely a preferred embodiment of the present invention and does not limit the present invention. Any adjustments and optimizations made within the scope of the claims of the present invention should be covered by the claims of the present invention.

Claims

1. A GaN field-effect transistor with high power figure of merit and excellent conduction characteristics, comprising a GaN field-effect transistor body, wherein the GaN field-effect transistor body includes a C-doped buffer layer and a device structure disposed on the C-doped buffer layer; characterized in that, A P-type buried layer that can deplete background carriers and channel carriers is provided in the C-doped buffer layer, and an N-type buried layer is provided in the C-doped buffer layer to replenish the channel carriers depleted by the P-type buried layer. Within the C-doped buffer layer, the N-type buried layer is located between the P-type buried layer and the device channel layer structure; The N-type buried layer is separated from the P-type buried layer by a C-doped buffer layer, and the N-type buried layer is in contact with the channel layer in the device structure. Within the C-doped buffer layer, the P-type buried layer includes a first P-type buried region and a second P-type buried region that corresponds to the first P-type buried region. The N-type buried layer includes an N-type first buried area and an N-type second buried area that corresponds to the N-type first buried area; The first buried area of ​​type N corresponds exactly to the first buried area of ​​type P, and the second buried area of ​​type N corresponds exactly to the second buried area of ​​type P. The first end of the N-type first buried region is located inside the first end of the P-type first buried region, and the first end of the N-type first buried region is flush with the end of the P-GaN gate adjacent to the drain in the device structure. The second end of the N-type first buried region does not exceed the second end of the P-type first buried region, and the two ends of the N-type second buried region are located inside the corresponding two ends of the P-type second buried region.

2. The GaN field-effect transistor with high power figure of merit and excellent conduction characteristics according to claim 1, characterized in that: The device structure also includes a barrier layer on the channel layer, a passivation layer on the barrier layer, a gate field plate on the P-GaN gate, a source electrode for forming the source electrode, and a source field plate corresponding to the source electrode, wherein, The source and drain are all in ohmic contact with the channel layer and barrier layer. The P-GaN gate is located between the source and drain. The source corresponds to the adjacent P-type first buried region and the drain corresponds to the adjacent P-type second buried region. The P-GaN gate and gate field plate are located within the passivation layer, and the P-GaN gate is supported on the barrier layer. The source field plate is connected to the source body and covers the passivation layer, and the lateral length of the source field plate on the passivation layer is less than the corresponding lateral length of the passivation layer.

3. The GaN field-effect transistor with high power figure of merit and excellent conduction characteristics according to claim 2, characterized in that: The doping concentration of the N-type buried layer is in the range of 6 × 10⁻⁶. 17 cm -3 ~2×10 18 cm -3 The spacing H between the N-type and P-type buried layers NP For: 0.05μm≦H NP ≤0.25μm; The N-type first buried region and the N-type second buried region are located between the drain electrode and the end of the P-GaN gate adjacent to the drain electrode, wherein... The first buried region of the N-type overlaps with the source field plate space on the cover passivation layer, while the second buried region of the N-type overlaps with the source field plate space.

4. The GaN field-effect transistor with high power figure of merit and excellent conduction characteristics according to claim 3, characterized in that: The first and second buried areas of type N have the same thickness T. N And the thickness T of the N-type buried layer N =0.1μm≦T N ≤0.15μm; The transverse length L of the first buried area of ​​type N N1 =0.8μm≦L N1 ≤1.3μm; Lateral length L of the second buried zone of type N N2 =5.2μm≦L N2 ≤5.7μm.

5. The GaN field-effect transistor with high power figure of merit and excellent conduction characteristics according to claim 2, characterized in that: The doping concentration range of the P-type buried layer is 5 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 ; The first and second buried areas of type P have the same thickness T. P And the thickness T of the P-type buried layer P 0.1μm≦T P ≤0.15μm; The first end of the first buried region of the P-type is adjacent to the source electrode, the second end of the first buried region of the P-type is adjacent to the drain electrode, and the lateral distance between the first end of the first buried region of the P-type and the source electrode is 0.5μm to 1μm. The first end of the P-type second buried region is adjacent to the source electrode, the second end of the P-type second buried region is adjacent to the drain electrode, the second end of the P-type second buried region is adjacent to the first end of the P-type first buried region, and the lateral distance between the second end of the P-type second buried region and the drain electrode is 0.5μm to 1μm.

6. The GaN field-effect transistor with high power figure of merit and excellent conduction characteristics according to claim 5, characterized in that: The transverse length L of the first buried area of ​​type P is... P1 4.3μm≦L P1 ≤6.8μm; The transverse length L of the second buried area of ​​type P P2 =5.5μm≦L P2 ≤6.5μm.

7. The GaN field-effect transistor with high power figure of merit and excellent conduction characteristics according to claim 2, characterized in that: Length L of the grid plate GFP =1μm≦L GFP ≤1.5μm; Lateral distance L between drain and P-GaN gate GD =16μm≦L GD ≤19μm.

8. The GaN field-effect transistor with high power figure of merit and excellent conduction characteristics according to claim 2, characterized in that: The length L of the source field plate covering the passivation layer SFP =14μm≦L SFP ≤15.8μm.

9. The GaN field-effect transistor with high power figure of merit and excellent conduction characteristics according to any one of claims 1 to 8, characterized in that: The C doping concentration range of the C-doped buffer layer is 2 × 10⁻⁶. 16 cm -3 ~1×10 17 cm -3 The length L of the C-doped buffer layer SD 21μm≦L SD ≤24μm, thickness T of the C-doped buffer layer B =4.5μm≦T B <5μm.

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