Semiconductor devices and their manufacturing methods

Abstract

A semiconductor device includes first and second nitrogen-based semiconductor layers, a gate electrode, a source electrode, a drain electrode, and a group of negatively charged ions. The gate electrode is disposed above the second nitrogen-based semiconductor layer. The source electrode and drain electrode are disposed above the second nitrogen-based semiconductor layer. The gate electrode is located between the source electrode and the drain electrode to define a drift region between the gate electrode and the drain electrode. A group of negatively charged ions is injected into the drift region and the 2DEG region, and spaced apart from the gate electrode and the drain electrode, and separated from the region directly below the gate electrode and the drain electrode. The gate electrode is closer to the negatively charged ions than the drain electrode, such that the negatively charged ions deplete at least a portion of the 2DEG region near the gate electrode.

Description

[0001] This application is a divisional application of Chinese patent application 202180007253.X entitled "Semiconductor device and method of manufacturing thereof", filed on December 31, 2021. Technical Field

[0002] This invention generally relates to nitrogen-based semiconductor devices. More specifically, this invention relates to a semiconductor device having negatively charged ions. Background Technology

[0003] In recent years, in-depth research on high-hole-mobility transistors (HHMTs) has been widespread, especially in high-power switching and high-frequency applications. Group III nitrogen-based HHMTs utilize a heterojunction interface between two materials with different band gaps to form a quantum well-like structure. This structure accommodates a two-dimensional hole gas (2DHG) region to meet the requirements of high-power / frequency devices. Besides HEMTs, examples of devices with heterostructures include heterojunction bipolar transistors (HBTs), heterojunction field-effect transistors (HFETs), and modulation-doped FETs (MODFETs). Summary of the Invention

[0004] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a first nitrogen-based semiconductor layer, a second nitrogen-based semiconductor layer, a gate electrode, and a doped nitrogen-based semiconductor layer. The second nitrogen-based semiconductor layer is disposed on the first nitrogen-based semiconductor layer and has a band gap greater than that of the first nitrogen-based semiconductor layer. The gate electrode is disposed above the second nitrogen-based semiconductor layer. The doped nitrogen-based semiconductor layer is disposed between the second nitrogen-based semiconductor layer and the gate electrode. The doped nitrogen-based semiconductor layer has a pair of opposing protrusions and an intermediate portion. The protrusions are not covered by the gate electrode, and the intermediate portion is located between the protrusions. The second nitrogen-based semiconductor layer has a first portion and a second portion, the first portion being located below the intermediate portion and the second portion being located below the protrusions. The second nitrogen-based semiconductor layer has a doping concentration of a dopant selected from a highly electronegative element group, wherein the dopant is selected from a highly electronegative element group, and the doping concentration increases from the first portion to the second portion.

[0005] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method includes the following steps: forming a first nitrogen-based semiconductor layer; forming a second nitrogen-based semiconductor layer on the first nitrogen-based semiconductor layer; forming a doped nitrogen-based semiconductor blanket layer on the second nitrogen-based semiconductor layer; forming a gate electrode blanket layer on the doped nitrogen-based semiconductor blanket layer; forming a first dielectric layer on the gate electrode blanket layer; patterning the gate electrode blanket layer and the first dielectric layer to form a gate electrode covered by the patterned first dielectric layer, thereby exposing the doped nitrogen-based semiconductor blanket layer; performing an ion implantation process to dope at least a portion of the second nitrogen-based semiconductor layer with a dopant selected from highly electronegative element groups, wherein at least a portion is beneath the exposed doped nitrogen-based semiconductor blanket layer; and removing the exposed doped nitrogen-based semiconductor blanket layer.

[0006] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a first nitrogen-based semiconductor layer, a second nitrogen-based semiconductor layer, a gate electrode, and a doped nitrogen-based semiconductor layer. The second nitrogen-based semiconductor layer is disposed on the first nitrogen-based semiconductor layer, and has a band gap greater than that of the first nitrogen-based semiconductor layer. The gate electrode is disposed above the second nitrogen-based semiconductor layer. The doped nitrogen-based semiconductor layer is disposed between the second nitrogen-based semiconductor layer and the gate electrode. The doped nitrogen-based semiconductor layer has a pair of opposing side surfaces, the distance between the side surfaces being greater than the width of the gate electrode. The second nitrogen-based semiconductor layer has a doping concentration of a dopant selected from the group of highly electronegative elements, and the doping concentration decreases and then increases between the side surfaces of the second doped nitrogen-based semiconductor layer.

[0007] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a first nitrogen-based semiconductor layer, a second nitrogen-based semiconductor layer, a gate electrode, a source electrode, a drain electrode, and a group of negatively charged ions. The second nitrogen-based semiconductor layer is disposed on the first nitrogen-based semiconductor layer and has a band gap larger than that of the first nitrogen-based semiconductor layer to form a heterojunction having a two-dimensional electron gas (2DEG) region therebetween. The gate electrode is disposed above the second nitrogen-based semiconductor layer. The source electrode and drain electrode are disposed above the second nitrogen-based semiconductor layer. The gate electrode is located between the source electrode and the drain electrode to define a drift region between the gate electrode and the drain electrode. A group of negatively charged ions is injected into the drift region and the 2DEG region, and spaced apart from the gate electrode and the drain electrode, and from the region directly below the gate electrode and the drain electrode. The gate electrode is closer to the negatively charged ions than the drain electrode, such that the negatively charged ions deplete at least a portion of the 2DEG region near the gate electrode.

[0008] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method includes the following steps: forming a first nitrogen-based semiconductor layer; forming a second nitrogen-based semiconductor layer on the first nitrogen-based semiconductor layer; forming a doped nitrogen-based semiconductor blanket layer on the second nitrogen-based semiconductor layer; forming a mask having at least one opening on the doped nitrogen-based semiconductor blanket layer to expose at least a portion of the doped nitrogen-based semiconductor blanket layer; performing an ion implantation process using negatively charged ions to distribute negatively charged ions in the exposed portion of the doped nitrogen-based semiconductor blanket layer and in a portion of the second nitrogen-based semiconductor layer below the exposed portion of the doped nitrogen-based semiconductor blanket layer; removing the mask from the doped nitrogen-based semiconductor blanket layer; forming a doped nitrogen-based semiconductor layer by removing the exposed portion of the doped nitrogen-based semiconductor blanket layer; patterning the doped nitrogen-based semiconductor blanket layer to remove the exposed portion of the doped nitrogen-based semiconductor blanket layer; and removing the mask from the doped nitrogen-based semiconductor blanket layer. The doped nitrogen-based semiconductor blanket is patterned to remove the exposed portions of the doped nitrogen-based semiconductor blanket, thereby forming a doped nitrogen-based semiconductor layer.

[0009] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a first nitrogen-based semiconductor layer, a second nitrogen-based semiconductor layer, at least one high-resistivity block, a gate electrode, and a doped nitrogen-based semiconductor layer. The second nitrogen-based semiconductor layer is disposed on the first nitrogen-based semiconductor layer and has a band gap larger than that of the first nitrogen-based semiconductor layer. The at least one high-resistivity block is formed by a group of negatively charged ions and embedded in the second nitrogen-based semiconductor layer. A source electrode and a drain electrode are disposed above the second nitrogen-based semiconductor layer and spaced apart from the high-resistivity block. The gate electrode is disposed above the second nitrogen-based semiconductor layer and between the source electrode and the drain electrode. The gate electrode is vertically and horizontally separated from the high-resistivity block. The doped nitrogen-based semiconductor layer is disposed between the second nitrogen-based semiconductor layer and the gate electrode and is vertically separated from the high-resistivity block.

[0010] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a first nitrogen-based semiconductor layer, a second nitrogen-based semiconductor layer, a group of negatively charged ions, and a field plate. The second nitrogen-based semiconductor layer is disposed on the first nitrogen-based semiconductor layer and has a band gap larger than that of the first nitrogen-based semiconductor layer, so as to form a heterojunction having a two-dimensional electron gas (2DEG) region therebetween. A gate electrode and a drain electrode are disposed above the second nitrogen-based semiconductor layer to define a drift region therebetween. A group of negatively charged ions is implanted into the drift region and spaced apart from the region directly below the gate electrode and the drain electrode to form at least one high-resistivity block in the second nitrogen-based semiconductor layer. The field plate is disposed on the gate electrode and extends in the region between the gate electrode and the high-resistivity block.

[0011] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method includes the following steps: forming a first nitrogen-based semiconductor layer; forming a second nitrogen-based semiconductor layer on the first nitrogen-based semiconductor layer; forming a gate electrode on the second nitrogen-based semiconductor layer; forming a first dielectric layer to cover the gate electrode; forming a mask with openings on the second nitrogen-based semiconductor layer and the first dielectric layer to expose at least a portion of the second nitrogen-based semiconductor layer from the openings; performing an ion implantation process to dope the exposed portion of the second nitrogen-based semiconductor layer with a dopant to form a high-resistivity block in the second nitrogen-based semiconductor layer, wherein the dopant is selected from the group of highly electronegative elements; forming a field plate on the gate electrode, and the field plate extending in the region between the gate electrode and the high-resistivity block.

[0012] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a first nitrogen-based semiconductor layer, a second nitrogen-based semiconductor layer, at least one high-resistivity block, a drain electrode, a gate electrode, and a field plate. The second nitrogen-based semiconductor layer is disposed on the first nitrogen-based semiconductor layer, and has a band gap larger than that of the first nitrogen-based semiconductor layer. The at least one high-resistivity block is formed by a group of negatively charged ions and doped in the second nitrogen-based semiconductor layer. The drain electrode is disposed above the second nitrogen-based semiconductor layer and spaced apart from the high-resistivity block. The gate electrode is disposed above the second nitrogen-based semiconductor layer and is vertically and horizontally separated from the high-resistivity block. The field plate is disposed above the gate electrode. The vertical projection of the field plate onto the second nitrogen-based semiconductor layer at least partially overlaps with the high-resistivity block.

[0013] With the above configuration, the electric field distribution of the semiconductor device can be modified by implanting at least a second nitrogen-based semiconductor layer (e.g., a barrier layer). Therefore, semiconductor devices can be fabricated without using any field plates or with only a single field plate. Attached Figure Description

[0014] When read in conjunction with the accompanying drawings, various aspects of this disclosure can be readily understood from the following detailed description. It should be noted that the features are not drawn to scale. In fact, for ease of discussion, the dimensions of various features can be arbitrarily increased or decreased. Embodiments of the invention are described in more detail below with reference to the accompanying drawings, wherein:

[0015] Figure 1A This is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0016] Figure 1B yes Figure 1A Enlarged vertical cross-sectional view of region A in the middle;

[0017] Figure 2A , Figure 2B , Figure 2C, Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H The diagram shows different stages of a semiconductor device manufacturing method according to some embodiments of the present invention;

[0018] Figure 3 This is an enlarged vertical cross-sectional view of a semiconductor device region according to some embodiments of the present invention;

[0019] Figure 4 This is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0020] Figure 5A This is a top view of a semiconductor device according to some embodiments of the present invention;

[0021] Figure 5B yes Figure 5A Vertical cross-sectional view of a semiconductor device;

[0022] Figure 5C yes Figure 5B The distribution of negatively charged ions in a region of a semiconductor device;

[0023] Figure 6A , Figure 6B , Figure 6C and Figure 6D The diagram shows different stages of a method for manufacturing a semiconductor device according to some embodiments of the present invention;

[0024] Figure 7 This is a top view of a semiconductor device according to some embodiments of the present invention;

[0025] Figure 8 This is a top view of a semiconductor device according to some embodiments of the present invention;

[0026] Figure 9 This is a top view of a semiconductor device according to some embodiments of the present invention;

[0027] Figure 10A This is a top view of a semiconductor device according to some embodiments of the present invention;

[0028] Figure 10B yes Figure 10A Vertical cross-sectional view of a semiconductor device;

[0029] Figure 10C yes Figure 10B The distribution of negatively charged ions in a region of a semiconductor device;

[0030] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G and Figure 11H The diagram illustrates different stages of a semiconductor device manufacturing method according to some embodiments of the present invention;

[0031] Figure 12 This is a vertical cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0032] Figure 13 This is a top view of a semiconductor device according to some embodiments of the present invention;

[0033] Figure 14 This is a top view of a semiconductor device according to some embodiments of the present invention;

[0034] Figure 15 This is a top view of a semiconductor device according to some embodiments of the present invention;

[0035] Figure 16 These are vertical cross-sectional views of semiconductor devices according to some embodiments of the present invention; and

[0036] Figure 17A , Figure 17B , Figure 17C and Figure 17D The diagram illustrates different stages of a method for manufacturing a semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0037] Throughout the accompanying drawings and detailed description, the same reference numerals will be used to denote the same or similar parts. The embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0038] In spatial descriptions, terms such as "up," "down," "above," "left," "right," "below," "top," "bottom," "vertical," "horizontal," "one side," "higher," "lower," "above," "above," and "below" are defined for a specific plane of a component or a group of components. The orientation of a component can be shown in its corresponding diagram. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and the structures described herein can be arranged in space in any orientation or manner in practice, provided that the advantages of the embodiments of the present invention are not deviated from by such arrangement.

[0039] Furthermore, it should be noted that the actual shapes of various structures depicted as approximately rectangular may, in actual devices, be curved, have rounded edges, or have uneven thicknesses, due to the manufacturing conditions of the device. In this invention, the use of straight lines and right angles is solely for the convenience of representing layers and technical features.

[0040] In the following description, semiconductor devices / chips / packages and methods of manufacturing thereof are listed as preferred examples. Those skilled in the art will understand that modifications, including additions and / or substitutions, can be made without departing from the scope and spirit of the invention. Specific details may be omitted to avoid obscuring the invention; however, the content of this invention is intended to enable those skilled in the art to implement the teachings within the scope of this invention without excessive experimentation.

[0041] Figure 1A This is a vertical cross-sectional view of a semiconductor device 1A according to some embodiments of the present invention. Figure 1B yes Figure 1A Enlarged vertical cross-sectional view of region A in the middle. Figure 1A and 1B Directions D1 and D2 are marked, where direction D1 is different from direction D2. In some embodiments, directions D1 and D2 are perpendicular to each other. For example, direction D1 is... Figure 1A and 1B The horizontal direction, and direction D2 is Figure 1A and 1B The vertical direction.

[0042] Semiconductor device 1A includes a substrate 10, a buffer layer 12, nitrogen-based semiconductor layers 14A and 16A, electrodes 20 and 22, a doped nitrogen-based semiconductor layer 32A, a gate electrode 34, dielectric layers 50, 52 and 54, a passivation layer 60, contact vias 70 and 72, and a patterned circuit layer 80.

[0043] Substrate 10 may be a semiconductor substrate. Exemplary materials for substrate 10 may include, for example, but not limited to, silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide, p-type doped silicon, n-type doped silicon, sapphire, semiconductor-on-insulator (e.g., silicon-on-insulator, SOI) or other suitable substrate materials. In some embodiments, substrate 10 may include, for example, but not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., group III-V compounds). In other embodiments, substrate 10 may include, for example, but not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof.

[0044] A buffer layer 12 may be disposed on / above / over the substrate 10. The buffer layer 12 may be disposed between the substrate 10 and the nitrogen-based semiconductor layer 14A. The buffer layer 12 may be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitrogen-based semiconductor layer 14A, thereby repairing defects caused by mismatches / differences. The buffer layer 12 may include a III-V compound. III-V compounds may include, for example, but not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Therefore, exemplary materials for the buffer layer 12 may also include, for example, but not limited to, gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (InAlGaN), or combinations thereof. In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown). The nucleation layer may be formed between the substrate 10 and the buffer layer 12. The nucleation layer may be configured to provide a transition to accommodate mismatches / differences between the III-nitride layers of the substrate 10 and the buffer layer. Exemplary materials for the nucleation layer may include, for example, but not limited to, aluminum nitride (AlN) or any alloy thereof.

[0045] A nitrogen-based semiconductor layer 14A is disposed on / above / over the buffer layer 12. A nitrogen-based semiconductor layer 16A is disposed on / above / over the nitrogen-based semiconductor layer 14A. Exemplary materials for the nitrogen-based semiconductor layer 14A may include, for example, but not limited to, nitrides or III-V compounds, such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and In... x Al y Ga (1–x–y) N, where x+y≤1, Al x Ga (1–x) N, where x ≤ 1. Exemplary materials for the nitrogen-based semiconductor layer 16A may include, for example, but not limited to, nitrides or III-V compounds, such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and In... x Al y Ga (1–x–y) N, where x+y≤1, Al y Ga (1–y) N where y≤1.

[0046] Exemplary materials for the nitrogen-based semiconductor layers 14A and 16A can be selected such that the band gap (i.e., the forbidden band width) of the nitrogen-based semiconductor layer 16A is greater than / higher than the band gap of the nitrogen-based semiconductor layer 14A. This results in their electron affinities being different from each other, forming a heterojunction between them. For example, when the nitrogen-based semiconductor layer 14A is selected as an unintentionally doped gallium nitride (GaN) layer (or may be referred to as an undoped gallium nitride layer) with a band gap of about 3.4 eV, the nitrogen-based semiconductor layer 16A can be selected as an aluminum gallium nitride (AlGaN) layer with a band gap of about 4.0 eV. Thus, the nitrogen-based semiconductor layers 14A and 16A can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the interface between the channel layer and the barrier layer, causing electrons to accumulate in the triangular well, thereby creating a two-dimensional electron gas (2DEG) region near the heterojunction. Therefore, the semiconductor device 1A may include at least one gallium nitride-based high-electron-mobility transistor (HEMT).

[0047] Electrodes 20 and 22 may be disposed on / above / over / on the nitrogen-based semiconductor layer 16A. Electrodes 20 and 22 may be in contact with the nitrogen-based semiconductor layer 16A. In some embodiments, electrode 20 may serve as a source electrode. In some embodiments, electrode 20 may serve as a drain electrode. In some embodiments, electrode 22 may serve as a source electrode. In some embodiments, electrode 22 may serve as a drain electrode. The function of electrodes 20 and 22 depends on the device design.

[0048] In some embodiments, electrodes 20 and 22 may include, for example, but not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds (e.g., silicides and nitrides), other conductive materials, or combinations thereof. Exemplary materials for electrodes 20 and 22 may include, for example, but not limited to, titanium (Ti), aluminum silicon (AlSi), titanium nitride (TiN), or combinations thereof. Each of electrodes 20 and 22 may be a single layer or a multilayer with the same or different compositions. Electrodes 20 and 22 form an ohmic contact with the nitrogen-based semiconductor layer 16A. Furthermore, the ohmic contact can be achieved by applying titanium (Ti), aluminum (Al), or other suitable materials to electrodes 20 and 22. In some embodiments, each electrode 20 and 22 is formed from at least one conformal layer and a conductive filler. The conformal layer may cover the conductive filler. Exemplary materials for the conformal layer include, for example, but not limited to, titanium (Ti), tantalum (Ta), titanium nitride (TiN), aluminum (Al), gold (Au), aluminum silicon (AlSi), nickel (Ni), platinum (Pt), or combinations thereof. Exemplary materials for conductive fillers may include, for example, but not limited to, aluminum silicon (AlSi), aluminum copper (AlCu), or combinations thereof.

[0049] A doped nitrogen-based semiconductor layer 32A may be disposed on / above / above the nitrogen-based semiconductor layer 16A. The doped nitrogen-based semiconductor layer 32A may be in contact with the nitrogen-based semiconductor layer 16A. The doped nitrogen-based semiconductor layer 32A may be disposed between electrodes 20 and 22. The doped nitrogen-based semiconductor layer 32A may have, for example, a rectangular profile. In some embodiments, the doped nitrogen-based semiconductor layer 32A may have, for example, a trapezoidal profile.

[0050] A gate electrode 34 may be disposed on / above / over the doped nitrogen-based semiconductor layer 32A. The gate electrode 34 may contact the doped nitrogen-based semiconductor layer 32A such that the doped nitrogen-based semiconductor layer 32A may be disposed / interleaved between the gate electrode 34 and the nitrogen-based semiconductor layer 16A. The doped nitrogen-based semiconductor layer 32A has a pair of opposing side surfaces, the distance between which is greater than the width of the gate electrode 34. The gate electrode 34 may be disposed / located between electrodes 20 and 22. The distance between electrode 22 and gate electrode 34 is greater than the distance between electrode 20 and gate electrode 34. The gate electrode 34 and the doped nitrogen-based semiconductor layer 32A can constitute a gate structure.

[0051] exist Figure 1AIn the exemplary illustration, semiconductor device 1A is an enhancement-mode device, which is normally-off-state when gate electrode 34 is approximately at zero bias. Specifically, the doped nitrogen-based semiconductor layer 32A may form at least one pn junction with nitrogen-based semiconductor layer 16A to deplete the 2DEG region, such that at least one block of the 2DEG region corresponding to the location below the corresponding gate electrode 34 has different characteristics (e.g., different electron concentration) from the rest of the 2DEG region and is therefore blocked.

[0052] Due to this mechanism, semiconductor device 1A has normally closed characteristics. In other words, when no voltage is applied to the gate electrode 34 or the voltage applied to the gate electrode 34 is less than the threshold voltage (i.e., the minimum voltage required to form an inversion layer under the gate electrode 34), the block of the 2DEG region under the gate electrode 34 is continuously blocked, so no current flows through this region.

[0053] An exemplary material for the doped nitrogen-based semiconductor layer 32A may be a p-type doped material. The doped nitrogen-based semiconductor layer 32A may include, for example, but not limited to, p-type doped III-V group nitride semiconductor materials, such as p-type gallium nitride (GaN), p-type aluminum gallium nitride (AlGaN), p-type indium nitride (InN), p-type aluminum indium nitride (AlInN), p-type indium gallium nitride (InGaN), p-type aluminum indium gallium nitride (AlInGaN), or combinations thereof. In some embodiments, the p-type doped material is implemented using p-type impurities, such as dopants like beryllium (Be), zinc (Zn), cadmium (Cd), and magnesium (Mg).

[0054] In some embodiments, gate electrode 34 may comprise a metal or a metal compound. Gate electrode 34 may be formed as a single layer or as a multilayer having the same or different compositions. Exemplary materials of the metal or metal compound may include, for example, but not limited to, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), metal alloys or compounds thereof, or other metal compounds. In some embodiments, exemplary materials of gate electrode 34 may include, for example, but not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof. Electrodes 20 and 22 and gate electrode 34 may constitute a gallium nitride-based (GaN-based) HEMT device having a 2DEG region.

[0055] In some embodiments, the nitrogen-based semiconductor layer 14A includes undoped gallium nitride, the nitrogen-based semiconductor layer 16A includes aluminum gallium nitride (AlGaN), and the doped nitrogen-based semiconductor layer 32A is a p-type gallium nitride layer that can bend the underlying band structure upward and deplete the corresponding blocks of the 2DEG region, thereby putting the semiconductor device 1A in a turned-off state.

[0056] To avoid breakdown caused by strong peak electric fields near the gate electrode edge, semiconductor devices typically employ multiple field plates (i.e., more than two external field plates) to achieve a more uniform electric field distribution. However, an excessive number of field plates can lead to unnecessary parasitic / stray capacitances, limiting the device's maximum operating frequency and reducing its electrical performance and reliability. Furthermore, the introduction of multiple field plates increases the device's fabrication complexity. Therefore, improving device performance is essential.

[0057] To avoid the aforementioned problems, this invention provides a novel method for suppressing breakdown.

[0058] In embodiments of the present invention, the electric field distribution in the semiconductor device 1A is improved by regionally doping negatively charged ions (selected from the group of highly electronegative elements) into the nitrogen-based semiconductor layer 16A (e.g., a barrier layer) to modify its electrical properties. Elements in the group of highly electronegative elements have greater electronegativity than nitrogen, such as fluorine (F) or chlorine (Cl). The detailed mechanism is described below.

[0059] refer to Figure 1B The doped nitrogen-based semiconductor layer 32A includes a central portion 322A and a pair of opposing protrusions 324A and 326A. The central portion 322A is located directly below the gate electrode 34. The width of the central portion 322A is defined by the gate electrode 34. The central portion 322A is covered by the gate electrode 34. The boundary of the central portion 322A coincides with the opposite sidewalls of the gate electrode 34.

[0060] The intermediate portion 322A is located between the protrusions 324A and 326A. The protrusions 324A and 326A are not covered by the gate electrode 34. The width of the protrusion 324A is the same as the width of the protrusion 326A. In some embodiments, the width of the protrusion 324A may be different from the width of the protrusion 326A. For example, the width of the protrusion 326A may be greater than the width of the protrusion 326A, so that the width design can match the distance relationship between the electrodes 20, 22 and the gate electrode 34, thereby improving the electrical performance of the semiconductor device 1A.

[0061] refer to Figure 1BThe nitrogen-based semiconductor layer 16A includes portions 162A, 164A, 166A, 168A, and 169A. Portion 162A is located below the intermediate portion 322A. Portions 164A and 166A are located below portions 324A and 326A, respectively. The doped nitrogen-based semiconductor layer 32A has a left-side surface extending upward from the interface between portions 164A and 168A. The doped nitrogen-based semiconductor layer 32A has a right-side surface extending upward from the interface between portions 166A and 169A. Portions 168A and 169A are adjacent to portions 164A and 166A, respectively. The upper surface of portion 168A is lower than that of portion 324A, allowing portions 168A and 324A to collectively form a stepped profile. A similar configuration can be applied to portions 169A and 326A.

[0062] During the fabrication of semiconductor device 1A, after forming a doped nitrogen-based semiconductor layer 32A and a gate electrode 34, an ion implantation process is performed on the resulting structure, wherein the gate electrode 34 serves as a mask. The dopant used in the ion implantation process can be selected from the group of highly electronegative elements. In some embodiments, the group of highly electronegative elements may include fluorine (F) or chlorine (Cl).

[0063] The doping concentration distribution along lines A-A', B-B', and C-C' is as follows: Figure 1B As shown. Please refer to the concentration distribution along line AA′. Since the gate electrode 34 can prevent / block the dopant from being incorporated into / entering portions 162A and 322A during the ion implantation process, the dopant concentration in portions 162A and 322A is zero or close to zero.

[0064] Furthermore, in other regions, the doping depth of the dopant can be well controlled by changing the ion implantation energy, so that most of the dopant can be incorporated into a portion of 164A, 166A, 168A, and 169A during the ion implantation process.

[0065] Referring to the concentration distribution along line B-B', the doping concentration of the dopant in most of the protruding portions 324A and 326A is zero or close to zero. The protruding portions 324A and 326A each have a bottom portion close to portions 164A and 166A, and these bottom portions are doped such that the doping concentration of the dopant within them varies linearly from zero to a non-zero constant along their thickness direction (e.g., direction D2).

[0066] The doping concentration of portions 164A and 166A of the nitrogen-based semiconductor layer 16A remains constant along its thickness direction (e.g., direction D2). Each of the protruding portions 324A and 326A of the doped nitrogen-based semiconductor layer 32A is doped such that the doping concentration of the dopant it possesses is less than the doping concentration of portions 164A and 166A.

[0067] The nitrogen-based semiconductor layer 14A has a top located below a portion 164A / 166A of the nitrogen-based semiconductor layer 16A, and the doping concentration of the dopant on this top varies linearly from a non-zero constant to zero along its thickness direction (e.g., direction D2).

[0068] Because negatively charged ions are introduced / implanted into interstitial sites in the layer (e.g., nitrogen-based semiconductor layer 16A), these negatively charged ions, selected from highly electronegative element groups, act as negative fixed charges in the nitrogen-based semiconductor layer 16A, thereby increasing the potential of the barrier layer. Consequently, the block of the 2DEG region directly beneath portions of 164A and 166A is depleted. Therefore, this configuration reduces the electric field line density near the edge of the gate electrode 34, mitigating the peak intensity of the electric field near the gate electrode 34 and suppressing breakdown. Thus, the semiconductor device 1A can exhibit good electrical performance without the need for a field plate.

[0069] In addition, to prevent negatively charged ions from affecting the rest of the 2DEG region in semiconductor device 1A, the dopants in parts of 168A and 169A should be removed.

[0070] Specifically, after the ion implantation process, a dielectric layer 52 can be formed to cover portions 324A and 326A, while portions 168A and 169A are not covered by the dielectric layer 52. Then, an annealing process is performed to remove some dopants from portions 168A and 169A of the nitrogen-based semiconductor layer 16A.

[0071] In this regard, referring to the concentration distribution along line C-C', the doping concentration of some 168A and 169A can be zero or close to zero on their upper surfaces. This concentration distribution can be achieved by performing an annealing process.

[0072] It should be noted that a dielectric layer 52 may be formed on portions 324A and 326A prior to the annealing process to prevent dopant from diffusing from portions 324A and 326A due to the annealing process. Since the dopant can be removed from portions 168A and 169A by performing the annealing process, the corresponding blocks in the 2DEG region are protected from dopant interference.

[0073] Following the ion implantation and annealing processes, the dopant is retained / retained in portions 164A and 166A, but not in portions 168A and 169A, and most of portion 162A. Due to the annealing process, the doping concentration in portions 168A and 169A is zero or near zero. Due to the obstruction of the gate electrode 34 during the ion implantation process, the doping concentration in most of portion 162A of the nitrogen-based semiconductor layer is zero or near zero.

[0074] In some embodiments, portion 162A has a portion adjacent to portions 164A / 166A, the doping concentration of which varies linearly along its width direction (e.g., direction D1). Due to the annealing process, the doping concentration of portions 168A / 169A is less than that of portions 164A / 166A. The doping concentration from portion 168A to portion 169A, along direction D1, is sequentially: remaining at zero, increasing from zero to a non-zero constant, remaining at this non-zero constant, decreasing from this non-zero constant to zero, remaining at zero, increasing to a non-zero constant, remaining at a non-zero constant, and then decreasing to zero. In some embodiments, the increase / decrease in the doping concentration of the nitrogen-based semiconductor layer 16A is continuous.

[0075] The reason for this doping concentration distribution is to shape the depletion region in the 2DEG region. If the distribution density is too high, the resistivity will also be very high, which is detrimental to the on-resistance of the device. If the distribution density is too low, the device will have difficulty maintaining an effective normally closed state, thus leading to leakage current problems.

[0076] refer to Figure 1A and 1B A dielectric layer 50 may be disposed on / above / over / on the gate electrode 34. The dielectric layer 50 has a pair of opposing side surfaces, which are respectively connected to the two opposing side surfaces of the gate electrode 34. Exemplary materials of the dielectric layer 50 may include, for example, but not limited to, dielectric materials. For example, the dielectric layer 50 may include silicon nitride (SiN). x ) layer, silicon dioxide (SiO) x Layers, silicon oxynitride (SiON), silicon carbide (SiC), silicon boron nitride (SiBN), silicon boron carbide (SiCBN), oxides, nitrides, plasma-enhanced oxides (PEOX), or combinations thereof.

[0077] A dielectric layer 52 may be disposed on / above / over / on the doped nitrogen-based semiconductor layer 32A. The dielectric layer 52 covers the gate electrode 34 and the side surfaces of the dielectric layer 50. The dielectric layer 52 covers the protrusions 324A and 326A of the doped nitrogen-based semiconductor layer 32A, and the two opposite side surfaces of the doped nitrogen-based semiconductor layer 32A are not covered by the dielectric layer 52. An exemplary material for the dielectric layer 52 may be the same as or similar to the material of the dielectric layer 50.

[0078] A dielectric layer 54 may be disposed on / above / over the nitrogen-based semiconductor layer 16A and cover the dielectric layer 52 to form protrusions. The dielectric layer 54 has a plurality of vias TH to expose the nitrogen-based semiconductor layer 16A. Electrodes 20 and 22 may extend through the vias TH (i.e., electrodes 20 and 22 penetrate the dielectric layer 54) to contact the nitrogen-based semiconductor layer 16A. An exemplary material for the dielectric layer 54 may be the same as or similar to the material of the dielectric layer 50.

[0079] A passivation layer 60 may be disposed on / above / over / on the electrodes 20, 22 and the dielectric layer 54. An exemplary material for the passivation layer 60 may be the same as or similar to the material of the passivation layer 60. Furthermore, the passivation layer 60 may serve as a planarization layer, having a horizontal upper surface supporting other layers / elements. In some embodiments, the passivation layer 60 may be formed as a thicker layer, and a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the passivation layer 60 to remove excess material, thereby forming a horizontal upper surface.

[0080] A via 70 is disposed within the passivation layer 60. The via 70 may extend through the passivation layer 60. The via 70 may extend longitudinally to connect electrodes 20 and 22. A via 72 is located directly above / above / above the gate electrode 34. The via 72 extends through dielectric layers 50, 52, and 54 and the passivation layer 60 to connect the gate electrode 34. The upper surfaces of the vias 70 and 72 are not covered by the passivation layer 60. Exemplary materials for the vias 70 and 72 may include, for example, but not limited to, conductive materials, such as metals or alloys.

[0081] A patterned circuit layer 80 may be disposed on / above / over / on the passivation layer 60 and conductive vias 70 and 72. The patterned circuit layer 80 is in contact with the conductive vias 70 and 72. The patterned circuit layer 80 may have metal lines, pads, traces, or combinations thereof, so that the patterned circuit layer 80 can form at least one circuit. An exemplary material of the patterned circuit layer 80 may be the same as or similar to the material of the contact vias 70 and 72.

[0082] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2HA diagram illustrating different stages of a method for manufacturing semiconductor device 1A is shown below. In the following text, deposition techniques may include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

[0083] refer to Figure 2A A buffer layer 12 can be formed on / above / over the substrate 10 using a deposition technique. A nitrogen-based semiconductor layer 14A can be formed on / above / over the buffer layer 12 using a deposition technique. A nitrogen-based semiconductor layer 16A can be formed on / above / over the nitrogen-based semiconductor layer 14A using a deposition technique, thereby forming a heterojunction between them. A doped nitrogen-based semiconductor blanket layer 82 can be formed on / above / over the nitrogen-based semiconductor layer 16A. A gate electrode blanket layer 84 can be formed on / above / over the doped nitrogen-based semiconductor blanket layer 82. The material of the gate electrode blanket layer 84 can be a conductive material; therefore, the gate electrode blanket layer 84 can serve as a conductive blanket layer. A dielectric blanket layer 86 can be formed on / above / over the gate electrode blanket layer 84.

[0084] refer to Figure 2B A mask layer ML1 can be formed on the dielectric layer 86. The formation of the mask layer ML1 may include a patterning process. After the patterning process, some portions of the dielectric layer 86 can be exposed.

[0085] refer to Figure 2C A patterning process is performed on the gate electrode blanket layer 84 and the dielectric blanket layer 86 to form the gate electrode 34 and the dielectric layer 50. The gate electrode 34 is covered by the dielectric layer 50. At least a portion of the doped nitrogen-based semiconductor blanket layer 82 is exposed by the gate electrode 34 and the dielectric layer 50.

[0086] refer to Figure 2DAn ion implantation process is performed using gate electrode 34 as a mask to dope at least a portion of the nitrogen-based semiconductor layer 16A beneath the exposed doped nitrogen-based semiconductor blanket 82 with a dopant selected from the group of highly electronegative elements, which is characterized as small particles. In some embodiments, at least a portion of the doped nitrogen-based semiconductor blanket 82 is doped with a dopant. In some embodiments, the group of highly electronegative elements may include fluorine (F) or chlorine (Cl). In this regard, the doping depth of the dopant can be adjusted by changing the ion implantation energy so that most of the dopant can be doped into the nitrogen-based semiconductor layer 16A. In some embodiments, the dopant may be doped into a portion of the doped nitrogen-based semiconductor blanket 82 (the portion adjacent to the nitrogen-based semiconductor layer 16A). In some embodiments, the dopant may be doped into a portion of the nitrogen-based semiconductor layer 14A adjacent to the nitrogen-based semiconductor layer 16A.

[0087] refer to Figure 2E It can form a dielectric blanket coating 90 to cover Figure 2D The resulting structure.

[0088] refer to Figure 2F A patterning process is performed on the dielectric blanket 90 to form a dielectric layer 52 to cover the gate electrode 34 and the dielectric layer 50, thereby exposing at least a portion of the doped nitrogen-based semiconductor blanket 82.

[0089] refer to Figure 2G A patterning process is performed on the doped nitrogen-based semiconductor blanket 82 to remove excess portions of the exposed doped nitrogen-based semiconductor blanket 82, thereby forming a doped nitrogen-based semiconductor layer 32A. At least a portion of the nitrogen-based semiconductor layer 16A may be exposed. The width of the formed doped nitrogen-based semiconductor layer 32A is wider than the width of the gate electrode 34.

[0090] Then, an annealing process can be performed to remove the dopants in the exposed nitrogen-based semiconductor layer 16A. Since the doped nitrogen-based semiconductor layer 32A is covered by the dielectric layer 52 during the annealing process, the dopants in a portion of the nitrogen-based semiconductor layer 16A (located directly below the doped nitrogen-based semiconductor layer 32A) can still be retained.

[0091] refer to Figure 2H A dielectric layer 54 can be formed to cover... Figure 2GThe resulting structure exposes at least a portion of the nitrogen-based semiconductor layer 16A. The formation of the dielectric layer 54 includes deposition techniques and patterning processes. In some embodiments, deposition techniques may be performed to form a blanket layer, and patterning processes may be performed to remove excess portions. In some embodiments, the patterning process may include photolithography, exposure and development, etching, other suitable processes, or combinations thereof. Thereafter, electrodes 20 and 22, contact vias 70 and 72, a passivation layer 60, and a patterned circuit layer 80 may be formed to achieve the desired structure. Figure 1A The configuration of semiconductor device 1A shown.

[0092] Figure 3 This is an enlarged vertical cross-sectional view of a region of the semiconductor device 1B according to some embodiments of the present invention. Directions D1 and D2 are as follows: Figure 3 As shown. Semiconductor device 1B is similar to... Figure 1A and Figure 1B The semiconductor device 1A shown is different from the previous embodiment in this example.

[0093] In this embodiment, the doping concentration of the entire 324B and 326B is zero or close to zero. The doping concentration of the entire nitrogen-based semiconductor layer 14B is zero or close to zero.

[0094] Referring to the concentration distribution along line A-A', the doping concentration of a portion 166B of the nitrogen-based semiconductor layer 16B can vary linearly along its thickness direction (e.g., direction D2). Alternatively, the doping concentration of a portion 166B of the nitrogen-based semiconductor layer 16B can first increase and then decrease along its thickness direction (e.g., direction D2). The relationship between doping concentration and depth can be a curve.

[0095] Referring to the concentration distribution along line C-C', the doping concentration of some 168B and 169B is greater than zero. That is to say, the doping concentration of some 168B and 169B can be greater than the doping concentration of the portion of the nitrogen-based semiconductor layer 16B between portions 164B and 166B.

[0096] During the fabrication of semiconductor device 1B, the doping distribution of the dopant can be controlled by adjusting parameters. In some embodiments, the parameters may include ion implantation energy. In some embodiments, the parameters may include the profile of a photomask, such as a gray-tone mask or a half-tone mask, to adjust the ion implantation energy during the ion implantation process. In some embodiments, the parameters may include annealing time.

[0097] Figure 4This is a vertical cross-sectional view of a semiconductor device 1C according to some embodiments of the present invention. The semiconductor device 1C is similar to... Figure 1A The semiconductor device 1A described and shown differs in that the nitrogen-based semiconductor layer 16A is replaced by a nitrogen-based semiconductor layer 16C.

[0098] The nitrogen-based semiconductor layer 16C includes portions 162C, 164C, and 169C. Portion 162C is located directly below the gate electrode 34. Portion 164C is located between portions 162C and 169C. Portion 169C of the nitrogen-based semiconductor layer 16C has an upper surface that is lower than the positions of portions 164C and the intermediate portion 162C. Portions 162C, 164C, and 169C can collectively form a stepped profile.

[0099] In the fabrication process of semiconductor device 1C, the patterning process of the doped nitrogen-based semiconductor layer 32C can further remove some of the top portion of the nitrogen-based semiconductor layer 16C. Removing the top portion of the nitrogen-based semiconductor layer 16C can form a stepped profile. Such a profile is beneficial for controlling the distribution of dopants.

[0100] Figure 5A This is a top view of a semiconductor device 1D according to some embodiments of the present invention. Figure 5B yes Figure 5A A vertical cross-sectional view of a semiconductor device 1D. The semiconductor device 1D is similar to... Figure 1A The semiconductor device 1A described and shown differs in that the distribution of negatively charged ions is different. Orientations D1, D2, and D3 are marked on... Figure 5A and 5B In the middle, directions D1, D2, and D3 are different from each other. In some embodiments, directions D1, D2, and D3 are perpendicular to each other.

[0101] Semiconductor device 1D includes a substrate 10, a buffer layer 12, nitrogen-based semiconductor layers 14D and 16D, electrodes 20 and 22, a doped nitrogen-based semiconductor layer 32D, a gate electrode 34, a dielectric layer 54, a passivation layer 60, a contact via 70, a patterned circuit layer 80, and a group of negatively charged ions 92. Descriptions of the same or similar layers are omitted in the following paragraphs.

[0102] A drift region DR is defined between gate electrode 34 and electrode 22. A group of negatively charged ions 92 (selected from a group of highly electronegative elements) is implanted / doped into the drift region DR and the 2DEG region in the nitrogen-based semiconductor layer 14D to form a high-resistivity block 94D formed by this group of negatively charged ions 92. The high-resistivity block 94D is embedded in the nitrogen-based semiconductor layer 16D (e.g., a barrier layer).

[0103] The doped nitrogen-based semiconductor layer 32D and gate electrode 34 are vertically separated / isolated from the negatively charged ions 92. The doped nitrogen-based semiconductor layer 32D and gate electrode 34 are vertically separated / isolated from the high-resistivity block 94D. The negatively charged ions 92 are separated from the area / region directly below the gate electrode 32 and electrode 22. The negatively charged ions 92 are adjacent to the interface formed between the nitrogen-based semiconductor layer 16D and the dielectric layer 54. The high-resistivity block 94D is separated from electrodes 20 and 22. The gate electrode 34 is vertically and horizontally separated from the high-resistivity block 94D. The gate electrode 34 is closer to the negatively charged ions 92 than the electrode 22, so that the negatively charged ions 92 can deplete at least a portion of the 2DEG region near the gate electrode 34, thereby rearranging / redistributing the electric field distribution therein.

[0104] Therefore, the electric field line density near the edge of the gate electrode 34 can be reduced to alleviate the peak intensity of the electric field near the gate electrode 34, thereby suppressing breakdown. The semiconductor device 1D can then exhibit good electrical performance without the need for a field plate.

[0105] refer to Figure 5A From a top view of semiconductor device 1A, gate electrode 34 and electrodes 20 and 22 extend along direction D3. Negatively charged ions 92 are distributed along direction D3 to form a continuous high-resistance strip 94 in the drift region DR. The high-resistance strip 94D, gate electrode 34, electrode 20, and electrode 22 extend along the same direction D3.

[0106] Figure 5C yes Figure 5B The distribution of negatively charged ions 92 in the region of the semiconductor device 1D. Negatively charged ions 92 are distributed from the upper surface of the nitrogen-based semiconductor layer 16D to its lower surface. The distribution density of negatively charged ions 92 varies from the upper surface to the lower surface of the nitrogen-based semiconductor layer 16D. Along direction D2 (i.e., from the dielectric layer 54 to the nitrogen-based semiconductor layer 16D), the distribution density of negatively charged ions 92 in the nitrogen-based semiconductor layer 16D is non-uniform. The distribution density of negatively charged ions 92 in the nitrogen-based semiconductor layer 16D first increases and then decreases along direction D2. In some embodiments, the distribution of negatively charged ions 92 along the thickness direction (e.g., direction D2) of the nitrogen-based semiconductor layer 16D can be a normal distribution.

[0107] The reason for this distribution density is to shape the depletion region for the 2DEG region. If the distribution density is too high, the resistivity will also become very high, which is detrimental to the on-resistance of the device. If the distribution density is too low, the device will have difficulty maintaining an effective normally closed state, thus at least one leakage current will occur. Through methods such as... Figure 5CThe distribution density shown allows semiconductor device 1D to be used without a field plate, thus avoiding the process complexity problems caused by the field plate. Therefore, as Figure 5B The structure shown does not include any field plates. However, in this invention, it is not limited to whether or not a field plate is introduced into the structure of the semiconductor device 1D.

[0108] In some embodiments, the distribution of negatively charged ions 92 can be determined by the implantation energy of the ion implantation process. For example, by controlling the implantation energy, negatively charged ions can be doped into the nitrogen-based semiconductor layer 16D so that the negatively charged ions 92 can be separated from the upper and lower surfaces of the nitrogen-based semiconductor layer 16D.

[0109] Figure 6A , Figure 6B , Figure 6C and Figure 6D A diagram illustrating the different stages of a method for manufacturing a 1D semiconductor device is shown below.

[0110] refer to Figure 6A A buffer layer 12 can be formed on / above / over the substrate 10 using a deposition technique. A nitrogen-based semiconductor layer 14D can be formed on / above / over the buffer layer 12 using a deposition technique. A nitrogen-based semiconductor layer 16D can be formed on / above / over the nitrogen-based semiconductor layer 14D using a deposition technique, thereby forming a heterojunction between them. A doped nitrogen-based semiconductor blanket layer 82 can be formed on / above / over the nitrogen-based semiconductor layer 16D. A mask layer ML2 having at least one opening OP is formed on the doped nitrogen-based semiconductor blanket layer 82. The opening OP of the mask layer ML2 exposes at least a portion EP of the doped nitrogen-based semiconductor blanket layer 82, wherein the opening OP of the mask layer ML2 is strip-shaped.

[0111] refer to Figure 6B An ion implantation process is performed using negatively charged ions 92 to distribute the negatively charged ions 92. The negatively charged ions 92 are distributed in the exposed portion EP of the doped nitrogen-based semiconductor blanket layer 82. The negatively charged ions 92 are also distributed in a portion P of the nitrogen-based semiconductor layer 16D, and this portion P is located below the exposed portion EP of the doped nitrogen-based semiconductor blanket layer 82.

[0112] refer to Figure 6C The mask layer ML2 is removed from the doped nitrogen-based semiconductor blanket 82. A gate electrode blanket 84 is formed on the doped nitrogen-based semiconductor blanket 82.

[0113] refer to Figure 6DA patterning process is performed on the doped nitrogen-based semiconductor blanket 82 to remove the exposed portion EP of the doped nitrogen-based semiconductor blanket 82. Thus, a doped nitrogen-based semiconductor layer 32D is formed, and the doped nitrogen-based semiconductor layer 32D is separated from the negatively charged ions 92. A gate electrode 34 (e.g., a gate electrode layer) is formed on / above / over the doped nitrogen-based semiconductor layer 32D and is separated from the negatively charged ions 92. The formation of the gate electrode 34 includes deposition techniques and a patterning process. Thereafter, electrodes 20 and 22, contact vias 70 and 72, a dielectric layer 54, a passivation layer 60, and a patterned circuit layer 80 can be formed to obtain, as shown in the image. Figure 5B The configuration of semiconductor device 1D is shown.

[0114] Figure 7 This is a top view of a semiconductor device 1E according to some embodiments of the present invention. The semiconductor device 1E is similar to... Figure 5A The semiconductor device 1D described and shown differs in that the high-resistance block 94D is replaced by multiple separate high-resistance blocks 94E.

[0115] In this embodiment, negatively charged ions 92 are distributed along direction D3, which is the same as the extension direction of electrodes 20 and 22. In response to the negatively charged ions 92, high-resistivity blocks 94E are formed in the drift region DR. The high-resistivity blocks 94E are arranged along direction D3. From a top view of the semiconductor device 1E, each high-resistivity block 94E is rectangular.

[0116] Figure 8 This is a top view of a semiconductor device 1F according to some embodiments of the present invention. The semiconductor device 1F is similar to... Figure 5A The semiconductor device 1D described and shown differs in that the high-resistance block 94D is replaced by multiple separate high-resistance blocks 94F.

[0117] In this embodiment, negatively charged ions 92 are distributed along direction D3, which is the same as the extension direction of electrodes 20 and 22. In response to the negatively charged ions 92, high-resistivity blocks 94F are formed in the drift region DR. The high-resistivity blocks 94F are disposed along direction D3. Viewed from a top view of the semiconductor device 1F, each high-resistivity block 94F is elliptical. In some embodiments, viewed from a top view of the semiconductor device 1F, each high-resistivity block 94F is circular.

[0118] Figure 9 This is a top view of a semiconductor device 1G according to some embodiments of the present invention. The semiconductor device 1G is similar to a reference stencil. Figure 5A The semiconductor device 1D described and shown differs in that the high-resistance block 94D is replaced by multiple separate high-resistance blocks 94G.

[0119] In this embodiment, negatively charged ions 92 are distributed along direction D3, which is the same as the extension direction of electrodes 20 and 22. In response to the negatively charged ions 92, a high-resistivity block 94G is formed in the drift region DR. The high-resistivity block 94G is disposed along direction D3. Each high-resistivity block 94G has a short side and a long side, wherein the long side is between the short side and electrode 22. Specifically, viewed from a top view of the semiconductor device 1G, each high-resistivity block 94G is trapezoidal.

[0120] For semiconductor devices 1E, 1F and 1G, the high-resistivity blocks 94E / 94F / 94G are formed to be separated from each other, and their total resistance can be reduced.

[0121] In the fabrication of semiconductor devices 1E, 1F, and 1G, the mask layer used in the ion implantation process has multiple separate openings (OPs) to expose the doped nitrogen-based semiconductor blanket layer located beneath it. The shape of the high-resistance band in the top view of the corresponding semiconductor device can be determined by the shape of the openings (OPs).

[0122] Figure 10A This is a top view of a semiconductor device 1H according to some embodiments of the present invention. Figure 10B yes Figure 10A A vertical cross-sectional view of semiconductor device 1H is shown. Directions D1, D2, and D3 are labeled in the figure. 10A and 10B. Directions D1, D2, and D3 are different from each other. In some embodiments, directions D1, D2, and D3 are perpendicular to each other.

[0123] Semiconductor device 1H includes a substrate 10, a buffer layer 12, nitrogen-based semiconductor layers 14H and 16H, electrodes 20 and 22, a doped nitrogen-based semiconductor layer 32H, a gate electrode 34, dielectric layers 50, 52, and 54, a passivation layer 60, a contact via 70, a patterned circuit layer 80, a group of negatively charged ions 92, and a field plate 96. Descriptions of the same or similar layers are omitted.

[0124] The drift region DR is defined between the gate electrode 32 and the electrode 22. A group of negatively charged ions 92 are implanted / doped into the drift region DR and the 2DEG region, thereby forming / embedding a high-resistivity block 94H in the nitrogen-based semiconductor layer 16H (e.g., a barrier layer), wherein the negatively charged ions 92 are selected from a group of highly electronegative elements.

[0125] Gate electrode 34 and electrode 22 extend along direction D3, and negatively charged ions 92 are distributed along direction D3, forming a high-resistivity block 94H. The high-resistivity block 94H can serve as a high-resistivity strip 94H in the drift region DR. The doped nitrogen-based semiconductor layer 32H and gate electrode 34 are vertically separated from the negatively charged ions 92 / high-resistivity block 94H. The doped nitrogen-based semiconductor layer 32H is vertically and horizontally separated from the high-resistivity block 94H. Gate electrode 34 is vertically and horizontally separated from the high-resistivity block 94H. Gate electrode 34 is closer to the high-resistivity block 94H than electrode 22. Negatively charged ions 92 are separated from the area / region directly below gate electrode 32 and electrode 22.

[0126] Dielectric layers 50 and 52 may be disposed on / above / over the gate electrode 34 and the nitrogen-based semiconductor layer 16H. Dielectric layers 50 and 52 cover the gate electrode 34. The nitrogen-based semiconductor layer 16H is not covered by dielectric layers 50 and 52. Dielectric layer 54 may be disposed on / above / over the nitrogen-based semiconductor layer 16H and covers dielectric layers 50, 52 and the high-resistivity block 94H.

[0127] Field plate 96 may be disposed on / above / above dielectric layer 54. Field plate 96 may be disposed on / above / above gate electrode 34. Field plate 96 may extend in the region between gate electrode 34 and high-resistivity block 94H. Field plate 96 extends along direction D1 from gate electrode 34 to high-resistivity block 94H. Field plate 96 forms an interface with dielectric layer 54. Field plate 96 is conformal to dielectric layer 54.

[0128] The field plate 96 has two opposing ends, E1 and E2. End E1 is located directly above the gate electrode 34. End E2 is located below end E1. End E2 of the field plate 96 vertically overlaps with the high-resistance block 94H. The high-resistance block 94H is closer to the electrode 22 than end E2 of the field plate 96. The vertical projection of the field plate 96 onto the nitrogen-based semiconductor layer 16H at least partially overlaps with the high-resistance block 94H. Therefore, the electric field line density near the edge of the field plate 96 can be reduced, thereby mitigating the peak intensity of the electric field near the field plate 96 and suppressing breakdown.

[0129] Exemplary materials for the field plate 96 may include, but are not limited to, conductive materials such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof. In some embodiments, other conductive materials may also be used, such as aluminum, copper-doped silicon, and alloys comprising these materials.

[0130] In this invention, by designing the doping positions of negatively charged ions 92 according to the position of a single field plate 96, the field plate 96 and the high-resistivity block 94H can jointly adjust the electric field distribution of the semiconductor device 1H. Therefore, the semiconductor device 1H can have a good electric field distribution without using too many field plates. The reliability of the semiconductor device can be further improved.

[0131] Figure 10C yes Figure 10B Distribution of negatively charged ions in region 1H of a semiconductor device. Figure 10C The distribution of negatively charged ions 92 in the nitrogen-based semiconductor layer 16H can be compared with... Figure 5C The distribution of negatively charged ions 92 in the nitrogen-based semiconductor layer 16D is the same or similar.

[0132] As described below, Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G and Figure 11H The diagram shows different stages of a method for manufacturing semiconductor device 1H.

[0133] refer to Figure 11A A buffer layer 12 can be formed on / above / over the substrate 10 using a deposition technique. A nitrogen-based semiconductor layer 14H can be formed on / above / over the buffer layer 12 using a deposition technique. A nitrogen-based semiconductor layer 16H can be formed on / above / over the nitrogen-based semiconductor layer 14H using a deposition technique, thereby forming a heterojunction therebetween. A doped nitrogen-based semiconductor blanket layer 82 can be formed on / above / over the nitrogen-based semiconductor layer 16H. A gate electrode blanket layer 84 is formed on the doped nitrogen-based semiconductor blanket layer 82. A dielectric blanket layer 86 can be formed on / above / over the gate electrode blanket layer 84.

[0134] refer to Figure 11B A mask layer ML3 can be formed on the dielectric layer 86. The formation of the mask layer ML3 may include a patterning process. After the patterning process, some portions of the dielectric layer 86 can be exposed.

[0135] refer to Figure 11C Patterning is performed on the dielectric blanket cover 90 and the gate electrode blanket cover 84 to form the dielectric layer 50 and the gate electrode 34. The dielectric blanket cover 90 can be formed to cover the dielectric layer 50, the gate electrode 34 and the nitrogen-based semiconductor blanket cover 82.

[0136] refer to Figure 11DPatterning is performed on the dielectric blanket 90 and the nitrogen-based semiconductor blanket 82 to form a dielectric layer 52 and a doped nitrogen-based semiconductor layer 32H. The dielectric layer 52 covers the gate electrode 34 and the doped nitrogen-based semiconductor layer 32H.

[0137] A mask layer ML4 with at least one opening OP is formed on / above / over the nitrogen-based semiconductor layer 16H and the dielectric layer 52. At least a portion of the nitrogen-based semiconductor layer 16H is exposed by the opening OP. The opening OP of the mask layer ML4 is strip-shaped. Then, an ion implantation process is performed to dope the exposed portion of the nitrogen-based semiconductor layer 16H with a dopant selected from highly electronegative element groups in order to form a high-resistivity block 94H in the nitrogen-based semiconductor layer 16H.

[0138] refer to Figure 11E Mask ML4 is removed from nitrogen-based semiconductor layer 16H and dielectric layer 52.

[0139] refer to Figure 11F A dielectric blanket cladding 54' is formed to cover the dielectric layer 52 and the nitrogen-based semiconductor layer 16H. A field plate blanket cladding 98 (i.e., a conductive blanket cladding) is formed to cover the dielectric layer 54' and the gate electrode 34.

[0140] refer to Figure 11G A mask layer ML5 is formed on the field blanket cladding 98. The mask layer ML5 overlaps perpendicularly with the high resistivity layer 94H. The right end of the mask layer ML5 is located directly above the high resistivity block 94H. The left end of the mask layer ML5 is located directly above the gate electrode 34.

[0141] refer to Figure 11H A patterning process is performed on the field plate blanket 98 using a mask layer ML5 to form a field plate 96. The field plate 96 is formed above the gate electrode 34 and extends in the region between the gate electrode 34 and the high-resistivity block 94H. The left end of the field plate 96 perpendicularly overlaps with the gate electrode 34. The right end of the field plate 96 perpendicularly overlaps with the high-resistivity block 94H. Thereafter, electrodes 20 and 22, contact vias 70, a passivation layer 60, and a patterned circuit layer 80 can be formed to obtain, as shown... Figure 10B The configuration of semiconductor device 1H is shown.

[0142] Figure 12 This is a vertical cross-sectional view of a semiconductor device 1I according to some embodiments of the present invention. The semiconductor device 1I is similar to... Figure 10B The semiconductor device 1H described and shown differs in that the high-resistance block 94H is replaced by a high-resistance block 94I. The high-resistance block 94I is not covered by the field plate 96I. In the vertical direction, the boundaries of the high-resistance strip 94I and the field plate 96I completely coincide.

[0143] Figure 13This is a top view of a semiconductor device 1J according to some embodiments of the present invention. The semiconductor device 1J is similar to... Figure 10A The semiconductor device 1H described and shown differs in that the high-resistance block 94H is replaced by multiple separate high-resistance blocks 94J.

[0144] In this embodiment, negatively charged ions 92 are distributed along direction D3, which is the same as the extension direction of the field plate 96J. In response to the negatively charged ions 92, high-resistivity blocks 94J are formed in the drift region. High-resistivity blocks 94J are disposed along direction D3. From a top view of the semiconductor device 1J, each high-resistivity block 94J is rectangular.

[0145] Figure 14 This is a top view of a semiconductor device 1K according to some embodiments of the present invention. The semiconductor device 1K is similar to a reference stencil. Figure 10A The semiconductor device 1H described and illustrated differs in that the high-resistance block 94H is replaced by multiple separate high-resistance blocks 94K.

[0146] In this embodiment, negatively charged ions 92 are distributed along direction D3, which is the same as the extension direction of the field plate 96K. In response to the negatively charged ions 92, high-resistivity blocks 94K are formed in the drift region. These high-resistivity blocks 94K are disposed along direction D3. From a top view of the semiconductor device 1K, each high-resistivity block 94K is elliptical.

[0147] Figure 15 This is a top view of a semiconductor device 1L according to some embodiments of the present invention. The semiconductor device 1F is similar to... Figure 10A The semiconductor device 1H described and shown differs in that the high-resistance block 94H is replaced by multiple separate high-resistance blocks 94L.

[0148] In this embodiment, negatively charged ions 92 are distributed along direction D3, which is the same as the extension direction of the field plate 96L. In response to the negatively charged ions 92, high-resistivity blocks 94L are formed in the drift region. The high-resistivity blocks 94L are disposed along direction D3. Each high-resistivity block 94L has a short side and a long side, which are located between the doped nitrogen-based semiconductor layer 32H and the electrode 22. Specifically, viewed from a top view of the semiconductor device 1L, each high-resistivity block 94L is trapezoidal.

[0149] Regarding semiconductor devices 1J, 1K, and 1L, the high-resistivity blocks 94J / 94K / 94L are separated from each other, and their total resistance can be reduced.

[0150] In the fabrication of semiconductor devices 1J, 1K, and 1L, the mask layer used in the ion implantation process has multiple separate openings (OPs) to expose multiple portions of the underlying nitrogen-based semiconductor layer (e.g., a barrier layer). In the top view of the corresponding semiconductor device, the shape of the high-resistivity block can be determined by the shape of the openings (OPs).

[0151] Figure 16 This is a vertical cross-sectional view of a semiconductor device 1M according to some embodiments of the present invention. The semiconductor device 1M is similar to... Figure 10A The semiconductor device 1H described and shown differs in that it omits dielectric layers 50 and 52.

[0152] Since these dielectric layers are omitted, dielectric layer 54M directly covers the gate electrode. Dielectric layer 54M can form an interface with gate electrode 34. Negatively charged ions 92 are embedded in nitrogen-based semiconductor layer 16M to form high-resistivity block 94M. High-resistivity block 94M is located above nitrogen-based semiconductor layer 14M.

[0153] A field plate 99 is disposed on dielectric layer 54M. Field plate 99 is conformal to dielectric layer 54M. Field plate 99 has a stepped profile. The left end portion E1 of field plate 99 is located directly above gate electrode 34. The right end portion of field plate 99 is located directly above high-resistance block 94M. By omitting dielectric layers 50 and 52, the thickness of semiconductor device 1H can be reduced.

[0154] refer to Figure 17A A buffer layer 12 and nitrogen-based semiconductor layers 14M and 16M are formed on the substrate 10. A high-resistivity block 94M is formed in the nitrogen-based semiconductor layer 16M. A doped nitrogen-based semiconductor layer 32 and a gate electrode 34 are formed on the nitrogen-based semiconductor layer 16M.

[0155] refer to Figure 17B A dielectric layer 54M is formed on the nitrogen-based semiconductor layer 16M to cover the doped nitrogen-based semiconductor layer 32 and the gate electrode 34. A field blanket 99' is formed on the dielectric layer 54M.

[0156] refer to Figure 17C A mask layer ML5 is formed on the field blanket cladding 99'. The left portion of the mask layer ML5 is located directly above the gate electrode 34. The right portion of the mask layer ML5 is located directly above the high-resistivity block 94M.

[0157] refer to Figure 17D A patterning process is performed on the field plate blanket coating 99' to form the field plate 99. The patterning process is performed using a mask layer ML5. After the patterning process, the mask layer ML5 can be removed from the field plate 99.

[0158] Based on the above description, in embodiments of the present invention, the doping position of negatively charged ions in the barrier layer is determined according to the position of the gate electrode or a single field plate; therefore, the electrical performance of the semiconductor device can be further improved without using any field plate or using only a single field plate. Thus, the semiconductor device can have excellent electrical performance and reliability.

[0159] The above description of the present invention is provided for illustrative and descriptive purposes. The invention is not intended to be exhaustive or to limit itself to the precise forms disclosed above. It is intended to be exhaustive or limited to the precise forms disclosed. It will be apparent to those skilled in the art that many modifications and variations are possible.

[0160] Terms used herein, unless otherwise defined, such as “substantially,” “materially,” “approximately,” and “about,” are used to describe and explain small variations. When used with an event or condition, a term may include examples where the event or condition has occurred precisely, and examples where the event or condition has occurred approximately. For example, when used with a numerical value, a term may include a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” may refer to two surfaces located along the same plane within a few micrometers (μm), such as within 40 micrometers (μm), within 30 μm, within 20 μm, within 10 μm, or within 1 μm.

[0161] As used herein, unless the context clearly specifies otherwise, the singular terms “single,” “an,” and “the single” may include plural references. In the description of some embodiments, the provided component “above” or “on top of” another group of components may include situations where the preceding group of components is directly on the following group of components (e.g., in physical contact with the following group of components), and situations where one or more intervening components are located between the preceding and following group of components.

[0162] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not intended to be limiting. Those skilled in the art will understand that various modifications and substitutions can be made to equivalents without departing from the true spirit and scope of the invention as defined in the appended claims. The drawings are not necessarily drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the processes presented in this disclosure and actual apparatus. Other embodiments of the invention may not be specifically described. The specification and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the purpose, spirit, and scope of the invention. All such modifications will fall within the scope of the appended claims. Although the methods disclosed herein are described by performing specific operations in a specific order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of these operations are not limited.

Claims

1. A semiconductor device, characterized in that, include: First nitrogen-based semiconductor layer; A second nitrogen-based semiconductor layer is disposed on the first nitrogen-based semiconductor layer, and has a band gap larger than that of the first nitrogen-based semiconductor layer, so as to form a heterojunction with a two-dimensional electron gas (2DEG) region therebetween; A gate electrode is disposed on the second nitrogen-based semiconductor layer; as well as A source electrode and a drain electrode are disposed on the second nitrogen-based semiconductor layer, wherein the gate electrode is located between the source electrode and the drain electrode to define a drift region between the gate electrode and the drain electrode; as well as A group of negatively charged ions is injected into the drift region and above the 2DEG region, spaced apart from the gate electrode and the drain electrode, and separated from the region directly below the gate electrode and the drain electrode, wherein the gate electrode is closer to the negatively charged ions than the drain electrode, such that the negatively charged ions deplete at least a portion of the 2DEG region near the gate electrode. The distribution of the negatively charged ions along the thickness direction of the second nitrogen-based semiconductor layer is a normal distribution.

2. The semiconductor device according to claim 1, characterized in that, The gate electrode, the source electrode, and the drain electrode extend in one direction, and the negatively charged ions are distributed along the direction to form a high-resistivity strip in the drift region.

3. The semiconductor device according to claim 1, characterized in that, Also includes: A doped nitrogen-based semiconductor layer is disposed between the second nitrogen-based semiconductor layer and the gate electrode, and is separated from the negatively charged ions.

4. The semiconductor device according to claim 1, characterized in that, The gate electrode, the source electrode, and the drain electrode extend in one direction, and the negatively charged ions are distributed along the direction to form multiple high-resistivity blocks in the drift region.

5. The semiconductor device according to claim 4, characterized in that, Each of the high-resistivity blocks is trapezoidal.

6. The semiconductor device according to claim 4, characterized in that, Each of the high-resistivity blocks has a short side and a long side, wherein the long side is between the short side and the drain electrode.

7. The semiconductor device according to claim 1, characterized in that, The negatively charged ions are distributed from the upper surface of the second nitrogen-based semiconductor layer to the lower surface of the second nitrogen-based semiconductor layer.

8. The semiconductor device according to claim 7, characterized in that, The distribution density of the negatively charged ions varies from the upper surface to the lower surface of the second nitrogen-based semiconductor layer.

9. The semiconductor device according to claim 1, characterized in that, The negatively charged ions are separated from the upper and lower surfaces of the second nitrogen-based semiconductor layer.

10. The semiconductor device according to claim 1, characterized in that, Also includes: A dielectric layer covers the gate electrode and the second nitrogen-based semiconductor layer, wherein the negatively charged ions are adjacent to an interface formed between the second nitrogen-based semiconductor layer and the dielectric layer, and the source electrode and the drain electrode penetrate the dielectric layer to contact the second nitrogen-based semiconductor layer.

11. The semiconductor device according to claim 1, characterized in that, The semiconductor device mentioned above does not include the field plate.

12. The semiconductor device according to claim 1, characterized in that, The negatively charged ions mentioned therein are dopants selected from the highly electronegative element group.

13. The semiconductor device according to claim 1, characterized in that, The negatively charged ions mentioned therein include fluorine.

14. A method for manufacturing a semiconductor device, characterized in that, include: Forming the first nitrogen-based semiconductor layer; A second nitrogen-based semiconductor layer is formed on the first nitrogen-based semiconductor layer; A doped nitrogen-based semiconductor blanket layer is formed on the second nitrogen-based semiconductor layer; A mask having at least one opening is formed on the doped nitrogen-based semiconductor blanket to expose at least a portion of the doped nitrogen-based semiconductor blanket; An ion implantation process is performed using negatively charged ions to distribute the negatively charged ions in the exposed portion of the doped nitrogen-based semiconductor blanket layer and in a portion of the second nitrogen-based semiconductor layer beneath the exposed portion of the doped nitrogen-based semiconductor blanket layer; Remove the mask from the doped nitrogen-based semiconductor blanket coating; as well as The doped nitrogen-based semiconductor blanket layer is patterned to remove the exposed portion of the doped nitrogen-based semiconductor blanket layer, thereby forming a doped nitrogen-based semiconductor layer; The distribution of the negatively charged ions along the thickness direction of the second nitrogen-based semiconductor layer is a normal distribution.

15. The method according to claim 14, characterized in that, Also includes: A gate electrode layer is formed on the doped nitrogen-based semiconductor layer and is separated from the negatively charged ions.

16. The method according to claim 14, characterized in that, The doped nitrogen-based semiconductor blanket layer is patterned to separate the formed doped nitrogen-based semiconductor layer from the negatively charged ions.

17. The method according to claim 14, characterized in that, The opening of the mask is strip-shaped.

18. The method according to claim 14, characterized in that, The mask has multiple openings to expose the doped nitrogen-based semiconductor blanket coating.

19. A semiconductor device, characterized in that, include: First nitrogen-based semiconductor layer; A second nitrogen-based semiconductor layer is disposed on the first nitrogen-based semiconductor layer, and has a band gap larger than that of the first nitrogen-based semiconductor layer; At least one high-resistance block, the high-resistance block being formed by a group of negatively charged ions and embedded in the second nitrogen-based semiconductor layer; The source electrode and drain electrode are disposed above the second nitrogen-based semiconductor layer and separated from the high-resistivity block; A gate electrode is disposed on the second nitrogen-based semiconductor layer and between the source electrode and the drain electrode, wherein the gate electrode is vertically and horizontally separated from the high-resistivity block; and A doped nitrogen-based semiconductor layer is disposed between the second nitrogen-based semiconductor layer and the gate electrode, and is perpendicularly separated from the high-resistivity block; The distribution of the negatively charged ions along the thickness direction of the second nitrogen-based semiconductor layer is a normal distribution.

20. The semiconductor device according to claim 19, characterized in that, The high-resistance block, the gate electrode, the source electrode, and the drain electrode extend in the same direction.

21. The semiconductor device according to claim 19, characterized in that, The gate electrode, the source electrode, and the drain electrode extend in the same direction, and a plurality of the high-resistivity blocks are arranged along the direction.

22. The semiconductor device according to claim 19, characterized in that, Also includes: A dielectric layer covering the gate electrode and the second nitrogen-based semiconductor layer, wherein a high-resistivity block is adjacent to an interface formed between the second nitrogen-based semiconductor layer and the dielectric layer, wherein the distribution density of negatively charged ions in the high-resistivity block varies along a direction from the dielectric layer to the second nitrogen-based semiconductor layer.

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