Micro-nano multi-port ion grid dielectric synapse transistor and preparation method thereof

Abstract

The application relates to the field of transistor technology, in particular to a micro-nano multi-port ion gate dielectric synapse transistor and a preparation method thereof, which comprises a conductive layer of indium tin oxide, an amorphous indium gallium zinc oxide metal oxide channel layer and an ion gate dielectric gel layer, and adopts a coplanar structure design; wherein the main gates G1, G2, G3 and G4 of the synapse transistor are multi-port signal input ends and are used for simulating the presynaptic membrane of a biological synapse; the conductance between the source and the drain is used for simulating the synaptic weight of a biological synapse; and the side gate modulation end is used for simulating the modulation function of a biological descending pathway on the nervous system. The application is aimed at the problems of insufficient computing power in emerging fields such as neural prostheses, brain-computer interfaces and neural robots, and a novel micro-nano multi-port ion gate dielectric synapse transistor device is designed, which is mainly used for realizing real-time processing of multi-analog state neural signals in microelectronics, so as to improve the overall output transmission, computing and storage capacity.

Description

Technical Field

[0001] This invention relates to the field of transistor technology, and in particular to a micro / nano multi-port ion-gate dielectric synaptic transistor and its fabrication method. Background Technology

[0002] Compared to traditional intelligent systems using the von Neumann architecture, the human sensory nervous system possesses more powerful data parallel processing capabilities and integrates storage and computation in its sensory information processing functions. When dealing with real-time big data streams, it demonstrates advantages such as fault tolerance, energy efficiency, robustness, and event-driven processing, attracting widespread attention from the academic community in recent years. By drawing inspiration from and simulating the working modes of biological nervous systems, we can fabricate integrated electronic devices with similar functions—mimicking sensory neurons—and apply them to future intelligent devices. This would enable timely and efficient perception and processing of environmental information in the real world, effectively avoiding the "von Neumann bottleneck" encountered by traditional electronic devices. Therefore, conducting comprehensive research on biomimetic nervous systems and exploring their integration with intelligent electronic devices will have significant research and potential industrialization implications for the development of next-generation neural prostheses, human-machine interfaces, and humanoid robots.

[0003] Synapses are the interconnected structures between neurons, playing a crucial role in biological sensory systems. Adjustable synaptic weights are fundamental to realizing signal processing in biological sensing. In recent years, scientists have focused on developing biomimetic neural systems based on synaptic devices. Various electronic devices are currently used to construct artificial synapses. Two-terminal memristors and multi-terminal synaptic transistors are two main types of synaptic devices. Synaptic transistors, in particular, can achieve parallel learning and are more likely to realize advanced synaptic functions. The ion migration process of electrically double-layered synaptic transistors is very similar to that of biological synapses. These advantages make them ideal data processing nodes for developing biomimetic sensory systems, thus the development of this type of neuromorphic device has received widespread attention. Summary of the Invention

[0004] To address the shortcomings of existing algorithms, this invention addresses the problem of insufficient computing power in emerging fields such as neuroprosthetics, brain-computer interfaces, and neurorobotics. It designs a novel micro / nano multi-port ion-gate dielectric synaptic transistor device, which is mainly used in microelectronics to realize real-time processing of multi-analog neural signals, thereby improving the overall output transmission, computing, and storage capabilities.

[0005] The technical solution adopted in this invention is: a micro / nano multi-port ion-gate dielectric synaptic transistor, comprising: an indium tin oxide conductive layer, an amorphous indium gallium zinc oxide metal oxide channel layer, and an ion-gate dielectric gel layer, wherein the transistor adopts a coplanar structure design; wherein, the main gate G1, G2, G3, and G4 of the synaptic transistor are multi-port signal input terminals used to simulate the presynaptic membrane of a biological synapse; the conductivity between the source and drain is used to simulate the synaptic weight of a biological synapse; and the side gate modulation terminal is used to simulate the modulation function of the descending biological pathway on the nervous system.

[0006] The fabrication method of micro / nano multi-port ion-gate dielectric synaptic transistors includes:

[0007] Step 1: Initially, IGZO is deposited on a silicon oxide wafer using a patterned deposition method with the aid of a metal mask via magnetron sputtering to form the channel layer of the synaptic transistor.

[0008] Furthermore, the initial parameters for magnetron sputtering were set to argon atmosphere, sputtering power of 100W, and cavity working pressure of 0.5Pa.

[0009] Step 2: ITO is deposited again on the semi-finished product from Step 1 by magnetron sputtering with the help of a metal mask to form an electrode layer.

[0010] Furthermore, the parameters for magnetron sputtering were again set to an argon atmosphere with a cavity working pressure of 0.8 Pa.

[0011] Step 3: Perform annealing to achieve better ohmic contact between the two layers of material;

[0012] Furthermore, the annealing temperature was set to 300 degrees Celsius for 3 hours;

[0013] Step 4: Using the dispensing function of a microelectronic inkjet printer, print the grid medium directly onto the semi-finished product after step 3 in a patterned manner.

[0014] Furthermore, the specific materials used in inkjet printing are: an organic mixture of ionic liquid, photoinitiator HOMPP, and polymer PEGDA.

[0015] Step 5: Irradiate the semi-finished product prepared in Step 4 in an ultraviolet curing chamber. The polymer top gate dielectric will cross-link under ultraviolet light, thus obtaining a novel synaptic transistor.

[0016] The beneficial effects of this invention are:

[0017] 1. Synaptic transistors are based on the double-layer effect of ion gels. Compared with traditional transistors, they have ultra-large gate capacitance at the μF / cm-2 level, high carrier density and low power consumption.

[0018] 2. Enables response testing to various single / multi-pulse excitation signals and simulates various neural synaptic behaviors, such as postsynaptic excitation current, double-pulse facilitation, and post-tetanic enhancement.

[0019] 3. The channel layer of the synaptic transistor can respond to light and electrical stimulation, and can be applied to different application scenarios;

[0020] 4. The structure of covering the top of the device with the gate dielectric can isolate environmental interference and greatly enhance the stability and lifespan of the synaptic transistor.

[0021] 5. The fabrication process of synaptic transistors can realize large-scale wafer-level transistor fabrication and is compatible with traditional transistor fabrication processes. Attached Figure Description

[0022] Figure 1 This is a top view of the internal structure of the synaptic transistor of the present invention;

[0023] Figure 2 This is a side view of the internal structure of the synaptic transistor of the present invention;

[0024] Figure 3 This is a schematic diagram of the double-layer effect of the present invention. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments. The drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0026] like Figure 1 , 2 As shown, a micro / nano multi-port ion-gate dielectric synaptic transistor includes: an indium tin oxide (ITO) conductive layer, an amorphous indium gallium zinc oxide (a-IGZO) metal oxide channel layer, and an ion-gate dielectric gel layer. The overall transistor adopts a coplanar structure design. Among them, the main gate (G1, G2, G3, G4) of the synaptic transistor is the multi-port signal input terminal of the transistor, which is used to simulate the presynaptic membrane of biological synapses. The conductance between the source (S) and the drain (D) is used to simulate the synaptic weight of biological synapses. The side gate modulation terminal (Gm) is used to simulate the modulation function of the descending biological pathway on the nervous system.

[0027] The novel coplanar multi-gate input structure of the present invention, compared with the stacked structure of traditional transistor devices, has each electrode and the channel layer on the same horizontal plane, which is beneficial for signal input integration and modulation by means of the lateral ion coupling mechanism of the ion medium. In addition, the fact that each electrode and the channel layer are on the same horizontal plane will greatly simplify the complexity of the packaging process.

[0028] Ion-gate dielectric synaptic transistors are primarily based on the double-layer effect generated by ion-gel gate dielectrics, enabling advanced ultra-low operating voltages (below 1V) and neuromorphic computing capabilities; such as... Figure 3 As shown, the specific process of the electric double layer effect is depicted. Under the drive of an applied electric field, the cations and anions contained in the ion gate dielectric layer rapidly and gradually migrate to the interface, eventually forming a dense electric double layer with spacing only on the nanometer scale at the channel / electrolyte and gate / dielectric interfaces, and generating μF / cm -2 Large gate capacitors at the level of [unspecified] reduce overall device power consumption.

[0029] In use, ports G1, G2, G3, and G4 can be selected individually or in multiples, and positive mimicry neural voltage pulse sequences can be applied individually or simultaneously. By utilizing the side-gate coupling characteristics of the solid-state ion gate medium, comprehensive processing and analysis of the data stream can be performed. Under the influence of a positive voltage pulse, cations in the ion gate medium migrate to the channel, inducing an excitatory postsynaptic current (EPSC) in the channel. When the voltage pulse is removed, the induced ions will move in the opposite direction and return to the initial state. At this time, the channel current will still act on the ions that have not been fully reset, and the EPSC signal will slowly decrease.

[0030] In addition, during use, positive or negative constant voltage signals can be applied to the Gm port simultaneously to enhance or suppress the overall output characteristics of the device. For example, under the action of positive voltage, more charge carriers will be induced in the channel, thereby improving the output signal of the device, while negative voltage will have the opposite effect.

[0031] Under the influence of multiple voltage pulses, after the excitatory synaptic current generated by the first pulse, the cations and anions at the gate / channel interface and the gate / gate dielectric will gradually drift back to their equilibrium state. If the next voltage pulse arrives during this process, some of the ions that have not returned will overlap with the number of ions excited in this instance, inducing more charge carriers in the channel. This results in a stronger excitatory postsynaptic current triggered in this instance, leading to phenomena such as double-pulse facilitation.

[0032] When a neural pulse sequence is input using multiple signal input terminals, a nonlinear superposition effect occurs, resulting in a final data output value that is much larger than the linear value obtained by applying signals individually to each signal input terminal. Therefore, ion-gate dielectric synaptic transistors are more suitable for neuromorphic computing.

[0033] The fabrication method of micro / nano multi-port ion-gate dielectric synaptic transistors includes:

[0034] Step 1: Initially, IGZO is deposited on a silicon oxide wafer using a patterned deposition method with the aid of a metal mask via magnetron sputtering to form the channel layer of the synaptic transistor.

[0035] The magnetron sputtering parameters were set to argon atmosphere, sputtering power of 100W, and chamber working pressure of 0.5Pa.

[0036] Step 2: ITO is deposited again on the semi-finished product from Step 1 by magnetron sputtering with the help of a metal mask to form an electrode layer.

[0037] The magnetron sputtering parameters were set to an argon atmosphere and a chamber working pressure of 0.8 Pa.

[0038] Step 3: Perform annealing to achieve better ohmic contact between the two layers of material;

[0039] The temperature was set to 300 degrees Celsius, and the duration was 3 hours.

[0040] Step 4: Using the dispensing function of a microelectronic inkjet printer, print the grid medium directly onto the semi-finished product after step 3 in a patterned manner.

[0041] The specific materials used in this step are an organic mixture of ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(tri-fluoromethylsulfonyl)imide), photoinitiator HOMPP (2-hydroxy-2-methyl-propiophenone), and polymer PEGDA (polyethylene glycol diacrylate).

[0042] Step 5: Irradiate the semi-finished product prepared in Step 4 in an ultraviolet curing chamber. The polymer top gate dielectric will cross-link under ultraviolet light, thus obtaining a novel synaptic transistor.

[0043] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A micro / nano multi-port ion-gate dielectric synaptic transistor, characterized in that, include: The transistor is designed with a coplanar structure, consisting of an indium tin oxide conductive layer, an amorphous indium gallium zinc oxide metal oxide channel layer, a main gate and a side gate modulation terminal, all disposed on the same horizontal plane, and an ion gate dielectric gel layer covering the conductive layer, the channel layer, the main gate and the side gate modulation terminal. The main gates G1, G2, G3, and G4 of the synaptic transistor are multi-port signal input terminals used to simulate the presynaptic membrane of a biological synapse. The conductance between the source and drain is used to simulate the synaptic weight of a biological synapse. The side gate modulation terminal is used to simulate the modulation function of the descending biological pathway on the nervous system.

2. The fabrication method of the micro / nano multi-port ion-gate dielectric synaptic transistor according to claim 1, characterized in that, Includes the following steps: Step 1: Initially, IGZO is deposited on a silicon oxide wafer using a patterned deposition method with the aid of a metal mask via magnetron sputtering to form the channel layer of the synaptic transistor. Step 2: ITO is deposited again on the semi-finished product from Step 1 by magnetron sputtering with the help of a metal mask to form an electrode layer. Step 3: Perform annealing to achieve better ohmic contact between the two layers of material; Step 4: Using the dispensing function of a microelectronic inkjet printer, the grid medium is patterned and printed directly onto the semi-finished product after step 3; the specific inkjet material is an organic mixture of ionic liquid, photoinitiator HOMPP, and polymer PEGDA. Step 5: Irradiate the semi-finished product prepared in Step 4 in an ultraviolet curing chamber. The polymer top gate dielectric will cross-link under ultraviolet light, thus obtaining a novel synaptic transistor.

3. The method for fabricating a micro / nano multi-port ion-gate dielectric synaptic transistor according to claim 2, characterized in that, The initial parameters for magnetron sputtering were set to argon atmosphere, sputtering power of 100 W, and chamber working pressure of 0.5 Pa.

4. The method for fabricating a micro / nano multi-port ion-gate dielectric synaptic transistor according to claim 2, characterized in that: The parameters for magnetron sputtering were again set to an argon atmosphere with a chamber working pressure of 0.8 Pa.

5. The method for fabricating a micro / nano multi-port ion-gate dielectric synaptic transistor according to claim 2, characterized in that: The annealing temperature was set to 300 degrees Celsius for 3 hours.

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