LDO regulator short protection circuit preventing false triggering

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a short-circuit protection circuit of an LDO voltage stabilizer. The short-circuit protection circuit of the LDO voltage stabilizer for preventing mis-triggering comprises a power output circuit having a power tube, a first resistor and a second resistor, the drain of the power tube serving as a voltage output end, and the source being connected to a power input end; further comprising: a voltage stabilizing circuit, a driving output end of which is connected to the gate of the power tube; a delay circuit, which outputs a delay control signal; and a short-circuit protection circuit, which receives the delay control signal, detects whether the output current of the power tube reaches a preset value, and if so, delays to detect again when the output current of the power tube reaches the preset value, and then closes the output of the power tube. The application adopts a pure analog circuit design, provides a brand-new control mode of the short-circuit protection circuit, omits the digital logic part and the clock circuit inside the chip, and simplifies the circuit structure.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a short-circuit protection circuit for an LDO regulator. Background Technology

[0002] An LDO (Linear Regulator) is a type of voltage regulator. An LDO step-down system subtracts excess voltage from the applied input voltage to produce a regulated output voltage. In practical applications, it is characterized by its small size and the need for fewer external components. For example... Figure 1 The diagram shows an LDO chip application circuit with built-in power transistors and voltage divider resistors. It only requires additional input capacitor C1 and output capacitor C2 to achieve step-down output, where 10 is an LDO step-down chip.

[0003] Because the power transistor in an LDO chip operates in the saturation region, meaning the voltage loss in the buck converter is entirely borne by the internal power transistor, when a short circuit occurs, the voltage drop across the power transistor becomes the system input voltage. If the power transistor's power is too high and the system operates in this state for an extended period, the power transistor will overheat and fail, causing the entire system to fail. Therefore, the short-circuit protection circuit of the LDO chip is crucial. In practical applications, LDOs are often used as power supply modules for MCU chips. While the MCU chip consumes very little power in standby mode, a large transient current will pull down the LDO's output voltage when it is woken up. This increases the output current of the internal power transistor, triggering the internal short-circuit protection circuit. In the LDO chip circuit design, the short-circuit protection signal needs to be shielded for a period of time to ensure that, in the aforementioned application scenarios, the LDO buck system does not mistakenly trigger the short-circuit protection, causing the system output voltage to drop and resulting in system failure.

[0004] The current common practice is to use digital circuit frequency division timing to generate this delay signal. This approach involves a large circuit scale, requiring the internal design of an OSC circuit to generate the clock frequency, which increases the circuit scale of the LDO chip and the internal static power consumption of the chip. Summary of the Invention

[0005] This invention addresses the technical problem of the lack of a low-power and simple delay circuit in the prior art to shield short-circuit protection signals, and aims to provide a short-circuit protection circuit for LDO regulators to prevent false triggering.

[0006] A short-circuit protection circuit for an LDO regulator to prevent false triggering includes a power output circuit with a power transistor, a first resistor and a second resistor for voltage division. The drain of the power transistor serves as the voltage output terminal, and the source is connected to the power input terminal. The first resistor and the second resistor are connected in series. The other end of the first resistor is connected to the voltage output terminal, and the other end of the second resistor is grounded.

[0007] Also includes:

[0008] A voltage regulator circuit, whose output terminal is connected to the gate of the power transistor;

[0009] A delay circuit outputs a delay control signal;

[0010] A short-circuit protection circuit receives the delay control signal, detects whether the output current of the power transistor reaches a preset value, and if it does, after a delay, detects again that the output current of the power transistor has reached the preset value, and then shuts off the output of the power transistor.

[0011] As a preferred embodiment, the power transistor is a PMOS transistor.

[0012] As a preferred embodiment, the delay circuit includes:

[0013] The first MOSFET has its source connected to the power input terminal;

[0014] A second MOS transistor has its gate connected to its drain, its drain connected to the drain of the first MOS transistor, and its source grounded.

[0015] A third MOSFET, with its drain connected to the gate of the first MOSFET and its source connected to the power input terminal;

[0016] A fourth MOSFET, whose gate is connected to the gate of the second MOSFET, and whose source is grounded;

[0017] A fifth MOS transistor, with its drain connected to the gate of the third MOS transistor and its source connected to the power input terminal;

[0018] A sixth MOS transistor, with its drain connected to the drain of the fifth MOS transistor and its source grounded;

[0019] A seventh MOS transistor outputs a delay control signal at its gate, and its drain is connected to the drain of the fourth MOS transistor, the gate of the fifth MOS transistor, and the gate of the sixth MOS transistor, respectively. Its source is connected to the power input terminal.

[0020] An eighth MOS transistor has its gate connected to the current mirror bias voltage, its drain connected to the drain of the seventh MOS transistor, and its source grounded.

[0021] A third capacitor has one end connected to the common terminal between the drain of the seventh MOS transistor and the drain of the eighth MOS transistor, and the other end grounded.

[0022] As a preferred embodiment, the first MOS transistor, the third MOS transistor, the fifth MOS transistor, and the seventh MOS transistor are all PMOS transistors;

[0023] The second MOS transistor, the fourth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are all NMOS transistors.

[0024] As a preferred embodiment, the short-circuit protection circuit includes a sampling circuit and a comparator circuit;

[0025] The sampling circuit includes:

[0026] A sampling transistor, with its gate connected to the gate of the power transistor and its source connected to the power input terminal;

[0027] A switching transistor, with its gate connected to the voltage output terminal, its drain connected to the drain of the sampling transistor, and its source grounded;

[0028] A third resistor is connected at one end to the drain of the sampling tube and at the other end to ground. The common terminal between the third resistor and the drain of the sampling tube generates a comparison signal.

[0029] The comparator circuit includes:

[0030] A ninth MOS transistor, with its gate connected to its drain, its source connected to the power input terminal, and its drain connected to the output terminal of the delay circuit;

[0031] The tenth MOS transistor has its gate connected to the reference voltage and its drain connected to the drain of the ninth MOS transistor.

[0032] The eleventh MOS transistor has its gate connected to the current mirror bias voltage, its drain connected to the source of the tenth MOS transistor, and its source grounded.

[0033] A twelfth MOS transistor, whose gate is connected to the gate of the ninth MOS transistor, and whose source is connected to the power input terminal;

[0034] A thirteenth MOS transistor, with its gate connected to the comparison signal, its drain connected to the drain of the twelfth MOS transistor, and its source connected to the drain of the eleventh MOS transistor;

[0035] The fourteenth MOSFET has its gate connected to the drain of the twelfth MOSFET, the drain connected to the gate of the power transistor, and its source connected to the power input terminal.

[0036] As a preferred embodiment, the sampling transistor, the ninth MOS transistor, the twelfth MOS transistor, and the fourteenth MOS transistor are all PMOS transistors;

[0037] The switching transistor, the tenth MOS transistor, the eleventh MOS transistor, and the thirteenth MOS transistor are all NMOS transistors.

[0038] As a preferred embodiment, the charging current of the ninth MOS transistor is greater than the discharging current of the eighth MOS transistor.

[0039] As a preferred embodiment, the voltage regulator circuit includes:

[0040] The fifteenth MOSFET has its source connected to the power input terminal;

[0041] The sixteenth MOS transistor has its gate connected to the reference voltage and its drain connected to the drain of the fifteenth MOS transistor.

[0042] The seventeenth MOS transistor has its gate connected to the current mirror bias voltage, its drain connected to the source of the sixteenth MOS transistor, and its source grounded.

[0043] The eighteenth MOS transistor has its gate connected to the gate of the fifteenth MOS transistor, and its gate is also connected to the drain. Its source is connected to the power input terminal.

[0044] The nineteenth MOS transistor has its gate connected to the common terminal of the first and second resistors, its drain connected to the drain of the eighteenth MOS transistor, and its source connected to the drain of the seventeenth MOS transistor.

[0045] The common terminal between the drain of the fifteenth MOS transistor and the drain of the sixteenth MOS transistor serves as the drive output terminal of the voltage regulator circuit.

[0046] As a preferred embodiment, both the fifteenth MOS transistor and the eighteenth MOS transistor are PMOS transistors;

[0047] The sixteenth MOS transistor, the seventeenth MOS transistor, and the nineteenth MOS transistor are all NMOS transistors.

[0048] As a preferred embodiment, the LDO regulator short-circuit protection circuit for preventing false triggering further includes:

[0049] A reference circuit that outputs a reference voltage and a current mirror bias voltage.

[0050] The positive and progressive effects of this invention are as follows: This invention employs a short-circuit protection circuit for LDO regulators to prevent false triggering, which has the following advantages:

[0051] 1. It adopts a pure analog circuit design, providing a brand-new control mode for short-circuit protection circuits, eliminating the digital logic part and the internal clock circuit of the chip, thus simplifying the circuit structure.

[0052] 2. It has the advantages of low cost, low power consumption, small size and high reliability, and is suitable for some small-size and low-cost LDO step-down systems. Attached Figure Description

[0053] Figure 1 This is an example of an LDO chip application circuit in the prior art;

[0054] Figure 2 This is a structural block diagram of the present invention;

[0055] Figure 3 This is a circuit diagram of the present invention;

[0056] Figure 4 This is a simulation waveform diagram of a load power-on according to the present invention;

[0057] Figure 5 This is a simulation waveform diagram of short-circuit recovery according to the present invention. Detailed Implementation

[0058] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to specific illustrations.

[0059] Reference Figure 2 A short-circuit protection circuit for an LDO regulator to prevent false triggering includes a power output circuit 105. The power output circuit 105 has a power transistor PM1, a first resistor R1, and a second resistor R2 for voltage division. The drain of the power transistor PM1 serves as the voltage output terminal VOUT, and the source of the power transistor PM1 is connected to the power input terminal VIN. The first resistor R1 and the second resistor R2 are connected in series as sampling resistors. The other end of the first resistor R1 is connected to the voltage output terminal VOUT, and the other end of the second resistor R2 is grounded. The common terminal between the first resistor R1 and the second resistor R2 serves as the FB signal (feedback signal).

[0060] The short-circuit protection circuit for the LDO regulator to prevent false triggering also includes a voltage regulator circuit 102, a short-circuit protection circuit 103, and a delay circuit 104.

[0061] The drive output terminal DRIVE of the voltage regulator circuit 102 is connected to the gate of the power transistor PM1, and the voltage regulator circuit 102 serves as the drive circuit for the power transistor PM1.

[0062] The short-circuit protection circuit 103 detects whether the output current of power transistor PM1 reaches a preset value. If it does, it delays and detects again that the output current of power transistor PM1 has reached the preset value, then shuts off the output of power transistor PM1. When the output of power transistor PM1 is pulled low, the short-circuit protection circuit 103 starts working. When the system output is pulled low, it controls the internal switching transistor to pull up the DRIVE signal through the OFF signal provided by the delay circuit 104 to shut down the power transistor output, thereby achieving the function of short-circuit protection.

[0063] The delay circuit 104 outputs a delay control signal (OFF signal). Its function is to delay the control signal for a fixed time when there is a transient large current output at the load end, the voltage output terminal VOUT is pulled low, and the short-circuit protection circuit 103 starts working. When the system output current reaches a preset value (the set current limiting protection point, i.e., when the OCP signal voltage is higher than VREF), the OFF signal level remains unchanged during the delay period, and the power transistor PM1 cannot be turned off. After the delay ends, the delay circuit 104 does not control the OFF signal. At this time, the short-circuit protection circuit 103 can normally control the switching of the power transistor PM1. When the output current of the power transistor PM1 triggers the preset value set by the system, the short-circuit protection circuit 103 will turn off the output of the power transistor PM1.

[0064] In some embodiments, the power transistor PM1 is a PMOS transistor.

[0065] In some embodiments, refer to Figure 2 and Figure 3 The voltage regulator circuit 102 includes a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, an eighteenth MOSFET M18, and a nineteenth MOSFET M19.

[0066] The gate of the fifteenth MOSFET M15 is connected to the gate of the eighteenth MOSFET M18, the drain of the fifteenth MOSFET M15 is connected to the drain of the sixteenth MOSFET M16, and the source of the fifteenth MOSFET M15 is connected to the power input terminal VIN. The common terminal between the drains of the fifteenth MOSFET M15 and the sixteenth MOSFET M16 serves as the drive output terminal DRIVE of the voltage regulator circuit 102.

[0067] The gate of the sixteenth MOSFET M16 is connected to the reference voltage VREF, the drain of the sixteenth MOSFET M16 is connected to the drain of the fifteenth MOSFET M15, and the source of the sixteenth MOSFET M16 is connected to the drain of the seventeenth MOSFET M17.

[0068] The gate of the seventeenth MOSFET M17 is connected to the current mirror bias voltage VG. The drain of the seventeenth MOSFET M17 is connected to the source of the sixteenth MOSFET M16 and the source of the nineteenth MOSFET M19, respectively. The source of the seventeenth MOSFET M17 is grounded.

[0069] The gate of the eighteenth MOSFET M18 is connected to the gate of the fifteenth MOSFET M15. The gate of the eighteenth MOSFET M18 is also connected to its drain. The drain of the eighteenth MOSFET M18 is connected to the drain of the nineteenth MOSFET M19. The source of the eighteenth MOSFET M18 is connected to the power input terminal VIN.

[0070] The gate of the nineteenth MOSFET M19 is connected to the common terminal of the first resistor R1 and the second resistor R2. The gate of the nineteenth MOSFET M19 receives the FB signal. The drain of the nineteenth MOSFET M19 is connected to the drain of the eighteenth MOSFET M18. The source of the nineteenth MOSFET M19 is connected to the drain of the seventeenth MOSFET M17.

[0071] The voltage regulator circuit 102 of this invention uses five MOSFETs—M15, M16, M17, M18, and M19—to form an operational amplifier. This amplifier, along with the first resistor R1, the second resistor R2, and the power transistor PM1, forms a negative feedback system. Based on the operational amplifier characteristics, VOUT = VREF * (R1 + R2) / R2. The output voltage VOUT can be adjusted to maintain a fixed proportional relationship with the reference voltage VREF by adjusting the gate-source voltage of the power transistor PM1 in a timely manner.

[0072] In some embodiments, refer to Figure 3 The fifteenth MOSFET M15 and the eighteenth MOSFET M18 are both PMOS transistors. The sixteenth MOSFET M16, the seventeenth MOSFET M17, and the nineteenth MOSFET M19 are all NMOS transistors.

[0073] In some embodiments, refer to Figure 2 and Figure 3 The short-circuit protection circuit 103 includes a sampling circuit 1031 and a comparator circuit 1032.

[0074] The sampling circuit 1031 includes a sampling transistor PM2, a switching transistor M20, and a third resistor R3.

[0075] The gate of sampling transistor PM2 is connected to the gate of power transistor PM1. The drain of sampling transistor PM2 is connected to the drain of switching transistor M20 and one end of the third resistor R3. The source of sampling transistor PM2 is connected to the power input terminal VIN.

[0076] The gate of the switching transistor M20 is connected to the voltage output terminal VOUT, the drain of the switching transistor M20 is connected to the drain of the sampling transistor PM2, and the source of the switching transistor M20 is grounded.

[0077] One end of the third resistor R3 is connected to the drain of the sampling transistor PM2, and the other end of the third resistor R3 is grounded. The common terminal between the third resistor R3 and the drain of the sampling transistor PM2 generates a comparison signal (OCP signal).

[0078] In the sampling circuit 1031, the switching transistor M20 acts as the switch for the sampling circuit. When the system output voltage VOUT is pulled low, the switching transistor M20 is turned off. At this time, the current of the sampling transistor PM2 flows through R3 to generate an OCP signal. The sampling transistor PM2 and the power transistor PM1 have the same gate-source voltage and both operate in the saturation region. Their current magnitude is proportional to their size. In this way, the current limiting trigger point of the entire system, i.e. the preset value, can be set by reasonably setting the resistance value of R1.

[0079] The comparator circuit 1032 includes a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, a twelfth MOSFET M12, a thirteenth MOSFET M13, and a fourteenth MOSFET M14.

[0080] The gate of the ninth MOSFET M9 is connected to its drain, the gate of the twelfth MOSFET M12 is connected to its gate, the drain of the ninth MOSFET M9 is connected to the drain of the tenth MOSFET M10, and the source of the ninth MOSFET M9 is connected to the power input terminal VIN. The drain of the ninth MOSFET M9 is also connected to the output terminal of the delay circuit 104 to receive the delay control signal.

[0081] The gate of the tenth MOSFET M10 is connected to the reference voltage VREF, the drain of the tenth MOSFET M10 is connected to the drain of the ninth MOSFET M9, and the source of the tenth MOSFET M10 is connected to the drain of the eleventh MOSFET M11.

[0082] The gate of the eleventh MOSFET M11 is connected to the current mirror bias voltage VG. The drain of the eleventh MOSFET M11 is connected to the source of the tenth MOSFET M10 and the source of the thirteenth MOSFET M13, respectively. The source of the eleventh MOSFET M11 is grounded.

[0083] The gate of the twelfth MOSFET M12 is connected to the gate of the ninth MOSFET M9, the drain of the twelfth MOSFET M12 is connected to the drain of the thirteenth MOSFET M13, and the source of the twelfth MOSFET M12 is connected to the power input terminal VIN.

[0084] The gate of the thirteenth MOSFET M13 is connected to the comparator signal (OCP signal), the drain of the thirteenth MOSFET M13 is connected to the drain of the twelfth MOSFET M12, and the source of the thirteenth MOSFET M13 is connected to the drain of the eleventh MOSFET M11.

[0085] The gate of the fourteenth MOSFET M14 is connected to the drain of the twelfth MOSFET M12, the drain of the fourteenth MOSFET M14 is connected to the gate of the power transistor PM1, and the source of the fourteenth MOSFET M14 is connected to the power input terminal VIN.

[0086] The comparator circuit 1032 is used to compare the magnitudes of the OCP signal and the VREF signal to determine whether the system output is short-circuited. When the OCP voltage is greater than VREF, short-circuit protection is triggered.

[0087] In some embodiments, refer to Figure 3 Sampling transistor PM2, ninth MOSFET M9, twelfth MOSFET M12, and fourteenth MOSFET M14 are all PMOS transistors. Switching transistors M20, tenth MOSFET M10, eleventh MOSFET M11, and thirteenth MOSFET M13 are all NMOS transistors.

[0088] In some embodiments, refer to Figure 2 and Figure 3 The delay circuit 104 includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, and a third capacitor C3.

[0089] The gate of the first MOSFET M1 is connected to the drain of the third MOSFET M3, the drain of the first MOSFET M1 is connected to the drain of the second MOSFET M2, and the source of the first MOSFET M1 is connected to the power input terminal VIN.

[0090] The gate of the second MOSFET M2 is connected to the drain, and the gate of the second MOSFET M2 is also connected to the gate of the fourth MOSFET M4. The drain of the second MOSFET M2 is connected to the drain of the first MOSFET M1, and the source of the second MOSFET M2 is grounded.

[0091] The gate of the third MOSFET M3 is connected to the drain of the fifth MOSFET M5, the drain of the third MOSFET M3 is connected to the gate of the first MOSFET M1, and the source of the third MOSFET M3 is connected to the power input terminal VIN.

[0092] The gate of the fourth MOSFET M4 is connected to the gate of the second MOSFET M2, the drain of the fourth MOSFET M4 is connected to the drain of the seventh MOSFET M7, and the source of the fourth MOSFET M4 is grounded.

[0093] The gate of the fifth MOSFET M5 is connected to the drain of the seventh MOSFET M7. The drain of the fifth MOSFET M5 is connected to the gate of the third MOSFET M3 and the drain of the sixth MOSFET M6. The source of the fifth MOSFET M5 is connected to the power input terminal VIN.

[0094] The gate of the sixth MOSFET M6 is connected to the drain of the seventh MOSFET M7, the drain of the sixth MOSFET M6 is connected to the drain of the fifth MOSFET M5, and the source of the sixth MOSFET M6 is grounded.

[0095] The gate of the seventh MOSFET M7 is connected to the short-circuit protection circuit 103 as the output terminal of the delay circuit 104. Preferably, as follows: Figure 3 As shown, the gate of the seventh MOSFET M7 is connected to the drain of the ninth MOSFET M9, the drain of the seventh MOSFET M7 is connected to the drain of the fourth MOSFET M4, the gate of the fifth MOSFET M5, and the gate of the sixth MOSFET M6, respectively, and the source of the seventh MOSFET M7 is connected to the power input terminal VIN.

[0096] The gate of the eighth MOSFET M8 is connected to the current mirror bias voltage VG, the drain of the eighth MOSFET M8 is connected to the drain of the seventh MOSFET M7, and the source of the eighth MOSFET M8 is grounded.

[0097] One end of the third capacitor C3 is connected to the common terminal between the drain of the seventh MOSFET M7 and the drain of the eighth MOSFET M8, and the other end of the third capacitor C3 is grounded.

[0098] The delay circuit 104 of this invention provides a delay period after a system short circuit to shield the output of the short-circuit protection circuit 103. When the system is operating normally, VREF is greater than OCP, and the voltage at point A is VIN - 0.7V (approximate value). When the OCP voltage is higher than VREF, the VGS voltage of the thirteenth MOSFET M13 is higher than the VGS voltage of the tenth MOSFET M10. At this time, the tenth MOSFET M10 is in the cutoff region. Due to the short circuit between the drain and source of the ninth MOSFET M9, the voltage at point A is gradually charged up to VIN. At this time, the seventh MOSFET M7 is turned off, and the third capacitor C3 begins to discharge through the current mirror of the eighth MOSFET M8. The voltage at point B decreases. When the voltage at point B decreases to the flip point of the inverter formed by the fifth MOSFET M5 and the sixth MOSFET M6, the voltage at point C changes from low to high. At this time, the third MOSFET M3 is turned off. The OFF signal is controlled only by the comparator circuit 1032. If the current of the system power transistor PM1 is still greater than a preset value, the comparator circuit 1032 shuts off the output of the power transistor PM1.

[0099] After the output of power transistor PM1 is turned off, the OCP signal decreases. When the OCP signal is lower than VREF, power transistor PM1 is turned back on. If the system is still in a short-circuit state at this time, the system will turn off power transistor PM1 again when OCP is greater than VREF. When the short circuit is removed, the system output current decreases, and the OCP signal is lower than VREF. At this time, the current flowing through the eleventh MOSFET M11 is entirely provided by the ninth MOSFET M9. The VGS voltage of the ninth MOSFET M9 is established, and the seventh MOSFET M7 has the same VGS voltage as the ninth MOSFET M9. At this time, the seventh MOSFET M7 begins to charge the third capacitor C3, while the eighth MOSFET M8 can still discharge the third capacitor C3. In practical applications, the current of the ninth MOSFET M9 is equal to the current of the eleventh MOSFET M11 in this operating state. The seventh MOSFET M7 and the ninth MOSFET M9 act as current mirrors to each other, and the recharging time can be determined by adjusting their ratio. In applications, it is necessary to ensure that the charging current of the ninth MOSFET M9 is greater than the discharging current of the eighth MOSFET M8; otherwise, the system will not function properly.

[0100] In some embodiments, refer to Figure 3 The first MOSFET M1, the third MOSFET M3, the fifth MOSFET M5, and the seventh MOSFET M7 are all PMOS transistors. The second MOSFET M2, the fourth MOSFET M4, the sixth MOSFET M6, and the eighth MOSFET M8 are all NMOS transistors.

[0101] In some embodiments, refer to Figure 2 The LDO regulator short-circuit protection circuit 103, which prevents false triggering, also includes a reference circuit 101. The reference circuit 101 outputs a reference voltage VREF and a current mirror bias voltage VG. The reference circuit 101 provides the reference voltage VREF and the current mirror bias voltage VG for the entire chip. The reference circuit of this invention uses a conventional analog circuit in the prior art, which will not be described in detail here.

[0102] Example 1:

[0103] by Figure 3 Taking the circuit diagram as an example, the transient power-on process of the load MCU chip in the LDO system is simulated. The voltage output terminal VOUT of this invention is connected to the input terminal of the load MCU chip for power-on simulation test, such as... Figure 4 As shown in the figure, the voltage output terminals VOUT, B, C, OCP, VREF and the output current IOUT of power transistor PM1 were collected from top to bottom.

[0104] from Figure 4It can be seen that when the OCP signal is higher than VREF, if the third capacitor C3 has not finished discharging and the voltage at point B has not dropped to the inverter signal flip point, the system will not trigger short-circuit protection. After the transient high current ends upon power-on, the system output voltage VOUT returns to normal. This indicates that the circuit of the present invention has an anti-accidental touch function.

[0105] Example 2:

[0106] by Figure 3 Taking the circuit diagram as an example, the transient power-on process of the load MCU chip in the LDO system is simulated. The voltage output terminal VOUT of this invention is connected to the input terminal of the load MCU chip to perform a short-circuit recovery simulation test, such as... Figure 5 As shown in the figure, from top to bottom are the voltage output terminal VOUT, point B, point C, OCP, VREF, and the output current IOUT of power transistor PM1.

[0107] from Figure 5 It can be seen that when the OCP signal is higher than VREF, the third capacitor C3 begins to discharge. When the voltage at point B drops to the inverter signal flip point, the output at point C changes from low to high. At this time, the comparator circuit 1032 can turn off the power transistor PM1. After turning off the power transistor PM1, the IOUT and OCP signals decrease. When IOUT is lower than the system-set protection point, the power transistor PM1 is turned back on. When IOUT is higher than the system-set protection point, the power transistor PM1 is turned off. In the actual circuit, since switching the power transistor and signal transmission both require time, the waveform at this time is IOUT oscillating near the current limiting point. The above experiments prove that the circuit structure of the present invention can limit the output current of the power transistor after a short circuit in the LDO system, and has the function of short circuit protection. It implements the function of short circuit protection with a relatively simple circuit, and has cost and size advantages in practical applications. When the short circuit is removed, the system output returns to normal.

[0108] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A short-circuit protection circuit for an LDO regulator to prevent false triggering, comprising a power output circuit having a power transistor, a first resistor for voltage division, and a second resistor; Its features are, The drain of the power transistor serves as the voltage output terminal, and the source is connected to the power input terminal. The first resistor and the second resistor are connected in series, with one end of the first resistor connected to the voltage output terminal and the other end of the second resistor grounded. The LDO regulator short-circuit protection circuit for preventing false triggering also includes: A voltage regulator circuit, whose output terminal is connected to the gate of the power transistor; A delay circuit outputs a delay control signal; A short-circuit protection circuit receives the delay control signal and detects whether the output current of the power transistor reaches a preset value. When the system output current reaches the preset value, the control signal is delayed for a fixed time. During the delay, the OFF signal level remains unchanged, and the power transistor cannot be turned off. After the delay ends, the delay circuit does not control the OFF signal. At this time, the short-circuit protection circuit can control the power transistor switch normally. When the output current of the power transistor triggers the preset value set by the system, the short-circuit protection circuit will turn off the power transistor output. The delay circuit includes: The first MOSFET has its source connected to the power input terminal; A second MOS transistor has its gate connected to its drain, its drain connected to the drain of the first MOS transistor, and its source grounded. A third MOSFET, with its drain connected to the gate of the first MOSFET and its source connected to the power input terminal; A fourth MOSFET, whose gate is connected to the gate of the second MOSFET, and whose source is grounded; A fifth MOS transistor, with its drain connected to the gate of the third MOS transistor and its source connected to the power input terminal; A sixth MOS transistor, with its drain connected to the drain of the fifth MOS transistor and its source grounded; A seventh MOS transistor outputs a delay control signal at its gate, and its drain is connected to the drain of the fourth MOS transistor, the gate of the fifth MOS transistor, and the gate of the sixth MOS transistor, respectively. Its source is connected to the power input terminal. An eighth MOS transistor has its gate connected to the current mirror bias voltage, its drain connected to the drain of the seventh MOS transistor, and its source grounded. A third capacitor, one end of which is connected to the common terminal between the drain of the seventh MOS transistor and the drain of the eighth MOS transistor, and the other end is grounded; The short-circuit protection circuit also includes a sampling circuit and a comparator circuit. The sampling circuit includes: A sampling transistor, with its gate connected to the gate of the power transistor and its source connected to the power input terminal; A switching transistor, with its gate connected to the voltage output terminal, its drain connected to the drain of the sampling transistor, and its source grounded; A third resistor is connected at one end to the drain of the sampling tube and at the other end to ground. The common terminal between the third resistor and the drain of the sampling tube generates a comparison signal. The comparator circuit includes: A ninth MOS transistor, with its gate connected to its drain, its source connected to the power input terminal, and its drain connected to the output terminal of the delay circuit; The tenth MOS transistor has its gate connected to the reference voltage and its drain connected to the drain of the ninth MOS transistor. The eleventh MOS transistor has its gate connected to the current mirror bias voltage, its drain connected to the source of the tenth MOS transistor, and its source grounded. A twelfth MOS transistor, whose gate is connected to the gate of the ninth MOS transistor, and whose source is connected to the power input terminal; A thirteenth MOS transistor, with its gate connected to the comparison signal, its drain connected to the drain of the twelfth MOS transistor, and its source connected to the drain of the eleventh MOS transistor; The fourteenth MOSFET has its gate connected to the drain of the twelfth MOSFET, the drain connected to the gate of the power transistor, and its source connected to the power input terminal.

2. The LDO regulator short-circuit protection circuit for preventing false triggering as described in claim 1, characterized in that, The power transistor is a PMOS transistor.

3. The LDO regulator short-circuit protection circuit for preventing false triggering as described in claim 1, characterized in that, The first MOS transistor, the third MOS transistor, the fifth MOS transistor, and the seventh MOS transistor are all PMOS transistors; The second MOS transistor, the fourth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are all NMOS transistors.

4. The LDO regulator short-circuit protection circuit for preventing false triggering as described in claim 1, characterized in that, The sampling transistor, the ninth MOS transistor, the twelfth MOS transistor, and the fourteenth MOS transistor are all PMOS transistors; The switching transistor, the tenth MOS transistor, the eleventh MOS transistor, and the thirteenth MOS transistor are all NMOS transistors.

5. The LDO regulator short-circuit protection circuit for preventing false triggering as described in claim 1, characterized in that, The charging current of the ninth MOS transistor is greater than the discharging current of the eighth MOS transistor.

6. The LDO regulator short-circuit protection circuit for preventing false triggering as described in claim 1, characterized in that, The voltage regulator circuit includes: The fifteenth MOSFET has its source connected to the power input terminal; The sixteenth MOS transistor has its gate connected to the reference voltage and its drain connected to the drain of the fifteenth MOS transistor. The seventeenth MOS transistor has its gate connected to the current mirror bias voltage, its drain connected to the source of the sixteenth MOS transistor, and its source grounded. The eighteenth MOS transistor has its gate connected to the gate of the fifteenth MOS transistor, and its gate is also connected to the drain. Its source is connected to the power input terminal. The nineteenth MOS transistor has its gate connected to the common terminal of the first and second resistors, its drain connected to the drain of the eighteenth MOS transistor, and its source connected to the drain of the seventeenth MOS transistor. The common terminal between the drain of the fifteenth MOS transistor and the drain of the sixteenth MOS transistor serves as the drive output terminal of the voltage regulator circuit.

7. The LDO regulator short-circuit protection circuit for preventing false triggering as described in claim 6, characterized in that, Both the fifteenth MOS transistor and the eighteenth MOS transistor are PMOS transistors; The sixteenth MOS transistor, the seventeenth MOS transistor, and the nineteenth MOS transistor are all NMOS transistors.

8. The LDO regulator short-circuit protection circuit for preventing false triggering as described in any one of claims 1 to 7, characterized in that, The LDO regulator short-circuit protection circuit for preventing false triggering also includes: A reference circuit that outputs a reference voltage and a current mirror bias voltage.

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