Electrostatic discharge protection circuit, method, system, device, and storage medium

Abstract

Embodiments of the application disclose an electrostatic protection circuit, method, system, device and storage medium, wherein the circuit comprises: a first end of an input module is connected to an input signal of a chip to be protected; a second end of the input module is connected to a first end of a current release module, a first end of a switch control module and a first end of a switch module respectively; a second end of the switch control module is connected to a second end of the switch module; a third end of the switch control module is connected to a third end of the switch module and a second end of the current release module respectively; the switch control module is configured to enter a conducting state and output a ground voltage to the switch module when the input signal is an electrostatic discharge signal; the switch module is configured to enter a closing state based on the ground voltage; and the current release module is configured to enter the conducting state and release a current of the electrostatic discharge signal when a voltage of the electrostatic discharge signal is greater than or equal to a preset voltage threshold.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technology, and in particular to an electrostatic discharge protection circuit, method, system, device, and storage medium. Background Technology

[0002] Electrostatic discharge (ESD) has always been a problem to be solved in electronic devices, circuits, and systems. It affects various fields, including consumer, industrial, aerospace, military, and medical. ESD protection is becoming increasingly important in display chips, power management chips, driver chips, and automotive chips. However, in related technologies, when an ESD event occurs, the ESD voltage and current enter the chip, causing high-voltage n-channel metal-oxide-semiconductor field-effect transistors (HVNMOS) to experience snapback breakdown damage under ESD high voltage conditions. Summary of the Invention

[0003] In view of this, embodiments of this application provide at least one electrostatic discharge protection circuit, method, system, device, and storage medium.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] On one hand, embodiments of this application provide an electrostatic discharge (ESD) protection circuit, the ESD protection circuit comprising:

[0006] Input module, current release module, switch module, and switch control module;

[0007] The first end of the input module is connected to the input signal of the chip to be protected, and the second end of the input module is connected to the first end of the current release module, the first end of the switch control module, and the first end of the switch module, respectively.

[0008] The second terminal of the switch control module is connected to the second terminal of the switch module;

[0009] The third terminal of the switch control module is connected to the third terminal of the switch module and the second terminal of the current release module, respectively.

[0010] The switch control module is used to enter the conduction state when the input signal is the electrostatic discharge signal, and output a ground voltage to the switch module;

[0011] The switch module is used to enter the off state based on the ground voltage;

[0012] The current release module is used to enter the conduction state and release the current of the electrostatic discharge signal when the voltage of the electrostatic discharge signal is greater than or equal to a preset voltage threshold.

[0013] On the other hand, embodiments of this application provide an electrostatic discharge (ESD) protection method applied to the aforementioned ESD protection circuit, the method comprising:

[0014] The input module in the electrostatic discharge protection circuit receives the input signal from the chip to be protected.

[0015] When the input signal is an electrostatic discharge signal, the switch control module of the electrostatic protection circuit is turned on so that the switch control module provides a grounding voltage to the switch module of the electrostatic protection circuit.

[0016] In response to the ground voltage, the switching module is turned off;

[0017] When the voltage of the electrostatic discharge signal is greater than or equal to a preset voltage threshold, the current release module in the electrostatic protection circuit is turned on, and the current of the electrostatic discharge signal is released by the current release module.

[0018] In another aspect, embodiments of this application provide an electrostatic discharge protection device, including a memory and a processor. The memory stores a computer program that can run on the processor, and the processor executes the program to implement some or all of the steps in the above-described method.

[0019] In another aspect, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above-described method.

[0020] In another aspect, embodiments of this application provide a computer program including computer-readable code, wherein when the computer-readable code is run in a computer device, a processor in the computer device performs some or all of the steps for implementing the above-described method.

[0021] In another aspect, embodiments of this application provide a computer program product, the computer program product including a non-transitory computer-readable storage medium storing a computer program, wherein when the computer program is read and executed by a computer, it implements some or all of the steps in the above method.

[0022] This application provides an electrostatic discharge (ESD) protection circuit, comprising an input module, a current release module, a switch module, and a switch control module. The first terminal of the input module is connected to the input signal of the chip to be protected, and the second terminal is connected to the first terminals of the current release module, the switch control module, and the switch module. Thus, the input module can transmit the input signal to the current release module, the switch control module, and the switch module, thereby controlling the on / off state of these modules based on the voltage and current of the input signal. The second terminal of the switch control module is connected to the second terminal of the switch module; the third terminal of the switch control module is connected to both the third terminal of the switch module and the second terminal of the current release module. This allows the switch control module to control the on / off state of the switch module. When the input signal is the ESD signal, the switch control module enters a conducting state and provides a grounding voltage to the switch module; the switch module then enters a closed state based on the grounding voltage. In this way, when an electrostatic discharge (ESD) event occurs, the switch control module can be turned on in a timely manner to connect to the ground voltage, thereby pulling the voltage of the switch module down to the ground voltage and causing the switch module to enter the off state. This prevents the switch module from being damaged by the ESD signal. Furthermore, if the voltage of the ESD signal exceeds a preset voltage threshold, the current release module turns on and releases the current of the ESD signal. Thus, when the voltage of the ESD signal is high, the current release module turns on, allowing the current of the ESD signal to flow through it and releasing the current, thereby protecting the switch module from damage and achieving ESD protection for the chip being protected.

[0023] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0025] Figure 1 A schematic diagram of the composition structure of the electrostatic discharge protection circuit provided in the embodiments of this application;

[0026] Figure 2A This is a schematic diagram of another component structure of the electrostatic protection circuit provided in the embodiments of this application;

[0027] Figure 2B This is another schematic diagram of the electrostatic discharge protection circuit provided in the embodiments of this application;

[0028] Figure 2C This is a schematic diagram of another component structure of the electrostatic discharge protection circuit provided in the embodiments of this application;

[0029] Figure 3 A schematic diagram illustrating the implementation process of an electrostatic protection method provided in this application embodiment;

[0030] Figure 4 A schematic diagram of the ESD protection circuit provided in related technologies;

[0031] Figure 5 This is a schematic diagram of another component structure of the electrostatic protection circuit provided in the embodiments of this application;

[0032] Figure 6 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0035] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0037] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0038] 1) Electrostatic Discharge (ESD): Electrostatic discharge can occur when one charged conductor comes into contact with another conductor. A strong electric field is established between the two conductors, causing breakdown due to the electric field. An electric arc is generated when the voltage between the two conductors exceeds the breakdown voltage of the air and insulating medium between them. The arc current can reach tens of amperes, and sometimes exceed 100 amperes (A), within a duration of 0.7 nanoseconds (ns) to 10 ns.

[0039] 2) The integrated circuit (IC) industry continues to drive the development of the smartphone industry. Touch and display driver integration (TDDI) brings a unified system architecture. The original system architecture, because the display and touch chips were separate, could lead to some display noise. TDDI, however, achieves unified control, resulting in better noise management. TDDI uses a "time-division scanning" method, dividing one frame of display time into two parts: one part for touch scanning and the other for display scanning, without interference, fundamentally reducing the risk of signal interference.

[0040] The electrostatic discharge (ESD) protection circuit provided in this application embodiment introduces an input module, a current release module, a switch module, and a switch control module. This allows the switch control module to be activated when the input signal is an ESD signal, thus turning off the switch module and protecting it from ESD signal breakdown. Furthermore, when the ESD signal voltage is high, the current release module conducts, releasing the current from the input signal and protecting the chip. The ESD protection circuit provided in this application embodiment can be integrated into a chip in an electronic device, such as a laptop, tablet, desktop computer, set-top box, or mobile device (e.g., mobile phone, portable music player, personal digital assistant, dedicated messaging device, portable gaming device), or a server. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0041] Figure 1 This is a schematic diagram of the composition structure of the electrostatic discharge protection circuit provided in the embodiments of this application, combined with... Figure 1The following description is provided: The electrostatic discharge protection circuit includes: an input module 101, a current release module 102, a switch module 104, and a switch control module 103;

[0042] The first terminal of the input module 101 is connected to the input signal of the chip to be protected. The second terminal of the input module 101 is connected to the first terminal of the current release module 102, the first terminal of the switch control module 103, and the first terminal of the switch module 104. The second terminal of the switch control module 103 is connected to the second terminal of the switch module 104. The third terminal of the switch control module 103 is connected to the third terminal of the switch module 104 and the second terminal of the current release module 102.

[0043] Here, the input module 101 can be a constant input voltage interface or a constant input / output voltage interface; that is, the input module 101 can have input functionality or simultaneously have input / output functionality. The chip to be protected can be any type of chip within an electronic device, such as a display chip, power management chip, driver chip, or automotive chip. The electrostatic discharge (ESD) protection circuit is built into the chip to be protected. For example, the first terminal of the input module is connected to the internal signal line of the chip to receive the input signal output by the chip. Alternatively, the ESD protection circuit can be located outside the chip to be protected, connected to the chip through its pins to receive its input signals.

[0044] The switch control module 103 is used to enter the conduction state when the input signal is the electrostatic discharge signal, and output a ground voltage to the switch module.

[0045] Here, if an electrostatic discharge event occurs in the chip to be protected, the input signal is an electrostatic discharge signal, meaning the input signal is generated by the electrostatic discharge event. For example, the signal generated by the energy discharge current when a charged human body touches the chip. The switch control module 103 can be composed of resistors and capacitors. When it receives the electrostatic discharge signal from the input module, since the electrostatic discharge signal is a high-frequency signal, it can cause the capacitor in the switch control module to turn on, thereby putting the switch control module 103 into a conducting state. At the same time, it provides a ground voltage to the switch module 104 to pull down the voltage of the switch module 104.

[0046] The switch module 104 is used to enter the off state based on the ground voltage.

[0047] Here, the switch module 104 can be formed by connecting at least two HVNMOS transistors in series. The switch module enters the off state in response to the ground voltage provided by the switch control module; in this way, the series-connected HVNMOS transistors form a series-connected parasitic diode. Since the diode has a large breakdown voltage, it is not easily broken down by the voltage generated by the electrostatic discharge signal, thereby protecting the HVNMOS transistors.

[0048] The current release module 102 is used to enter the conduction state and release the current of the electrostatic discharge signal when the voltage of the electrostatic discharge signal is greater than a preset voltage threshold.

[0049] Here, in the circuit design process, to protect the switching module when the current release module is conducting, the on-state voltage of the current release module needs to be set to be less than the breakdown voltage of the switching module. This can be achieved by selecting the components in the current release module according to the breakdown voltage of the switching module, ensuring that the sum of the on-state voltages of all components in the current release module is less than the breakdown voltage of the switching module. That is, the preset voltage threshold is greater than or equal to the sum of the on-state voltages of all components in the current release module, and less than the breakdown voltage of the switching module. In some possible implementations, the current release module includes a diode and an electrostatic discharge (ESD) protection device. In this case, the preset voltage threshold is set according to the sum of the on-state voltages of the diode and the ESD protection device. For example, if the on-state voltage of the diode is 0.5 volts (V) and the on-state voltage of the ESD protection device is 30V, then the preset voltage threshold can be set to 30.5V. Under the action of the ESD discharge signal, the switching module forms a register diode, and the breakdown voltage of the switching module is 50V. In this way, the sum of the conduction voltages of the diodes and electrostatic protection devices in the current release module is less than the breakdown voltage of the switching module. When the voltage of the electrostatic discharge signal is greater than or equal to 30.5V, the diodes and electrostatic protection devices conduct, that is, the current release module enters the conduction state, so that the current of the electrostatic discharge signal flows through the current release module 102 to release the current of the electrostatic discharge signal without breaking down the switching module.

[0050] In this embodiment, the input module in the electrostatic discharge (ESD) protection circuit can transmit input signals to the current release module, the switch control module, and the switch module, thereby controlling the on / off state of the current release module, the switch control module, and the switch module through the voltage and current of the input signal. The switch control module is connected to the switch module, thus controlling the on / off state of the switch module. When an ESD event occurs, the switch control module can promptly turn on to connect to the ground voltage, thereby pulling the voltage of the switch module down to the ground voltage, causing the switch module to enter the off state, thus preventing the switch module from being broken down by the ESD signal. Moreover, when the voltage of the ESD signal is greater than a preset voltage threshold, the current release module enters the conducting state and releases the current of the ESD signal; thus, when the voltage of the ESD signal is high, the current release module turns on, allowing the current of the ESD signal to flow through the current release module, thereby releasing the current of the ESD signal, protecting the switch module from breakdown, and achieving ESD protection for the chip to be protected.

[0051] In some embodiments, the fourth terminal of the switch control module 103 is connected to the fourth terminal of the switch module 104; the switch control module 103 is also used to control the on / off state of the switch module through the second terminal and the fourth terminal of the switch control module.

[0052] Here, the switching module may include two switching devices, whose on / off states are controlled by the second and fourth terminals of the switching control module, respectively. Thus, the fourth terminal of the switching control module is connected to the fourth terminal of the switching module, allowing for more precise voltage input to the switching module to control its conduction or disconnection.

[0053] In some embodiments, the current release module is formed by release submodules in both positive and negative directions and an electrostatic discharge protection submodule to release current from electrostatic discharge signals with larger voltages. The structure of the current release module 102 is as follows: Figure 2A As shown, the current release module 102 includes: a positive release submodule 201, a negative release submodule 202, and an electrostatic discharge protection submodule 203;

[0054] The first end of the positive release submodule 201 is connected to the power supply voltage terminal and the first end of the electrostatic protection submodule 203, respectively; the second end of the positive release submodule 201 is connected to the second end of the input module 101, the first end of the switch control module 103 and the first end of the negative release submodule 202, respectively.

[0055] The second terminal of the negative release submodule 202 is connected to the ground voltage terminal and the second terminal of the electrostatic protection submodule 203, respectively.

[0056] Here, the forward release submodule 201 conducts when the input signal voltage is a forward voltage. The forward release submodule can be implemented using a P-type diode, where the first terminal of the forward release submodule can be the negative terminal of the P-type diode, and the second terminal can be the positive terminal. The electrostatic discharge (ESD) protection submodule 203 has a higher turn-on voltage; it conducts when the input signal voltage is greater than or equal to a preset voltage threshold. The ESD protection submodule 203 can be implemented using an ESD protection device (clamp). Thus, the second terminal of the forward release submodule 201 is connected to the second terminal of the input module as the first terminal of the ESD protection module to receive the input signal.

[0057] The negative release submodule 202 conducts when the input signal voltage is negative. The negative release submodule 202 can be implemented using an N-type diode. Thus, the first terminal of the negative release submodule 202 can be the negative terminal of the N-type diode, and the second terminal can be the positive terminal. In this way, the second terminal of the negative release submodule 202 serves as the second terminal of the current release module, connected to the third terminal of the switch control module and the third terminal of the switch module, and connected to the ground voltage terminal, allowing the negative release submodule 202 to be grounded when it is conducting.

[0058] The forward release submodule is used to enter the conduction state when the voltage of the electrostatic discharge signal is a positive voltage and greater than a preset voltage threshold, and to provide the voltage of the electrostatic discharge signal to the electrostatic protection submodule.

[0059] Here, the forward discharge submodule and the electrostatic discharge protection submodule form a forward voltage protection mode. When the input signal is an electrostatic discharge signal and the voltage is a positive voltage greater than a preset voltage threshold, it indicates that the input signal is generated by static electricity and is accompanied by a large voltage and current. If the voltage is a positive voltage and greater than the preset voltage threshold, then the voltage causes the forward discharge submodule and the electrostatic discharge protection submodule to conduct. The current in the electrostatic discharge signal first flows from the forward discharge submodule to the positive voltage terminal, then from the positive voltage terminal to the electrostatic discharge protection submodule, and finally, the current flows from the electrostatic discharge protection submodule to the ground voltage terminal, thereby releasing the large current in the electrostatic discharge signal and protecting the switching module in the circuit.

[0060] In some possible implementations, the forward release submodule can be implemented using a forward diode, which typically has a forward voltage of 0.5V to 1V.

[0061] The negative discharge submodule is used to enter a conduction state and provide the voltage of the input signal to the electrostatic protection submodule when the voltage of the electrostatic discharge signal is a negative voltage and the absolute value of the negative voltage is greater than the preset voltage threshold.

[0062] Here, the negative discharge submodule and the electrostatic discharge protection submodule form a negative voltage protection mode. When the input signal is an electrostatic discharge signal, and the voltage is negative and its absolute value is greater than a preset voltage threshold, this voltage causes the negative discharge submodule and the electrostatic discharge protection submodule to conduct. The current in the electrostatic discharge signal first flows from the negative discharge submodule to the ground voltage terminal, then from the ground voltage terminal to the electrostatic discharge protection submodule, and finally, the current flows from the electrostatic discharge protection submodule to the positive voltage terminal, thereby releasing the large current in the electrostatic discharge signal and protecting the switching module in the circuit.

[0063] In some possible implementations, the negative release submodule can be implemented using a negative diode, whose forward voltage is typically -0.5V to -1V.

[0064] The electrostatic discharge protection submodule is used to enter a conducting state and release the current of the electrostatic discharge signal based on the voltage of the electrostatic discharge signal.

[0065] Here, the conduction voltage of the electrostatic discharge (ESD) protection submodule is typically set to 30V. This ESD protection module conducts when the input signal is an ESD discharge signal and the voltage value is greater than a preset voltage threshold, thereby dissipating the large current of the input signal from the ESD protection module and preventing the input signal generated by static electricity from damaging the chip being protected.

[0066] In this embodiment, by introducing a positive release submodule, a negative release submodule, and an electrostatic discharge (ESD) protection submodule into the current release module, the ESD protection submodule can be turned on regardless of whether the input signal is a positive or negative voltage, as long as the voltage value is relatively large. The ESD protection submodule releases the large current in the input signal, thereby achieving ESD protection for the switching module and the chip to be protected in the circuit.

[0067] In some embodiments, a switch control module is formed by a signal transmission submodule and a high-frequency submodule, which enables the switch module to be turned off in a timely manner, preventing the switch module from being damaged by voltage generated by static electricity. That is, the aforementioned switch control module 103 can... Figure 2B Implementation, such as Figure 2B As shown, the switch control module 103 includes: a signal transmission submodule 211 and a high-frequency submodule 212.

[0068] The first end of the signal transmission submodule 211 is connected to the first end of the switch module 104 and the second end of the input module 101, respectively; the second end of the signal transmission submodule 211 is connected to the first end of the high-frequency submodule 212.

[0069] The second end of the high-frequency submodule 212 is connected to the second end of the switch module 104; the third end of the high-frequency submodule 212 is connected to the fourth end of the switch module 104. Figure 2B (Not shown); the fourth terminal of the high-frequency submodule 212 is connected to the third terminal of the switch module 104 and the ground voltage terminal, respectively.

[0070] Here, the switch control module 103 can be implemented using capacitors and resistors, while the signal transmission submodule 211 can be implemented using a resistor, which can be a resistor with a resistance value in the kiloohm range. The first end of this resistor is connected to the second end of the input module 101, and the second end of the resistor is connected to the first end of the high-frequency submodule 212, thereby enabling the input signal from the input module 101 to be received and transmitted to the high-frequency submodule 212. The first end of the resistor serves as the first end of the switch control module, connecting to the first end of the switch module 104, thus allowing the switch control module to control the switch module.

[0071] In some possible implementations, the high-frequency submodule 212 can be implemented using capacitors, for example, through... Figure 5 The capacitors CAP1, CAP2 shown are implemented such that the second terminal of the high-frequency submodule 212 is connected to the second terminal of the switch control module as the second terminal of the switch module; the third terminal of the high-frequency submodule 212 is connected to the fourth terminal of the switch control module as the fourth terminal of the switch module; and the fourth terminal of the high-frequency submodule is connected to the third terminal of the switch control module as the third terminal of the switch module. This facilitates the connection of ground voltage when the high-frequency submodule 212 is turned on, thereby providing ground voltage to the switch module and turning off the switch module.

[0072] The signal transmission submodule 211 is used to transmit the input signal to the high-frequency submodule.

[0073] Here, after receiving the input signal, the current of the input signal flows from the signal transmission submodule 211 to the high-frequency submodule.

[0074] The high-frequency submodule 212 is used to enter the conduction state when the input signal is the electrostatic discharge signal, connect to the ground voltage terminal, and provide ground voltage to the switch module.

[0075] Here, if the input signal is a signal generated by static electricity, then the input signal is a high-frequency signal, which causes the capacitor in the high-frequency submodule 212 to conduct, and then the high-frequency submodule 212 is grounded through the fourth terminal to provide a ground voltage to the switch module, so that the switch module enters the off state.

[0076] The high-frequency submodule 212 is also used to enter a disconnect state when the input signal is the working signal of the chip to be protected.

[0077] Here, the operating signal of the chip to be protected is the signal emitted by the chip under normal operating conditions. For example, if the chip to be protected is a power management chip, it emits a power-on signal under normal operating conditions; or, if the chip to be protected is a driver chip, it emits a signal emitted by any component within the chip, such as an amplifier signal, under normal operating conditions. When the chip to be protected emits an input signal under normal operating conditions, this input signal is not a high-frequency signal and cannot turn on the high-frequency submodule; thus, the switch control module is in the off state and does not control the switch module to turn off, so that the operating signal of the chip to be protected can act on the switch module to control the switch module's on or off state.

[0078] In this embodiment, a switch control module is formed by a signal transmission submodule for transmitting input signals and a high-frequency submodule. When the signal transmission submodule transmits an electrostatic discharge signal to the high-frequency submodule, the high-frequency submodule is turned on, thereby grounding the high-frequency submodule and lowering the voltage of the switch module, causing the switch module to turn off, thus protecting the switch module.

[0079] In some embodiments, the switch module is implemented by connecting a first switch submodule and a second switch submodule in series, that is, the switch module 104 can be used to... Figure 2C The structure shown is implemented as follows: Figure 2C As shown, the switch module 104 includes: a first switch submodule 231 and a second switch submodule 232.

[0080] The first terminal of the first switch submodule 231 is connected to the second terminal of the input module 101; the second terminal of the first switch submodule 231 is connected to the second terminal of the switch control module; the third terminal of the first switch submodule 231 is connected to the first terminal of the second switch submodule; the fourth terminal of the first switch submodule 231 is self-biased.

[0081] Here, the first switch submodule 231 can be accessed via... Figure 5The HVNMOS implementation of MN1 shown can be implemented in the following ways: the first terminal of the first switch submodule 231 can be the drain of the HVNMOS of MN1, serving as the first terminal of the switch module. The second terminal of the first switch submodule 231 can be the gate of the HVNMOS of MN1, serving as the second terminal of the switch module, and connected to the second terminal of the signal transmission submodule in the switch control module. Thus, if the input signal is a high-level signal generated during the normal operation of the chip to be protected, the gate voltage of the first switch submodule 231 will be high, and the first switch submodule 231 will enter the conduction state, allowing the input signal to pass through it. The third terminal of the first switch submodule 231 can be the source of the HVNMOS of MN1, connected to the first terminal of the second switch submodule, realizing the series connection of the two switch submodules. The fourth terminal of the first switch submodule 231 originates from and ultimately returns to the first switch submodule 231, meaning the first switch submodule 231 can be a self-biased HVNMOS.

[0082] The second terminal of the second switch submodule 232 is connected to the fourth terminal of the switch control module; the third terminal of the second switch submodule 232 is connected to the third terminal of the switch control module 103 and the ground voltage terminal respectively; the fourth terminal of the second switch submodule 232 is connected to the ground voltage terminal.

[0083] Here, the second switch submodule 232 can be accessed via Figure 5 The HVNMOS implementation of MN2 shown can have its first terminal being the drain of the HVNMOS in MN2. The second terminal of the second switch submodule 232 can be the gate of the HVNMOS in MN2, serving as the fourth terminal of the switch module and connected to the third terminal of the high-frequency submodule in the switch control module. This allows the ground voltage transmitted by the high-frequency submodule to be applied when the high-frequency submodule is on, thus turning off both the second switch submodule 232 and the first switch submodule. The third terminal of the second switch submodule 232 can be the source of the HVNMOS in MN2, connected to the third terminal of the switch control module and the ground voltage terminal, enabling the signal passing through the second switch submodule to be transmitted to the ground terminal even when the chip under protection is operating normally.

[0084] The first switch submodule 231 is used to enter the off state when it receives the ground terminal voltage provided by the switch control module at the second terminal of the first switch submodule.

[0085] Here, if the input signal is an electrostatic discharge signal, the high-frequency submodule in the switch control module is turned on and enters the ground terminal, thereby pulling down the gate voltage of the first switch submodule 231 so that the first switch submodule 231 is turned off.

[0086] The first switch submodule 231 is also used to enter the conduction state when the switch control module is in the off state and the input signal is a high-level signal.

[0087] Here, if the input signal is generated by the chip under protection during normal operation, the high-frequency submodule in the switch control module is disconnected, meaning the switch control module is in the off state. If the signal generated by the chip under protection during normal operation is a high-level signal, the signal transmission submodule in the switch control module outputs a high voltage to the gate of the first switch submodule 231, thereby turning on the first switch submodule 231. Thus, under normal operation, the signal from the chip under protection can pass through the first switch submodule, enabling it to process the input signal.

[0088] The second switch submodule 232 is used to enter the off state when it receives the ground terminal voltage provided by the switch control module at the second terminal of the second switch submodule.

[0089] Here, if the input signal is an electrostatic discharge signal, the high-frequency submodule in the switch control module is turned on, entering the ground terminal, and transmitting the ground voltage to the second terminal of the second switch submodule through the third and fourth terminals of the high-frequency submodule. For example, if the second switch submodule is an HVNMOS, with the high-frequency submodule turned on and its fourth terminal grounded, the third terminal of the high-frequency submodule transmits the ground voltage to the gate of the HVNMOS, thereby pulling down the gate voltage of the second switch submodule and turning it off.

[0090] In this embodiment, by connecting the first and second switch submodules in series, both the first and second switch submodules are turned off when the switch control module is on, forming two parasitic diodes with relatively high breakdown voltages. For example, if the breakdown voltage of each parasitic diode is 25V, then the breakdown voltage of the two parasitic diodes connected in series is 50V. Thus, the electrostatic discharge signal voltage must reach at least 50V to break down the two parasitic diodes. Furthermore, when the electrostatic discharge signal voltage reaches 50V, this voltage exceeds a preset voltage threshold, causing the current release module to conduct. This releases the large current generated by static electricity, protecting the two switch submodules connected in series within the switch module, thereby achieving electrostatic protection for the chip to be protected.

[0091] In some embodiments, by connecting the second terminal of the second switch submodule to the internal circuitry of the chip to be protected, so that the on / off state of the second switch submodule can be controlled by the logic circuitry under normal operating conditions of the chip, this can be achieved through the following process: The second terminal of the second switch submodule 232 is connected to the internal logic circuitry of the chip to be protected. The second switch submodule 232 is used to enter a closed state or an on state in response to the logic signal when the input signal is the operating signal of the chip to be protected.

[0092] Here, the internal logic circuit of the chip to be protected can be any logic circuit within the chip, such as an inverter within the chip. Connecting the second terminal of the second switch submodule 232 to the output terminal of the directional controller allows the inverter to output high and low level signals, controlling the on / off state of the second switch submodule. Taking an HVNMOS as an example, the gate of the HVNMOS is connected to the internal logic circuit of the chip to be protected. If the logic signal is high, the gate of the HVNMOS is connected to a high level, turning the HVNMOS on. Thus, under normal operating conditions, the internal logic circuit can control the second switch submodule 232, allowing the signals generated by the chip to be processed by both the first and second switch submodules.

[0093] In some possible implementations, the high-frequency submodule, namely high-frequency submodule 212, is implemented by multiple capacitors, including: a first capacitor, a second capacitor, and a third capacitor.

[0094] The first terminal of the first capacitor is connected to the first terminal of the second capacitor and the second terminal of the signal transmission submodule; the second terminal of the first capacitor is connected to the second terminal of the third capacitor and the ground voltage terminal; the second terminal of the second capacitor is connected to the first terminal of the third capacitor and the fourth terminal of the switching module.

[0095] Here, the first, second, and third capacitors can be of the same or different types, and their capacitance values ​​can be the same or different. All three capacitors enter a conducting state under high-frequency signal conditions; that is, they enter a conducting state when the input signal is an electrostatic discharge signal. When the input signal is a signal generated by the chip under protection in its normal operating state, they do not conduct; that is, they are disconnected.

[0096] The first capacitor is used to enter the conduction state when the input signal is the electrostatic discharge signal, and connect the ground voltage terminal to control the first switch submodule of the switch module to enter the off state.

[0097] Here, the first terminal of the first capacitor serves as the first terminal of the high-frequency submodule and is connected to the second terminal of the signal transmission submodule and the gate of the first switching submodule. The second terminal of the first capacitor is grounded. Thus, when the first capacitor is turned on, it connects to the ground voltage terminal to pull down the gate voltage of the first switching submodule, causing the first switching submodule to enter the off state.

[0098] When the input signal is the electrostatic discharge signal, the second capacitor and the third capacitor enter the conducting state and connect the ground voltage terminal to control the second switch submodule of the switch module to enter the closed state.

[0099] Here, the second terminal of the second capacitor and the first terminal of the third capacitor are connected to the gate of the second switch submodule, and the second terminal of the third capacitor is grounded; thus, when the second capacitor and the third capacitor are turned on, the second capacitor and the third capacitor are connected to the ground voltage terminal to pull down the gate voltage of the second switch submodule, so that the second switch submodule enters the off state.

[0100] In this embodiment, a high-frequency submodule is formed by multiple capacitors. When the input signal is an electrostatic discharge signal, the multiple capacitors are turned on, that is, the high-frequency submodule is turned on, so as to pull down the gate voltage of the first switch submodule and the second switch submodule, thereby turning off the first switch submodule and the second switch submodule, thus protecting the first switch submodule and the second switch submodule from being broken down by the high voltage of the electrostatic discharge signal.

[0101] This application provides an electrostatic discharge protection method, which can be executed by a processor of a computer device. Figure 3 This is a schematic diagram illustrating the implementation process of an electrostatic discharge (ESD) protection method provided in an embodiment of this application, as shown below. Figure 3 As shown, the method includes the following steps S301 to S304:

[0102] Step S301: The input module in the electrostatic protection circuit receives the input signal of the chip to be protected.

[0103] Here, the electrostatic discharge protection circuit can be the electrostatic discharge protection circuit in the above embodiment. The input module in the electrostatic discharge protection circuit receives the input signal of the chip to be protected, so as to transmit the input signal to other modules in the electrostatic discharge protection circuit through the input module.

[0104] Step S302: When the input signal is an electrostatic discharge signal, the switch control module of the electrostatic protection circuit is turned on so that the switch control module provides a grounding voltage to the switch module of the electrostatic protection circuit.

[0105] Here, when the input signal is an electrostatic discharge signal generated by static electricity, the switch control module is turned on and provides a ground voltage to the switch module so that the switch module enters the off state.

[0106] Step S303: In response to the grounding voltage, the switching module is turned off.

[0107] Here, when the switch control module is on, the switch control module pulls down the voltage of the switch module, causing the switch module to enter the off state.

[0108] Step S304: When the voltage of the electrostatic discharge signal is greater than or equal to a preset voltage threshold, the current release module in the electrostatic protection circuit is turned on, and the current of the electrostatic discharge signal is released by the current release module.

[0109] Here, if the voltage of the electrostatic discharge signal is too high, it will cause the current release module to conduct, so that current flows through the current release module, thereby releasing the large current generated by static electricity and protecting the switching module.

[0110] In this embodiment, when an electrostatic discharge (ESD) event occurs, the switch control module is turned on to connect to the ground voltage, thereby pulling the voltage of the switch module down to the ground voltage and turning off the switch module. This prevents the switch module from being damaged by the ESD signal. Furthermore, if the voltage of the ESD signal exceeds a preset voltage threshold, the current release module is turned on and releases the current of the ESD signal. Thus, when the voltage of the ESD signal is high, the current release module is turned on, allowing the current of the ESD signal to flow through it, thereby achieving ESD protection for the chip to be protected.

[0111] The following describes the application of the electrostatic discharge (ESD) protection circuit provided in the embodiments of this application in a real-world scenario, taking an ESD protection circuit applied to an input / output constant voltage interface as an example.

[0112] In some embodiments, ESD has been a persistent problem in electronic devices, circuits, and systems. This issue affects various sectors, including consumer, industrial, aerospace, military, and medical. ESD protection is becoming increasingly important in display chips, power management chips, driver chips, and automotive chips, playing a crucial role in everyday applications. However, in high-voltage processes, HVNMOS is easily broken down by ESD voltages, leading to sudden backflashover and damage.

[0113] Based on this, the embodiments of this application provide an ESD protection structure for a constant input / output constant voltage interface, which effectively reduces the damage caused by HVNMOS in the internal region of the chip when an ESD event occurs.

[0114] Figure 4 The diagram shows the structure of an ESD protection circuit provided in related technologies, such as... Figure 4 As shown, the ESD protection circuit includes a constant input / output voltage interface PAD 41, a P-type diode (Pdiode) 42, an N-type diode (Ndiode) 43, an electrostatic discharge (ESD) protection device (Clamp) 44, an HVNMOS 45, a power supply voltage VDDA 46, and a ground terminal (VSSA) 47. In this ESD protection circuit, the gate terminal of the HVNMOS 45 is connected to the wire NET2, which is connected to the internal circuitry of the chip. The HVNMOS 45 is turned on or off by signals within the chip. Pdiode 42 is an ESD protection device that protects against PD ESD (PD means pin is positively biased against the power supply) and PSESD (PS means pin is positively biased against VSS) test modes. Ndiode 43 is an ESD protection device that protects against ND ESD (ND means pin is negatively biased against the power supply) and NS ESD (NS means pin is negatively biased against VSS) test modes. Clamp 44 is an ESD protection device between VDDA and VSSA. Pdiode, Ndiode, and Clamp combine to form the ESD network of the PAD interface. However, due to the large chip size and the excessively high turn-on voltage of the Clamp device, the clamping voltage of the PAD interface will eventually become even higher. The ESD voltage and current will eventually enter the chip, causing the HVNMOS in the chip to undergo sudden return breakdown damage under high ESD conditions.

[0115] Based on this, embodiments of this application provide an electrostatic discharge (ESD) protection circuit that uses a series-connected HVNMOS transistor for ESD protection, such as... Figure 5 As shown, MN1 is a self-biased HVNMOS with its own P-well. A resistor-capacitor (RC) circuit network is added to improve ESD protection. When the chip is working normally, the voltage of connection NET1 is high. Connection NET1 connects to resistor RES, capacitor CAP, and the gate terminal of MN1's HVNMOS. When MN1's HVNMOS is turned on, due to the blocking effect of capacitor CAP1, connection NET2 receives signals from inside the chip to control the conduction and shutdown of PAD 41 on the VSSA path. Connection NET2 connects to capacitors CAP1 and CAP2, and the gate terminal of MN2's HVNMOS. Figure 5 As shown, the RC network includes: resistor RES, capacitor CAP, capacitor CAP1, and capacitor CAP2.

[0116] In some possible implementations, when PAD 41 is high, there is a high voltage on the NET1 line after resistor RES. The HVNMOS of MN1 is turned on under the high voltage. The connection NET2 needs to receive the logic signal inside the chip. If the NET2 signal is high, the path from PAD 41 to the VSSA terminal is open. If the NET2 signal is low, the path from PAD 41 to VSSA 56 is closed.

[0117] When an ESD event occurs, such as when a charged human body touches the chip to discharge energy current, the gate (G) terminals of MN1 and MN2 are set low through the RC network, meaning the G terminals of MN1 and MN2 are connected to the ground voltage terminal. This shuts down MN1 and MN2, and the HVNMOS becomes two parasitic diodes. Figure 5 As shown, in this case, the HVNMOS of MN1 is equivalent to parasitic diode 51, and the HVNMOS of MN2 is equivalent to parasitic diode 52. The breakdown voltage of the parasitic diode of the HVNMOS is generally 25V. Since the two diodes are connected in series, the PAD will only be damaged at a clamping voltage of approximately 50V. However, at a clamping voltage of 50V, the ESD current has already been discharged through Pdiode 42 and Clamp 44, thus achieving the effect of protecting the HVNMOS.

[0118] In this embodiment, an RC network and a self-biased HVNMOS are added to the protection circuit to improve the electrostatic discharge level of the PAD interface. By adding the RC network, the HVNMOS is turned off when an ESD event occurs, making the HVNMOS equivalent to two parasitic reverse diodes, which increases the sudden return breakdown voltage of the HVNMOS, thereby protecting the HVNMOS.

[0119] Based on the foregoing embodiments, this application provides an electrostatic discharge protection device, which includes various units and modules included in each unit. It can be implemented by a processor in a computer device; of course, it can also be implemented by specific logic circuits. In the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0120] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. In some embodiments, the functions or modules included in the device provided in this disclosure can be used to perform the methods described in the above method embodiments. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0121] It should be noted that, in the embodiments of this application, if the above-described backlight control method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0122] This application provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0123] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0124] This application provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0125] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0126] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0127] It should be noted that, Figure 6 This is a schematic diagram of a hardware entity of a computer device in an embodiment of this application, such as... Figure 6 As shown, the hardware entities of the computer device 600 include: a processor 601, a communication interface 602, and a memory 603. The processor 601 typically controls the overall operation of the computer device 600. The communication interface 602 enables the computer device to communicate with other terminals or servers via a network. The memory 603 is configured to store instructions and applications executable by the processor 601, and can also cache data to be processed or already processed by the processor 601 and various modules in the computer device 600 (e.g., image data, audio data, voice communication data, and video communication data). It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 601, the communication interface 602, and the memory 603 can be performed via a bus 604.

[0128] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0129] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0130] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0131] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0132] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0133] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0134] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0135] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An electrostatic discharge protection circuit, characterized by, The electrostatic discharge protection circuit includes: an input module, a current release module, a switch module, and a switch control module; The first end of the input module is connected to the input signal of the chip to be protected, and the second end of the input module is connected to the first end of the current release module, the first end of the switch control module, and the first end of the switch module, respectively. The second terminal of the switch control module is connected to the second terminal of the switch module; The third terminal of the switch control module is connected to the third terminal of the switch module and the second terminal of the current release module, respectively. The switch control module is used to enter the conduction state when the input signal is an electrostatic discharge signal, and output a ground voltage to the switch module. The switch module is used to enter the off state based on the ground voltage; The current release module is used to enter the conduction state and release the current of the electrostatic discharge signal when the voltage of the electrostatic discharge signal is greater than or equal to a preset voltage threshold. The switch control module includes: a signal transmission submodule and a high-frequency submodule; a first terminal of the signal transmission submodule is connected to a first terminal of the switch module and a second terminal of the input module; a second terminal of the signal transmission submodule is connected to a first terminal of the high-frequency submodule; a second terminal of the high-frequency submodule is connected to a second terminal of the switch module; a third terminal of the high-frequency submodule is connected to a fourth terminal of the switch module; and a fourth terminal of the high-frequency submodule is connected to the third terminal of the switch module and a ground voltage terminal. The signal transmission submodule is used to transmit the input signal to the high-frequency submodule; The high-frequency submodule is used to enter a conduction state when the input signal is the electrostatic discharge signal, connect to the grounding voltage terminal, and provide grounding voltage to the switching module; The switching module includes: a first switching submodule and a second switching submodule; a first terminal of the first switching submodule is connected to a second terminal of the input module; a second terminal of the first switching submodule is connected to a second terminal of the switch control module; a third terminal of the first switching submodule is connected to a first terminal of the second switching submodule; a fourth terminal of the first switching submodule is self-biased; a second terminal of the second switching submodule is connected to a fourth terminal of the switch control module; a third terminal of the second switching submodule is connected to both a third terminal of the switch control module and a ground voltage terminal; and a fourth terminal of the second switching submodule is connected to the ground voltage terminal. The first switch submodule is configured to enter a closed state when it receives a ground terminal voltage provided by the switch control module at its second terminal; The second switch submodule is used to enter the off state when it receives the ground terminal voltage provided by the switch control module at the second terminal of the second switch submodule.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that, The current release module includes: a positive release submodule, a negative release submodule, and an electrostatic protection submodule; The first end of the positive release submodule is connected to the power supply voltage terminal and the first end of the electrostatic protection submodule, respectively; the second end of the positive release submodule is connected to the second end of the input module, the first end of the switch control module, and the first end of the negative release submodule, respectively. The second terminal of the negative release submodule is connected to both the ground voltage terminal and the second terminal of the electrostatic protection submodule. The forward release submodule is used to enter the conduction state when the voltage of the electrostatic discharge signal is a positive voltage and greater than a preset voltage threshold, and to provide the voltage of the electrostatic discharge signal to the electrostatic protection submodule. The negative discharge submodule is used to enter the conduction state and provide the voltage of the input signal to the electrostatic protection submodule when the voltage of the electrostatic discharge signal is a negative voltage and the absolute value of the negative voltage is greater than the preset voltage threshold. The electrostatic discharge protection submodule is used to enter a conducting state and release the current of the electrostatic discharge signal based on the voltage of the electrostatic discharge signal.

3. The electrostatic discharge protection circuit according to claim 1, characterized in that, The fourth terminal of the switch control module is connected to the fourth terminal of the switch module; The switch control module is also used to control the on / off state of the switch module through the second terminal and the fourth terminal of the switch control module.

4. The electrostatic discharge protection circuit according to claim 1, characterized in that, The high-frequency submodule is also used to enter a disconnect state when the input signal is the working signal of the chip to be protected.

5. The electrostatic discharge protection circuit according to any one of claims 1 to 4, characterized in that, The second terminal of the second switch submodule is connected to the internal logic circuit of the chip to be protected; The internal logic circuit of the chip to be protected is used to output logic signals to the second switch submodule; The second switch submodule is used to enter a closed state or an open state in response to the logic signal when the input signal is the working signal of the chip to be protected.

6. The electrostatic discharge protection circuit according to claim 1, characterized in that, The high-frequency submodule includes: a first capacitor, a second capacitor, and a third capacitor; The first terminal of the first capacitor is connected to the first terminal of the second capacitor and the second terminal of the signal transmission submodule; the second terminal of the first capacitor is connected to the second terminal of the third capacitor and the ground voltage terminal; the second terminal of the second capacitor is connected to the first terminal of the third capacitor and the fourth terminal of the switching module. The first capacitor is used to enter the conduction state when the input signal is the electrostatic discharge signal, and connect the ground voltage terminal to control the first switch submodule of the switch module to enter the off state. When the input signal is the electrostatic discharge signal, the second capacitor and the third capacitor enter the conducting state and connect the ground voltage terminal to control the second switch submodule of the switch module to enter the closed state.

7. A method for electrostatic protection, characterized in that, The method, applied to the electrostatic discharge protection circuit according to any one of claims 1 to 6, comprises: The input module in the electrostatic discharge protection circuit receives the input signal from the chip to be protected. When the input signal is an electrostatic discharge signal, the switch control module of the electrostatic protection circuit is turned on so that the switch control module provides a grounding voltage to the switch module of the electrostatic protection circuit. In response to the ground voltage, the switching module is turned off; When the voltage of the electrostatic discharge signal is greater than or equal to a preset voltage threshold, the current release module in the electrostatic protection circuit is turned on, and the current of the electrostatic discharge signal is released by the current release module.

8. An electrostatic discharge protection system, characterized in that, The electrostatic discharge protection system includes: the chip to be protected and the electrostatic discharge protection circuit according to any one of claims 1 to 6.

9. An electrostatic discharge protection device, comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method of claim 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 7.

Images