Driving circuit and related control chip circuit, power adapter and electronic device

Abstract

The application provides a driving circuit and related control chip circuit, a power adapter and an electronic device. The driving circuit comprises a first-stage driving circuit and a second-stage driving circuit, wherein the first-stage driving circuit is connected to the second-stage driving circuit; the second-stage driving circuit is used for driving an external power tube to realize a driving function; the driving current of the second-stage driving circuit is E times of the first-stage driving current, and E is greater than 1. According to the embodiment of the application, the di / dt change can be reduced, the power tube driving voltage can be smoothly increased, and the EMI effect of the chip can be improved by using the small-current driving of the first-stage driving circuit and the large-current driving method of the second-stage driving circuit.

Description

Technical Field

[0001] This application relates to the field of electronic technology, specifically to drive circuits and related control chip circuits, power adapters and electronic devices. Background Technology

[0002] Switching power supplies suffer from electromagnetic interference (EMI) noise due to the changes in dv / dt and di / dt during switching, caused by parasitic inductance and capacitance. The main noise sources include power MOSFETs, output diodes, inductors, and transformers. Currently popular PD (power delivery) fast charging requires a wider output voltage range. Therefore, chip design necessitates a wider operating voltage range for the chip's input voltage, which presents a challenge for the design of the driver circuit.

[0003] In existing drive control technologies, a large current is often applied from the outset, resulting in a large di / dt and consequently poor electromagnetic interference (EMI) performance. Therefore, the problem of reducing EMI during the drive process urgently needs to be solved. Summary of the Invention

[0004] This application provides a driving circuit and related control chip circuit, power adapter and electronic device, which can reduce EMI effects during the driving process.

[0005] In a first aspect, embodiments of this application provide a driving circuit, the driving circuit comprising: a first driving circuit and a second driving circuit, wherein...

[0006] The first driving circuit is connected to the second driving circuit; the second driving circuit is used to drive the external power transistor to achieve the driving function; the driving current of the second driving circuit is E times the driving current of the first driving circuit, where E is greater than 1.

[0007] Secondly, embodiments of this application provide a control chip circuit, the control chip circuit including the driving circuit described in the first aspect above.

[0008] Thirdly, embodiments of this application provide a power adapter, which includes a drive circuit as described in the first aspect, or a control chip circuit as described in the second aspect.

[0009] Fourthly, embodiments of this application provide an electronic device, which includes a driving circuit as described in the first aspect, or a control chip circuit as described in the second aspect, or a power adapter as described in the third aspect.

[0010] Implementing the embodiments of this application has the following beneficial effects:

[0011] As can be seen from the driving circuit and related products described in the embodiments of this application, the driving circuit includes: a first driving circuit and a second driving circuit, wherein the first driving circuit is connected to the second driving circuit, and the second driving circuit is used to drive an external power transistor to achieve the driving function. The driving current of the second driving circuit is E times the driving current of the first driving circuit, where E is greater than 1. Since the first driving circuit uses a small current driving method and the second driving circuit uses a large current driving method, the di / dt change can be reduced, the driving voltage of the power transistor can rise smoothly, and the EMI effect of the chip can be improved. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of an NMOS transistor provided in an embodiment of this application;

[0014] Figure 2 This is a schematic diagram of a PMOS transistor provided in an embodiment of this application;

[0015] Figure 3 This is a schematic diagram of the structure of a driving circuit provided in an embodiment of this application;

[0016] Figure 4 This is a waveform diagram of a driving circuit provided in an embodiment of this application;

[0017] Figure 5 This is another schematic diagram of a driving circuit provided in an embodiment of this application;

[0018] Figure 6 This is a schematic diagram of the structure of a first-segment driving circuit provided in an embodiment of this application;

[0019] Figure 7 This is a schematic diagram of the structure of a second-segment driving circuit provided in an embodiment of this application;

[0020] Figure 8 This is a waveform diagram of another driving circuit provided in an embodiment of this application. Detailed Implementation

[0021] To help those skilled in the art better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the description of the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, software, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but also includes steps or units not listed, or other steps or units inherent to such processes, methods, products, or apparatus.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] The embodiments of this application are described below with reference to the accompanying drawings. In the drawings, the intersection of intersecting wires is indicated by dots, and the absence of dots indicates that the wires are not connected.

[0025] In the embodiments of this application, such as Figure 1 As shown, for an NMOS transistor, the first terminal is the gate, the second terminal is the source, the third terminal is the drain, the fourth terminal is the substrate, and the fifth terminal is grounded; as shown... Figure 2 As shown, for a PMOS transistor, the first terminal is the gate, the second terminal is the source, the third terminal is the drain, and the fourth terminal is the substrate. The fourth terminal is used to connect to the power supply, such as VCC or VDD.

[0026] In related technologies, such as Figure 3 As shown, the drive circuit uses a single-stage control method, and the waveform of its drive signal is shown in the figure. Figure 4As shown, the large di / dt variation during switching leads to poor EMI performance. Furthermore, the highest output voltage is VDD-VGS, where VGS is approximately 1.2V. When the chip is used for PD fast charging, and VDD voltage drops to as low as 6.5V, the output voltage is limited to around 5.3V. Traditional high-voltage power transistors have a threshold voltage between 3 and 4V. Using a 5.3V output drive voltage to drive a high-voltage MOS power transistor with a threshold voltage of 3-4V results in insufficient drive capability and incomplete transistor turn-on, leading to low switching efficiency.

[0027] Please see Figure 5 , Figure 5 This is a schematic diagram of a driving circuit provided in an embodiment of this application. The driving circuit includes: a first driving circuit and a second driving circuit, wherein...

[0028] The first driving circuit is connected to the second driving circuit; the second driving circuit is used to drive the external power transistor to achieve the driving function; the driving current of the second driving circuit is E times the driving current of the first driving circuit, where E is greater than 1.

[0029] The first driving circuit uses a small current, while the second driving circuit uses a large current. The two circuits achieve a transition from small to large current, thereby reducing the di / dt change and improving EMI performance.

[0030] As can be seen, the driving circuit described in the embodiments of this application includes: a first driving circuit and a second driving circuit. The first driving circuit is connected to the second driving circuit. The second driving circuit is used to drive the external power transistor to achieve the driving function. The driving current of the second driving circuit is E times the driving current of the first driving circuit, where E is greater than 1. Since the first driving circuit uses a small current driving method and the second driving circuit uses a large current driving method, the di / dt change can be reduced, the driving voltage of the power transistor can rise smoothly, and the EMI effect of the chip can be improved.

[0031] Furthermore, such as Figure 6 , Figure 7 As shown, Figure 6 A schematic diagram of the first driving circuit is given. Figure 7 The structural diagram of the second driving circuit is shown below:

[0032] Optional, such as Figure 7As shown, the second driving circuit includes a boost circuit, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5; the boost circuit includes: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a bipolar junction transistor (BJT), a first inverter group, a first capacitor C, a first resistor R1, and a second resistor R2;

[0033] The first terminal of the first PMOS transistor P1 is connected to the first terminal of the first NMOS transistor N1; the third terminal of the first PMOS transistor P1 is connected to the negative terminal (-) of the first capacitor C and the third terminal of the first NMOS transistor N1; the third terminal of the first PMOS transistor P1 is connected to the first power supply VCC and the BJT; the BJT is connected to the positive terminal (+) of the first capacitor C and the second terminal of the second PMOS transistor P2.

[0034] The first terminal of the second PMOS transistor P2 is connected to the first terminal of the second NMOS transistor N2 and the output terminals of the first a1 inverters in the first inverter group, where the first inverter group includes a inverters, a1 is less than a, and both a1 and a are odd numbers; the second terminal of the second PMOS transistor P2 is also connected to the positive (+) terminal of the first capacitor C; the third terminal of the second PMOS transistor P2 is connected to the first terminal of the third NMOS transistor N3 and the third terminal of the second NMOS transistor N2; the output terminal of the first inverter group is connected to the first terminal of the fourth NMOS transistor N4; the third terminal of the second PMOS transistor P2 is grounded;

[0035] The second terminal of the third NMOS transistor N3 is connected to the third terminal of the fourth NMOS transistor N4 and the second terminal of the fifth NMOS transistor N5; the first terminal of the fifth NMOS transistor N5 is used to connect to the output signal DU2 of the first driving circuit; the third terminals of the third NMOS transistor N3 and the third terminal of the fifth NMOS transistor N5 are both connected to the second power supply VDD; the second terminal of the fifth NMOS transistor N5 is connected to one end of the first resistor R1 and the driving port GATE; the other end of the first resistor R1 is connected to one end of the second resistor R2 and is used to output the comparison voltage VO_ADOPT, and the other end of the second resistor R2 is grounded;

[0036] The first terminal of the first NMOS transistor N1 is used to connect to the second input signal VCON2. The second input signal VCON2 is the output signal obtained by the output of the AND gate circuit through the second inverter group y2. One input terminal of the AND gate circuit is input by the first input signal VCON1 through the third inverter group y1. The other input terminal of the AND gate circuit is used to input the drive signal PWM. The second inverter group y2 includes b inverters. The first input signal is the output signal of the comparator. The third inverter group y1 includes c inverters, where b and c are both odd numbers. The second terminal of the first NMOS transistor N1 is grounded.

[0037] The first inverter group may include 'a' inverters, where a1 is less than a, and both a1 and a are odd numbers. For example, in this embodiment, three inverters are used: inverter x1, inverter x2, and inverter x3. Inverters can improve driving capability and achieve a delay effect.

[0038] VCC is the internal power supply voltage of the driver circuit chip, and VDD is the external power supply voltage of the driver circuit chip. The driver port GATE is used to connect the power transistor, which charges the external circuitry.

[0039] Optional, such as Figure 6 As shown, the first driving circuit includes: the comparator, the third inverter group, the first current amplifier circuit, the second current amplifier circuit, the sixth NMOS transistor N6, and the seventh NMOS transistor N7; the fourth inverter group includes d inverters, where d is an odd number; the first current amplifier circuit includes the third PMOS transistor P3, the fourth PMOS transistor P4, the third resistor R3, and the fourth resistor R4; the second current amplifier circuit includes the eighth NMOS transistor N8 and the ninth NMOS transistor N9;

[0040] The positive input terminal (+) of the comparator is connected to the third power supply, and the negative input terminal (-) of the comparator is input with the comparison voltage VO_ADOPT; the output terminal of the comparator is connected to the first terminal of the sixth NMOS transistor N6 and the input terminal of the third inverter group; the output terminal of the third inverter group is connected to the first terminal of the seventh NMOS transistor N7.

[0041] The second terminal of the sixth NMOS transistor N6 is connected to the third terminal of the ninth NMOS transistor N9; the third terminal of the sixth NMOS transistor N6 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the third terminal and the first terminal of the third PMOS transistor P3; the first terminal of the third PMOS transistor P3 is connected to the first terminal of the fourth PMOS transistor P4; the second terminals of the third PMOS transistor P3 and the fourth PMOS transistor P4 are both connected to the second power supply VDD; the third terminal of the fourth PMOS transistor P4 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the third terminal of the seventh NMOS transistor N7 and outputs the output signal of the first segment drive circuit; the second terminal of the seventh NMOS transistor N7 is grounded.

[0042] The first terminal of the ninth NMOS transistor N9 is connected to the first terminal of the eighth NMOS transistor N8; the first and third terminals of the eighth NMOS transistor N8 are used to connect to the current bias module to introduce bias current I1; the second terminal of the ninth NMOS transistor N9 and the third terminal of the eighth NMOS transistor N8 are both grounded.

[0043] The fourth inverter group may include d inverters, where d is an odd number. In this embodiment, three inverters are used: inverter x4, inverter x5, and inverter x6. The third power supply provides the internal reference voltage VREF of the power chip. The aforementioned bias current is from the internal bias circuit of the chip. The first current amplifier circuit and the second current amplifier circuit are used to implement the current amplification function.

[0044] Optionally, the comparator is used to compare the comparison voltage VO_ADOPT and the reference voltage VREF of the third power supply V1 to obtain the first drive control signal. The comparison voltage VO_ADOPT is the voltage obtained by voltage division through the first resistor R1 and the second resistor R2.

[0045] When the first segment drive control signal is high, the sixth NMOS transistor N6 is turned on, the input current at the first terminal of the ninth NMOS transistor N9 is M times the bias current, and at the same time, the seventh NMOS transistor N7 is turned off, where M is greater than 1.

[0046] After the fourth PMOS transistor P4 is turned on, it drives the first terminal of the fifth NMOS transistor N5 to make the voltage at the first terminal of the fifth NMOS transistor N5 rise rapidly. The set value is M*N times the bias current, where N is greater than 1.

[0047] The first terminal of the fifth NMOS transistor N5 is driven, causing the voltage of the fifth NMOS transistor N5 to rise rapidly.

[0048] Where M is greater than 1, for example, M = 5. N is greater than 1, for example, N = 40. Specifically, P4 is turned on, causing the output signal DU of the first segment drive circuit to rise to the set value, thereby driving the first terminal of the fifth NMOS transistor N5, so that the voltage at the first terminal of the fifth NMOS transistor N5 rises rapidly.

[0049] Optionally, when the voltage GATE of the output signal of the second stage driving circuit rises to the first preset threshold, the first input signal becomes low, the sixth NMOS transistor N6 is turned off to close the charging path; at the same time, the seventh NMOS transistor N7 is pulled down to turn on, pulling down the voltage of the output signal of the first stage driving circuit, and turning off the driving of the fifth NMOS transistor N5 to complete the first stage driving process.

[0050] The first preset threshold can be preset or set by system default. For example, the first preset threshold is VGS_N5+(R1+R2) / R2*VREF, where VGS is the voltage between the gate and the source.

[0051] Optionally, the first PMOS transistor P1 and the first NMOS transistor N1 constitute a first inverter; the second PMOS transistor P2 and the second NMOS transistor N2 constitute a second inverter.

[0052] Optionally, during the second driving process, the first PMOS transistor P1 of the first inverter is turned on, and the first NMOS transistor N1 of the first inverter is turned off; the initial voltage of the positive terminal of the first capacitor is a first voltage value, which is equal to the difference between the voltage of the first power supply and the voltage of the VBE terminal of the BJT.

[0053] When the first PMOS transistor P1 is turned on, the negative terminal of the first capacitor is charged until the absolute value of the difference between its voltage and the voltage of the first power supply is less than a second preset threshold. Then, the positive terminal of the first capacitor is raised to a second voltage value, which is equal to twice the difference between the voltage of the first power supply and the voltage at the VBE terminal of the BJT, i.e., 2VV-VBE. At the same time, the upper transistor of the second inverter, the second PMOS transistor P2, is turned on, and the lower transistor, the second NMOS transistor N2, is turned off. The third NMOS transistor N3 is then turned on.

[0054] The second preset threshold can be preset or set by system default. The second preset threshold can be close to 0, for example, the second preset threshold = 0, or, for example, the second preset threshold = 0.01.

[0055] In this circuit, P1 and N1 form the first inverter INV1, and P2 and N2 form the second inverter INV2. INV1, C, INV2, and the BJT together constitute a simple boost circuit, also known as a BOOST circuit. Using BOOST control technology, the drive voltage of the power transistor is ensured to be within a reasonable range. This improves the output drive voltage and switching efficiency when the chip's input voltage is low, enhancing the drive capability under low input voltage conditions and meeting the wide-range input voltage requirements of the PD.

[0056] In specific implementation, the driving circuit described in the embodiments of this application works as follows:

[0057] (1) When the drive signal (Pulse Width Modulation, PWM) is high and the VCON1 signal is low, the upper transistor P1 of the first inverter INV1 is turned on and the lower transistor N1 is turned off. The initial voltage of the positive terminal of the capacitor is VCC-VBE, where VBE is the voltage at the VBE terminal of the BJT, which is usually about 0.6-0.7V. When transistor P1 is turned on, the negative terminal of the capacitor is charged to VCC, and the positive terminal of the capacitor is raised to 2VCC-VBE. At the same time, the upper transistor P2 of the second inverter INV2 is turned on and the lower transistor N2 is turned off, so the output voltage DU1 is 2VCC-VBE, which in turn turns on the drive transistor N3.

[0058] (2) When the drive signal PWM is low and the VCON1 signal is high, the upper transistor P1 of the first inverter INV1 is turned off, the lower transistor N1 is turned off, the negative terminal of the capacitor is pulled to 0, and the positive terminal of the capacitor becomes VCC-VBE. At the same time, the upper transistor P2 of the second inverter INV2 is turned off, and the lower transistor N2 is turned on. This turns off the drive transistor N3. At the same time, the pull-down transistor N3 is turned on to pull down the GATE voltage and turn off the drive.

[0059] In addition, the specific working principle of segmented drive is as follows: by sampling the output drive GATE, the drive transistors N3 and N5 are turned on respectively, so that the output drive current gradually increases and the drive voltage rises slowly, thereby improving EMI.

[0060] Specifically, such as Figure 7As shown: The output drive voltage GATE is divided by resistors R1 and R2, resulting in an output voltage VO_ADOPT. This voltage is compared with the reference voltage VREF by comparator COMP, outputting the first drive control signal VCON1. ​​When comparator COMP outputs control signal VCON1 high, transistor N6 is turned on, and the drive current of N9 in its branch becomes M*I1, meaning the ratio of the drive current of N8 to the drive current of N9 is 1:M. Simultaneously, transistor N7 is turned off. The drive current of transistor P4 is M*N*I1, and the ratio of the drive current of P3 to the drive current of P4 is 1:N; this drives the gate of N5, causing its gate voltage to rise rapidly. When the drive voltage DU2 of N5 rises to VGS_N5+(R1+R2) / R2*VREF, the comparator COMP output VCON1 immediately goes low, turning off N6 and closing the charging path. VGS_N5 is the voltage value between the gate and source of N5. At the same time, pull-down transistor N7 turns on, pulling down the voltage of DU2 to turn off the driver transistor N5, thus completing the first stage of driving.

[0061] Upon completion of the first stage of driving, the comparator COMP1 output VCON1 goes low. At this time, the VO_ADOPT output voltage is (R1+R2) / R2*VREF. The PWM signal and the inverted VCON1 signal are ANDed together, and the output voltage VCON2 controls INV1 and inverter X1. When the upper transistor P1 of INV1 is turned on and the lower transistor N1 is turned off, the initial voltage at the positive terminal of the capacitor is VCC-VBE. When P1 is turned on, the negative terminal of the capacitor is charged to VCC, and the positive terminal of the capacitor is raised to 2VCC-VBE. Simultaneously, the upper transistor P2 of INV2 is turned on and the lower transistor N2 is turned off. The output voltage is 2VCC-VBE. When the driving transistor N3 is turned on, the driving current increases, and the output GATE voltage quickly rises from (R1+R2) / R2*VREF to 2VCC-VBE-VGS_N3. This allows the drive current to change from small to large, and the drive voltage to change from low to high in a slow and gradual manner, thereby reducing di / dt spikes and improving EMI performance.

[0062] In the specific implementation, since the width-to-length ratio of N3 and N5 is E:1, the drive current of N3 is E times that of N5. That is, the drive current of the second stage is E times that of the first stage. In this embodiment, the second stage drive circuit uses a BOOST circuit to boost the gate voltage of N3 to a maximum of 2VCC-VBE. When the external supply voltage decreases due to the output load and falls below 2VCC-VBE, the maximum output GATE voltage becomes VDD, which is higher than the traditional method without a boost circuit for VGS. This improves the output drive voltage and switching efficiency when the input voltage is low, and enhances the drive capability when VDD is low.

[0063] In this embodiment, a two-stage drive control and BOOST drive transistor gate voltage technology are employed, which improves EMI and increases the minimum drive voltage of the chip. This increases the drive capability at low input voltages while also improving the switching efficiency of the power transistor.

[0064] In this embodiment, to improve EMI performance, a segmented driving method can be employed in the power control chip's drive circuit. The main approach is segmented driving: the first segment uses a small current drive, and the second segment uses a large current drive. This reduces di / dt variations, allowing the power transistor's drive voltage to rise smoothly and improving the chip's EMI performance. Furthermore, the use of BOOST control technology ensures that the power transistor's drive voltage remains within a reasonable range.

[0065] In this embodiment, segmented driving and BOOST technology are employed. This improves the chip's EMI performance and ensures that the output drive voltage does not fall below the input voltage when the chip's input voltage is relatively low. This enhances the driving capability and efficiency of the power transistor.

[0066] The first power supply, second power supply, and third power supply can all be AC / DC power supplies, DC / DC power supplies, regulated power supplies, communication power supplies, modular power supplies, frequency converters, inverters, AC regulated power supplies, DC regulated power supplies, etc., and this application does not limit them. The first power supply and the second power supply can be the same power supply or different power supplies.

[0067] Furthermore, the power transistor outputs power to the electrical device to charge it. The electrical device can be understood as a device that needs to be charged by the user. User equipment can include, but is not limited to: smartphones, tablets, smart robots, smart elevators, in-vehicle equipment, wearable devices, smart home devices, computing devices or other processing devices connected to a wireless modem, as well as various forms of user equipment (UE), mobile station (MS), terminal device, etc.

[0068] In specific implementation, such as Figure 8 As shown, the waveforms of PWM, VCON1, VCON2, and GATE signals are displayed. It can be seen that the drive current can change from small to large, and the drive voltage can change from low to high in a slow, gradual manner. This reduces di / dt spikes and improves EMI performance.

[0069] Furthermore, the aforementioned drive circuit can be applied to a control chip circuit, which may include at least one of the following: AC-DC chip control circuit, DC-DC chip control circuit, linear power supply, etc., without limitation. The AC-DC chip control circuit may be a flyback AC-DC chip control circuit or a non-flyback AC-DC chip control circuit, which can better improve the insufficient drive voltage and EMI problems existing in the power supply.

[0070] Based on the above embodiments of this application, the driving circuit provided by this application can meet the wide input voltage requirements of PD fast charging and improve chip EMI, thereby achieving the purpose of improving the EMI effect of the power chip and meeting the wide range input voltage requirements of PD. It can improve the output driving voltage and switching efficiency while increasing the chip input voltage, and enhance the driving capability when the input voltage is low.

[0071] Furthermore, both the aforementioned drive circuit and the aforementioned control chip circuit can be applied to power adapters.

[0072] Of course, embodiments of this application also provide an electronic device, which may include, for example: Figure 5 The described drive circuit, chip control circuit, or power adapter, for example, an electronic device, can be a power bank or charger.

[0073] The above are the implementation methods of the embodiments of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the embodiments of this application, and these improvements and modifications are also considered to be within the protection scope of this application.

Claims

1. A driving circuit, characterized in that, The driving circuit includes: a first driving circuit and a second driving circuit, wherein... The first driving circuit is connected to the second driving circuit; the second driving circuit is used to drive the external power transistor to achieve the driving function; the driving current of the second driving circuit is E times the driving current of the first driving circuit, wherein E is greater than 1. The first driving circuit drives with a small current and the second driving circuit drives with a large current, and the two circuits realize the transition of current from small to large. The second driving circuit includes a boost circuit, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5; the boost circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a bipolar junction transistor (BJT), a first inverter group, a first capacitor C, a first resistor R1, and a second resistor R2. The first end of P1 is connected to the first end of N1; the second end of P1 is connected to the negative terminal of C and the third end of N1; the third end of P1 is connected to the first power supply VCC and the base and collector of the BJT; the emitter of the BJT is connected to the positive terminal of C and the second end of P2. The first terminal of P2 is connected to the first terminal of N2 and the output terminals of the first a1 inverters in the first inverter group, the first inverter group includes a inverters, a1 is less than a, and both a1 and a are odd numbers; the second terminal of P2 is also connected to the positive terminal of C; the third terminal of P2 is connected to the first terminal of N3 and the third terminal of N2; the output terminal of the first inverter group is connected to the first terminal of N4; the second terminals of N2 and N4 are grounded; The second terminal of N3 is connected to the third terminal of N4 and the second terminal of N5; the first terminal of N5 is used to connect to the output signal of the first segment of the driving circuit; the third terminals of N3 and N5 are both connected to the second power supply VDD; the second terminal of N5 is connected to one end of R1 and the driving port; the other end of R1 is connected to one end of R2 and is used to output the comparison voltage VO_ADOPT, and the other end of R2 is grounded; The first terminal of N1 is used to connect to the second input signal VCON2. VCON2 is the output signal obtained by passing the signal output from the output terminal of the AND gate circuit through the second inverter group. One input terminal of the AND gate circuit is input by the first input signal VCON1 through the third inverter group. The other input terminal of the AND gate circuit is used to input the drive signal. The second inverter group includes b inverters. The first input signal is the output signal of the comparator. The third inverter group includes c inverters, where b and c are both odd numbers. The second terminal of N1 is grounded. In an NMOS transistor, the first terminal is the gate, the second terminal is the source, the third terminal is the drain, and the fourth terminal is the substrate; in a PMOS transistor, the first terminal is the gate, the second terminal is the source, the third terminal is the drain, and the fourth terminal is the substrate.

2. The driving circuit according to claim 1, characterized in that, The first driving circuit includes: the comparator, the fourth inverter group, the first current amplifier circuit, the second current amplifier circuit, the sixth NMOS transistor N6, and the seventh NMOS transistor N7; the fourth inverter group includes d inverters, where d is an odd number; the first current amplifier circuit includes the third PMOS transistor P3, the fourth PMOS transistor P4, the third resistor R3, and the fourth resistor R4; the second current amplifier circuit includes the eighth NMOS transistor N8 and the ninth NMOS transistor N9; The non-inverting input of the comparator is connected to the third power supply, and the inverting input of the comparator is input to VO_ADOPT; the output of the comparator is connected to the first terminal of N6 and the input of the third inverter group; the output of the third inverter group is connected to the first terminal of N7. The second terminal of N6 is connected to the third terminal of N9; the third terminal of N6 is connected to one terminal of R3, and the other terminal of R3 is connected to the third terminal and the first terminal of P3; the first terminal of P3 is connected to the first terminal of P4; the second terminals of P3 and P4 are both connected to VDD; the third terminal of P4 is connected to one terminal of R4, and the other terminal of R4 is connected to the third terminal of N7 and outputs the output signal of the first segment drive circuit; the second terminal of N7 is grounded. The first terminal of N9 is connected to the first terminal of N8; the first and third terminals of N8 are used to connect to a current bias module to introduce bias current; the second terminal of N9 and the third terminal of N8 are both grounded.

3. The driving circuit according to claim 2, characterized in that, The comparator is used to compare the VO_ADOPT and the reference voltage VREF of the third power supply to obtain the first drive control signal. The VO_ADOPT is the voltage obtained by voltage division through R1 and R2. When the first segment drive control signal is high, N6 is turned on, the input current at the first terminal of N9 is M times the bias current, and at the same time, N7 is turned off, where M is greater than 1. After the output signal of the first driving circuit rises to a set value, it drives the first terminal of N5 to make the voltage of the first terminal of N5 rise rapidly. The set value is M*N times the bias current, where N is greater than 1. Drive the first terminal of N5 to cause the voltage of N5 to rise rapidly.

4. The driving circuit according to claim 3, characterized in that, When the voltage GATE of the output signal of the second stage driving circuit rises to the first preset threshold, the first input signal becomes low, and N6 is turned off to close the charging path. Simultaneously, pulling down N7 turns it on, lowering the voltage of the output signal of the first stage drive circuit, and turning off the drive of N5 to complete the first stage drive process.

5. The driving circuit according to claim 1 or 2, characterized in that, The P1 and N1 transistors constitute the first inverter; the P2 and N2 transistors constitute the second inverter.

6. The driving circuit according to claim 4, characterized in that, During the second stage of driving, the first inverter is used to turn on the upper transistor P1 and turn off the lower transistor N1; the initial voltage of the positive terminal of C is a first voltage value, which is equal to the difference between the voltage of the first power supply and the voltage of the VBE terminal of the BJT. When P1 is turned on, the negative terminal of the first capacitor is charged until the absolute value of the difference between its voltage and the voltage of the first power supply is less than a second preset threshold. Then, the positive terminal of the first capacitor is raised to a second voltage value, which is equal to twice the voltage of the first power supply and the voltage between the VBE terminal of the BJT. At the same time, the upper transistor P2 of the second inverter is turned on, and the lower transistor N2 is turned off, thus turning on the N3 driver.

7. A control chip circuit, characterized in that, The control chip circuit includes the drive circuit described in any one of claims 1-6.

8. A power adapter, characterized in that, The power adapter includes the drive circuit described in any one of claims 1-6, or the control chip circuit described in claim 7.

9. An electronic device, characterized in that, The electronic device includes a drive circuit as described in any one of claims 1-6, or a control chip circuit as described in claim 7, or a power adapter as described in claim 8.

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