analog / digital converter

Abstract

Analog / digital converter, high speed and small size. An analog / digital converter (1) converts an input analog potential (A in ) into a digital conversion value (CODE), wherein the analog / digital converter (1) has a comparator (2) that compares the input analog potential (A in ) with a reference potential (V ref ), and a time measurement circuit (4) that measures a comparison operation time from the start to the end of the comparison operation of the comparator (2), and outputs a digital conversion value (CODE) corresponding to the measured comparison operation time and the comparison result (Q) of the comparator (2).

Description

Technical Field

[0001] This invention relates to a method for processing input analog signals (input analog potential A). in Analog-to-digital converter that converts data into digital values. Background Technology

[0002] As an analog-to-digital converter (hereinafter referred to as an AD converter) that converts an input analog signal into a digital value, a flash-type AD converter is known (for example, see Patent Document 1). The flash-type AD converter has a resolution of n bits that is (2... n -1) comparison potentials and (2) n -1) comparators. Furthermore, the flash-type AD converter requires an input analog potential A. in Simultaneous potential comparison is performed in all comparators, and the corresponding values ​​from 0 to (2) are investigated. n Which of the following numeric values ​​is used to obtain the numeric value?

[0003] The advantage of a flash-type AD converter is that it can easily obtain the analog potential A relative to the input through a single comparator operation. in The digital value enables high-speed AD conversion. Because no analog potential A is required as an input. in Therefore, sampling is not required, so there is no need for sampling units (capacitors, switches, and units that control them), nor is there any time spent on sampling.

[0004] Furthermore, successive approximation type AD converters are known as AD converters (for example, see Patent Document 2). Successive approximation type AD converters, relative to a resolution of n bits, are determined by (2... n It consists of 10 capacitor elements and has an input analog potential A. in The system includes a sampling capacitor, a CDAC, a comparator, and a CDAC control circuit. Furthermore, the successive approximation type AD converter uses a binary search method, obtaining the digital value through n comparison operations.

[0005] The advantage of successive approximation AD converters is that a digital value can be obtained by performing n comparisons through one comparator, and the balance between circuit quantity, high speed, and power consumption is better.

[0006] As an AD converter, Wilkinson type AD converters (also known as voltage-to-time conversion type AD converters) are known (for example, see Patent Document 3).

[0007] Wilkinson type A / D converters have input analog potential A inThe capacitor used for charging (sampling) and the TDC circuit (Time to Digital Converter). Furthermore, the Wilkinson type AD converter converts the input analog potential A... in After the capacitor being charged (sampled) is disconnected (held) from the input, the charge stored in the capacitor is removed by a constant current, and the digital value is obtained by measuring the time until the charge becomes 0 (becomes 0V) through the TDC circuit.

[0008] The advantage of Wilkinson type ADCs is that they are expected to be ADCs with excellent differential linearity.

[0009] Patent Document 1: Japanese Patent Application Publication No. 01-103320

[0010] Patent Document 2: Japanese Patent Application Publication No. 2002-374169

[0011] Patent Document 3: Japanese Patent Application Publication No. 62-109434

[0012] However, a flash-type AD converter needs to be used to obtain (2 n -1) units of comparison potential and (2 n -1) comparators increase the size of the AD converter. For example, 4095 comparison potentials and 4095 comparators are needed to achieve 12-bit resolution in a flash AD converter.

[0013] Furthermore, successive approximation type AD converters in CDAC require (2 n The converter consists of several capacitors and analog switches. These components occupy a large area, thus increasing the size of the AD converter.

[0014] Furthermore, Wilkinson type A / D converters require input analog potential A. in The large capacitor used for sampling increases the size of the A / D converter. The capacitor in a Wilkinson type A / D converter needs to be a fraction of the converter's n-bit resolution (2^n). n The size of the capacitor increases exponentially as the resolution increases.

[0015] Due to the miniaturization of components, digital logic circuits have benefited from this, achieving miniaturization and high integration. However, analog circuits (especially components such as capacitors and resistors) are difficult to miniaturize, and the area of ​​analog circuits in the chip becomes relatively larger, which is the main reason for the increased price.

[0016] Furthermore, with the miniaturization of MOS components, the increased leakage current of MOS switches has become a problem. In successive approximation ADCs and Wilkinson converters, the combination of capacitors and MOS switches in the circuit leads to increased errors due to leakage current.

[0017] In addition, there are slope type, follower type (slope input type), VF conversion type, and ΔΣ type as AD converters, but these AD converters are small in size, but the conversion time is longer. Summary of the Invention

[0018] The purpose of this invention is to solve the above-mentioned problems of the prior art and provide a high-speed and small-size AD converter.

[0019] The present invention provides an analog-to-digital converter that converts an input analog potential into a digital value. The analog-to-digital converter is characterized by having:

[0020] A comparator that compares the input analog potential with a reference potential; and

[0021] The conversion circuit measures the comparison operation time from the start to the end of the comparison operation of the comparator, and outputs the digital conversion value corresponding to the measured comparison operation time and the comparison result of the comparator.

[0022] Furthermore, the AD converter of the present invention converts an input analog potential into a digital value, and the analog / digital converter is characterized by having:

[0023] Multiple comparators compare the input analog potential with multiple different reference potentials, respectively; and

[0024] A conversion circuit that outputs a digital conversion value corresponding to the comparison operation time from the start to the end of the comparison operation of the comparators, determined from the plurality of the comparators.

[0025] According to the present invention, since fewer comparators 2 can be used to complete one comparison operation and the AD conversion can be completed by processing the result, the AD converter 1 can be provided with high speed and small size. Attached Figure Description

[0026] Figure 1 This is a structural diagram showing the structure of the first embodiment of the AD converter of the present invention.

[0027] Figure 2 It is shown Figure 1 The circuit diagram shows an example of the comparator structure.

[0028] Figure 3 This is an explanation Figure 1 The waveform diagram shows the operation of the comparator and the termination detection circuit.

[0029] Figure 4 It is shown Figure 1 The diagram shows an example of the relevant characteristics of the comparator.

[0030] Figure 5 This is an explanation based on Figure 1 The diagram shows an example of calculating the input analog potential using the comparison action time in the time measurement circuit.

[0031] Figure 6 This is a structural diagram illustrating the structure of a second embodiment of the AD converter of the present invention.

[0032] Figure 7 It is shown Figure 6 The diagram shows an example of the relevant characteristics of the comparator.

[0033] Figure 8 This is a structural diagram illustrating the structure of the third embodiment of the AD converter of the present invention.

[0034] Figure 9 It is shown Figure 8 The diagram shows an example of the relevant characteristics of the comparator.

[0035] Figure 10 This is a structural diagram illustrating the structure of the fourth embodiment of the AD converter of the present invention.

[0036] Figure 11 It is shown Figure 10 The diagram shows an example of the relevant characteristics of the comparator.

[0037] Figure 12 This is a structural diagram illustrating the structure of the fifth embodiment of the AD converter of the present invention.

[0038] Figure 13 It is shown Figure 12 The circuit diagrams show examples of different types of comparators.

[0039] Figure 14 It is shown Figure 12 The diagram shows an example of the relevant characteristics of the comparator.

[0040] Label Explanation

[0041] 1. 1A, 1B, 1C, 1D: Analog-to-digital converter (AD converter); 2. 20~27, 2 A 2 A0 ~2 A2 2 B0 ~2 B11. Comparator; 2. 30-37: End detection circuit; 3. Time measurement circuit (TDC circuit); 4. 5A, 5B, 5C, 5D: Voltage divider circuit; 5. 60-63: Timer; 6. 7A, 7B, 7C, 7D: Decoder circuit; 7. 8B, 8C: Selection circuit; 8. 21, 23: Memory unit; 8. 22, 24: Power switch; 9. N1-N4, NT0-NT2: N-channel MOS transistors; 10. P1-P4, PT1-PT4: P-channel MOS transistors. Detailed Implementation

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, in the following embodiments, structures representing the same functions will be labeled with the same reference numerals, and descriptions will be omitted where appropriate.

[0043] (First Embodiment)

[0044] Reference Figure 1 The analog-to-digital converter 1 (hereinafter referred to as AD converter 1) of the first embodiment includes: a comparator 2, which compares the input analog potential A, which is input as an analog signal. in With reference potential V ref The circuit performs a comparison; the end detection circuit 3 detects the end of the comparison operation of the comparator 2; and the time measurement circuit 4 (hereinafter referred to as TDC circuit 4) measures the comparison operation time from the start to the end of the comparison operation of the comparator 2, and outputs a digital conversion value CODE corresponding to the measured comparison operation time and the comparison result Q of the comparator 2.

[0045] Comparator 2 has: a first input terminal, which is input with a lower limit reference potential V REFL ~Upper limit reference potential V REFH Input analog potential A in The second input terminal is set to the lower limit reference potential V. REFL ~Upper limit reference potential V REFH The potential between (in this embodiment, the lower limit reference potential V) REFL ~Upper limit reference potential V REFH The reference potential V at the center of the potential) ref ; Output terminal, its output input analog potential A in With reference potential V ref The comparison result Q; the inverting output terminal, which outputs the inverted output Q of the comparison result Q. - ; and a start signal input terminal, which receives the start signal START. - .

[0046] Comparator 2 is the start signal input to the start signal input terminal. -The comparator 2 is indicated by the START signal, which signals the start of the comparison. - When the voltage level changes from high (Hi) to low (Low), the input analog potential A is initially input to the first input terminal. in The reference potential V input to the second input terminal ref The comparison operation. Then, the analog potential A is input. in Reference potential V ref In this case, comparator 2 outputs "1" (high level Hi) from its output terminal as the comparison result Q, at the input analog potential A. in Reference potential V ref In the case of a condition, comparator 2 outputs "0" (low level) from the output terminal as the comparison result Q.

[0047] For example, such as Figure 2 As shown, comparator 2 can be constructed by adding a P-channel MOS transistor P0, which functions as a power switch 22, to a general CMOS SRAM memory cell 21. The gate of the P-channel MOS transistor P0 is connected to the input start signal START. - The start signal input terminal of comparator 2.

[0048] The memory cell 21 has P-channel MOS transistors P1 and P2 and N-channel MOS transistors N1, N2, N3 and N4.

[0049] P-channel MOS transistor P1 and N-channel MOS transistor N1 constitute the first CMOS inverter. The source of P-channel MOS transistor P1 is connected to the power supply voltage Vcc via power switch 22, and the drain of P-channel MOS transistor P1 is connected to the drain of N-channel MOS transistor N1. The source of N-channel MOS transistor N1 is connected to the ground voltage Vss.

[0050] P-channel MOS transistor P2 and N-channel MOS transistor N2 constitute the second CMOS inverter. The source of P-channel MOS transistor P2 is connected to the power supply voltage Vcc via power switch 22, and the drain of P-channel MOS transistor P2 is connected to the drain of N-channel MOS transistor N2. The source of N-channel MOS transistor N2 is connected to ground voltage Vss.

[0051] Furthermore, the connection point between the input of the first CMOS inverter (i.e., the gate of the P-channel MOS transistor P1 and the gate of the N-channel MOS transistor N1) and the output of the second CMOS inverter (i.e., the drain of the P-channel MOS transistor P1 and the drain of the N-channel MOS transistor N1) becomes the inverted output Q of the output comparison result Q. - The inverting output terminal of comparator 2.

[0052] Furthermore, the connection point between the input of the second CMOS inverter, namely the gate of the P-channel MOS transistor P2 and the gate of the N-channel MOS transistor N2, and the output of the first CMOS inverter, namely the drain of the P-channel MOS transistor P2 and the drain of the N-channel MOS transistor N2, becomes the output terminal of comparator 2, which outputs the comparison result Q.

[0053] N-channel MOS transistor N3 is connected in parallel with N-channel MOS transistor N1, and the gate of N3 becomes the input reference potential V. ref The second input terminal of comparator 2.

[0054] N-channel MOS transistor N4 is connected in parallel with N-channel MOS transistor N2, and the gate of N4 becomes the input analog potential A. in The first input terminal of comparator 2.

[0055] Reference Figure 3 At the start signal START - When the voltage level Hi is high, the P-channel MOS transistor P0, which acts as a power switch 22, is turned off, regardless of the input analog potential A. in Reference potential V ref How much potential does it have? Compare the result Q with the inverting output Q. - Both are "0" (low level). Additionally, in Figure 3 In the image, (a) shows the start signal START. - (a) shows the waveform of comparator 2, and (b) shows the output waveform of the end detection circuit 3.

[0056] When the start signal START - When the signal transitions to a low level (Low), the P-channel MOS transistor P0, acting as the power switch 22, turns on and applies the power supply voltage Vcc to the memory cell 21, initiating the comparison operation of comparator 2. That is, the start signal START, input to the start signal input terminal of comparator 2... - The moment when the high level (Hi) transitions to the low level (Low) marks the start of the comparison operation for comparator 2.

[0057] Memory cell 21, which is supplied with power supply voltage Vcc, wants to output Q inverted from the comparison result Q = 0. - The unstable state becomes the comparison result Q ≠ inverted output Q - The stable state. At this time, the input analog potential A in Reference potential V refIn this case, compared to N3, N4 has a larger current flowing through the ground voltage Vss. Therefore, the comparison result Q = inverted output Q. - The unstable state is disrupted, the comparison result Q becomes "1" (high level Hi), and the inverted output Q is activated. - It becomes stable when it becomes "0" (low level).

[0058] The detection circuit 3 ends based on the output of comparator 2 (comparison result Q, inverted output Q). - The circuit used to detect the end of the operation of comparator 2 can be constructed, for example, by an XOR logic circuit as follows: When the comparison result Q is compared with the inverted output Q... - If they are equal, output "0" (low level). When the comparison result Q is compared with the inverted output Q, output "0". - Under different conditions, the output is "1" (high level Hi). Figure 3 In the example shown, the output V of the end detection circuit 3 is... time The moment when the level changes from low (Low) to high (Hi) marks the end of the comparison operation of comparator 2.

[0059] like Figure 4 As shown, the comparison time of comparator 2, from the start time of the comparison action to the end time of the comparison action, is related to the input analog potential A. in and reference potential V ref The potential difference is related. A in and V ref The smaller the potential difference, the longer the comparison action time. in and V ref The larger the potential difference, the shorter the comparison action time. In other words, the comparison action time can also be compared with the input analog potential A. in and reference potential V ref Comparator 2 is related to the potential difference.

[0060] Additionally, in the comparator, the comparison operation time is compared with the input analog potential A, which is the object of comparison. in and reference potential V ref The correlation between the potential difference and the comparator is a characteristic that can also be seen in comparators such as general operational amplifiers. Therefore, if the comparison operation time is correlated with the potential difference between the input analog potential Ain and the reference potential Vref, which are being compared, then the comparator 2 in this embodiment is not limited to... Figure 2 The structure shown.

[0061] TDC circuit 4 has the function of measuring the comparison action time of comparator 2, and using the measured comparison action time and comparison result Q to calculate the input analog potential A.in The function of converting numbers to CODE values.

[0062] TDC circuit 4 measures the signal from the start signal START. - The start and end times of the operation of comparator 2 (from high level Hi to low level Low) are detected by the output V of detection circuit 3. time The time when comparator 2 finishes its operation from low level (Low) to high level (Hi) is taken as the comparison operation time.

[0063] TDC circuit 4 stores the input analog potential A. in and reference potential V ref The correlation between the potential difference and the comparison action time is used to calculate the input analog potential A. in The numerical conversion value CODE.

[0064] When the comparison result Q = "1" (high level Hi), TDC circuit 4 uses the input analog potential A. in Reference potential V ref Large areas ( Figure 4 The input analog potential A corresponding to the measured comparison action time is obtained by analyzing the relevant characteristics in region X shown. in The input analog potential A obtained by calculation in Convert the numerical value CODE and output it.

[0065] When the comparison result Q = "0" (low level), TDC circuit 4 uses the input analog potential A. in Reference potential V ref Small area ( Figure 4 The input analog potential A corresponding to the measured comparison action time is obtained by analyzing the relevant characteristics in the region Y shown. in The input analog potential A obtained by calculation in Convert the numerical value CODE and output it.

[0066] For example, when the comparison result Q = "0" and the measured comparison action time is "Ta", the TDC circuit 4 uses the correlation characteristics in region Y to determine the input analog potential A corresponding to the measured comparison action time = "Ta". in = "Va", the input analog potential A obtained from the calculation. in Convert the numeric value of “Va” to CODE and output it.

[0067] Regarding the determination of the input analog potential A in TDC circuit 4 based on the measured comparison action time. in The method can be achieved by pre-setting Figure 5The comparison action time and input analog potential A shown in (a) are shown. in The correlation characteristics between them are implemented as lookup tables and function storage. Furthermore, if the correlation characteristics are pre-stored as functions, it can be implemented as follows: Figure 5 As shown in (b), a linear approximation divided by several thresholds can also be as follows: Figure 5 (c) shows a logarithmic approximation divided by several thresholds.

[0068] After using Figure 2 In the case of comparator 2 shown, if the circuit is designed for excessively high speed, the comparison operation time relative to the input analog potential A will be too long. in The reduced variation in voltage leads to coarser resolution during AD conversion. Therefore, to achieve finer resolution, the comparison operation time of comparator 2 needs to be designed to be moderately longer. This can be achieved by reducing the drain current Ids of the N-channel MOS transistors N3 and N4 (reducing the form factor W / L and increasing L). Furthermore, the comparison operation time of comparator 2 can also be extended by uniformly reducing the drain current Ids of the P-channel MOS transistors P1 and P2 and the N-channel MOS transistors N1, N2, N3, and N4, or by adding capacitance to the nodes of the output terminals and the inverting output terminals.

[0069] In addition, when using Figure 2 In the case of comparator 2 shown, the input analog potential A in With reference potential V ref The smaller the potential difference, the shorter the comparison action time relative to the input analog potential A. in The greater the change, the greater the input analog potential A in With reference potential V ref The larger the potential difference, the longer the comparison action time relative to the input analog potential A. in The smaller the change, the better. Therefore, as an AD converter 1, the following problem exists: when the comparison operation time is not relative to the input analog potential A... in The input analog potential A changes significantly. in At the reference potential V ref In situations where the location is near the target area, it is difficult to use. The invention that solves this problem is the second embodiment described below.

[0070] (Second Implementation)

[0071] Reference Figure 6 The second embodiment of the AD converter 1A includes: a voltage divider circuit 5A, which generates a lower limit reference potential V. REFL ~Upper limit reference potential V REFH Multiple different reference potentials V ref0 ~V ref3Multiple comparators 20-23, which are used to input analog potential A in With multiple reference potentials V ref0 ~V ref3 The system includes: separate comparison circuits; multiple end detection circuits 30-33, which detect the end of the comparison operation of each comparator 20-23; timers 60-63, which measure the comparison operation time of each comparator 20-23; and a decoder circuit 7A, whose output is a count value selected from the count values ​​count0-count3 of each timer 60-63. * (Hereinafter, * indicates any one of the options) Comparator 2 is determined from the comparison results Q0 to Q3 of multiple comparators 20 to 23. * Comparison results Q * The calculated input analog potential A in The numerical conversion value CODE.

[0072] Reference Figure 7 The comparison action time (measured value) of comparators 20-23 is compared with the input analog potential A. in and reference potential V ref0 ~V ref3 The various potential differences are related, and the input analog potential A is related. in With reference potential V ref0 ~V ref3 The smaller the potential difference between each value, the faster the comparison action time (measured value) relative to the input analog potential A. in The greater the change, the better. Furthermore, the voltage divider circuit 5A, with the comparison operation time of each of the comparators 20-23 relative to the input analog potential A, exhibits different characteristics. in The variation is sufficiently large in the overlapping region to generate the reference potential V. ref0 ~V Ref3 .

[0073] Therefore, the measurement range of the AD converter 1A (lower limit reference potential V) can be increased. REFL ~Upper limit reference potential V REFH The entire region becomes the comparison action time relative to the input analog potential A. in The range of variation is sufficiently large. Additionally, the reference potential V... ref The number of comparators 2 and termination detection circuits 3 can be appropriately set according to the measurement range, required accuracy, etc.

[0074] The voltage divider circuit 5A can be constructed from voltage divider resistors, but resistors are components with large deviations and large layout dimensions. Therefore, it is preferable to construct the voltage divider circuit 5A from MOS components and diode components, as this can improve accuracy and reduce layout size.

[0075] Input the outputs V of multiple end detection circuits 30-33 into timers 60-63. time0 ~V time3 Start signal START - and clock signal CK.

[0076] Then, timers 60-63 measure the time from the start signal START. - The operation of comparators 60-63, which transition from high level (Hi) to low level (Low), starts at the time of operation and serves as the output V of multiple end-detection circuits 30-33. time0 ~V time03 The measured values ​​count0 to count3 up to the end of the transition from low level (Low) to high level (Hi) serve as the comparison operation times for each of the multiple comparators 20 to 23, and are output to the decoder circuit 7A.

[0077] like Figure 7 As shown, the decoder circuit 7A stores the input analog potential A. in and reference potential V ref0 ~V ref3 The correlation characteristics between the various potential differences and the comparison action times (measured values) in comparators 20-23. Decoder circuit 7A selects the largest measured value count from the measured values ​​count0-count3. * Comparator 2, which has the longest comparison time, is determined to be the largest. * Then, decoder circuit 7A uses the determined comparator 2. * Based on the relevant characteristics of the determined comparator 2 * Comparison results Q * and the selected measurement value count * Calculate the input analog potential A in The numerical conversion value CODE.

[0078] For example, in an unknown input analog potential A in yes Figure 7 In the case of Vb shown, the output V of the detection circuit 32 is terminated. time2 From the latest low level Low to the high level Hi, the decoder circuit 7A selects the measured value count2 = Tb measured by the timer 62. Furthermore, the decoder circuit 7A determines the comparator 22 with the longest comparison operation time.

[0079] Decoder circuit 7A in the determined comparator 2 * Comparison results Q * When = "1" (high level Hi), use the determined comparator 2. * Input analog potential A in Reference potential Vref* Large areas ( Figure 7 The area X shown * The relevant characteristics in the data are used to determine the input analog potential A corresponding to the selected comparison action time (measured value). in The input analog potential A obtained by calculation in Convert the numerical value CODE and output it.

[0080] Decoder circuit 7A in the determined comparator 2 * Comparison results Q * When the value is "0" (low level), the determined comparator 2 is used. * Input analog potential A in Reference potential V ref* Small area ( Figure 7 The region Y shown * The relevant characteristics in the data are used to determine the input analog potential A corresponding to the selected comparison action time (measured value). in The input analog potential A obtained by calculation in Convert the numerical value CODE and output it.

[0081] For example, in the determined comparator 2 * When the comparison result Q2 = "0" and the selected maximum comparison action time (measured value count2) is "Tb", the decoder circuit 7A uses the correlation characteristics in region Y2 to determine the input analog potential A corresponding to the measured comparison action time = "Tb". in = "Vb", the input analog potential A calculated by the operation. in Convert the numeric value CODE of "Vb" and output it.

[0082] (Third Implementation)

[0083] Reference Figure 8 The AD converter 1B of the third embodiment includes: a voltage divider circuit 5B, which generates a lower limit reference potential V. REFL ~Upper limit reference potential V REFH Multiple different reference potentials V ref0 ~V ref3 V ref0 -V ref1 intermediate potential V ref(0-1) V ref1 -V ref2 intermediate potential V ref(1-2) V ref2 -V ref3 intermediate potential V ref(2-3) Multiple comparators 20-23, which are used to input analog potential A inWith multiple reference potentials V ref0 ~V ref3 Compare separately; multiple comparators 2 A0 ~2 A2 They affect the input analog potential A in With intermediate potential V ref(0-1) V ref(1-2) V ref(2-3) The comparisons are performed separately; multiple end detection circuits 30-33 detect the end of the comparison operation of each comparator 20-23; a selection circuit 8B selects any one of the comparators 20-23; and a timer 6 measures the time of the comparator 20 selected by the selection circuit 8B. * The comparison operation time; and the decoder circuit 7B, whose output is based on the measured value count of timer 6 and the value of comparator 2 determined from multiple comparators 20 to 23. * Comparison results Q * The calculated input analog potential A in The numerical conversion value CODE.

[0084] Select circuit 8B is based on comparator 2. A0 ~2 A2 Comparison results Q A0 ~Q A2 Select any one of multiple comparators 20 to 23. The selection circuit 8B has AND circuits AND0 to AND3 and OR circuit OR.

[0085] Additionally, comparator 2 A0 ~2 A2 It can be in any form, but it uses a form that operates at a higher speed than comparators 20-24.

[0086] Input comparator 2 to the AND circuit AND0 A0 Comparison results Q A0 As the output V of the end detection circuit 30 time0 The selection signal in comparator 2 A0 Comparison results Q A0 When the value is "1", the output V of the detection circuit 30 is terminated. time0 The input is fed into timer 6 via the OR circuit.

[0087] Input comparator 2 to the AND circuit AND1 A1 Comparison results Q A1 = "1" and comparator 2 A0 Comparison results Q A0 The signal that equals "0" and becomes "1" (other combinations are "0") serves as the output V of the end detection circuit 31. time1 The selection signal in comparator 2A1 Comparison results Q A1 = "1" and comparator 2 A0 Comparison results Q A0 When the value is "0", the output V of the detection circuit 31 is terminated. time1 The input is fed into timer 6 via the OR circuit.

[0088] Input comparator 2 to the AND circuit A2 Comparison results Q A2 = "1" and comparator 2 A1 Comparison results Q A1 The signal that equals "0" and becomes "1" (other combinations are "0") serves as the output V of the end detection circuit 32. time2 The selection signal in comparator 2 A2 Comparison results Q A2 = "1" and comparator 2 A1 Comparison results Q A1 When the value is "0", the output V of the detection circuit 32 is terminated. time2 The input is fed into timer 6 via the OR circuit.

[0089] Input to comparator 2 in AND circuit AND2 A2 Comparison results Q A2 The signal obtained by reversing the signal is used as the output V of the end detection circuit 33. time3 The selection signal in comparator 2 A0 Comparison results Q A0 When the value is "0", the output V of the detection circuit 33 is terminated. time3 The input is fed into timer 6 via the OR circuit.

[0090] Therefore, when the analog potential A is input in Exceeding the intermediate potential V ref(0-1) In this case, circuit 8B selects comparator 20, and timer 6 measures the comparison operation time of comparator 20. When the input analog potential A... in Intermediate potential V ref(0-1) ~V ref(1-2) In this case, selection circuit 8B selects comparator 21, and timer 6 measures the comparison operation time of comparator 21. When the input analog potential A... in Intermediate potential V ref(1-2) ~V ref(2-3) In this case, circuit 8B selects comparator 22, and timer 6 measures the comparison operation time of comparator 22. When the input analog potential A... in Below the intermediate potential V ref(2-3)In this case, the selection circuit 8B selects comparator 23, and the timer 6 measures the comparison operation time of comparator 23.

[0091] like Figure 9 As shown, the decoder circuit 7B stores the input analog potential A. in and reference potential V ref0 ~V ref3 The correlation characteristics between the various potential differences and the comparison operation times (measured values) in comparators 20-23. Decoder circuit 7B uses comparator 2, which is determined according to the same logic as selection circuit 8B. * Based on the relevant characteristics, the output is determined according to the comparator 2. * Comparison results Q * The input analog potential A is calculated based on the measured value count of timer 6. in The numerical conversion value CODE.

[0092] (Fourth implementation)

[0093] Reference Figure 10 The AD converter 1C of the fourth embodiment includes: a voltage divider circuit 5C that generates a lower limit reference potential V. REFL ~Upper limit reference potential V REFH Multiple different reference potentials V ref0 ~V ref7 Multiple comparators 20-27, which are used to input analog potential A in With multiple reference potentials V ref0 ~V ref7 The comparisons are performed separately; multiple end detection circuits 30-37 detect the end of the comparison operation of each comparator 20-23; selection circuit 8C selects any one of the comparators 20-27; timer 6 measures the time of the comparator 2 selected by selection circuit 8B. * The comparison operation time; and the decoder circuit 7C, whose output is based on the measured value count of timer 6 and the value of comparator 2 determined from multiple comparators 20 to 27. * Comparison results Q * The calculated input analog potential A in The numerical conversion value CODE.

[0094] Selection circuit 8C selects any one of the comparators 20 to 27 based on the comparison results Q0 to Q7 of comparators 20 to 27. Selection circuit 8C has AND circuits AND0 to AND7 and OR circuits OR.

[0095] The comparison result Q0 of the AND circuit input comparator 20 is used as the output V of the end detection circuit 30. time0The selection signal, when the comparison result Q0 of comparator 20 is "1", ends the output V of detection circuit 30. time0 The input is fed into timer 6 via the OR circuit.

[0096] The comparison result Q1 of the input comparator 21 to the AND circuit is "1" and the comparison result Q0 of the input comparator 20 is "0", which becomes a signal of "1" (other combinations are "0"), and this is used as the output V of the end detection circuit 31. time1 The selection signal, when the comparison result Q1 of comparator 21 is "1" and the comparison result Q0 of comparator 20 is "0", ends the output V of detection circuit 31. time1 The input is fed into timer 6 via the OR circuit.

[0097] The comparison result Q2 of the input comparator 22 is "1" and the comparison result Q1 of the input comparator 21 is "0", which becomes a signal of "1" (other combinations are "0"), and this is used as the output V of the end detection circuit 32. time2 The selection signal, when the comparison result Q2 of comparator 22 is "1" and the comparison result Q1 of comparator 21 is "0", ends the output V of detection circuit 32. time2 The input is fed into timer 6 via the OR circuit.

[0098] The comparison result Q3 of the input comparator 23 to the AND circuit is "1" and the comparison result Q2 of the input comparator 22 is "0", which becomes a signal of "1" (other combinations are "0"), and this is used as the output V of the end detection circuit 33. time3 The selection signal, when the comparison result Q3 of comparator 23 is "1" and the comparison result Q2 of comparator 22 is "0", ends the output V of detection circuit 33. time3 The input is fed into timer 6 via the OR circuit.

[0099] The comparison result Q4 of the input comparator 24 to the AND circuit is "1" and the comparison result Q3 of the input comparator 23 is "0", which becomes the selection signal of "1" (other combinations are "0"), and serves as the output V of the end detection circuit 34. time4 The selection signal, when the comparison result Q4 of comparator 24 is "1" and the comparison result Q3 of comparator 23 is "0", terminates the output V of detection circuit 34. time4 The input is fed into timer 6 via the OR circuit.

[0100] The comparison result Q5 of the input comparator 25 to the AND circuit is "1", and the comparison result Q4 of the input comparator 24 is "0", which becomes a signal of "1" (other combinations are "0"), and this is used as the output V of the end detection circuit 35.time5 The selection signal, when the comparison result Q5 of comparator 25 is "1" and the comparison result Q4 of comparator 24 is "0", ends the output V of detection circuit 35. time5 The input is fed into timer 6 via the OR circuit.

[0101] The comparison result Q6 of the input comparator 26 to the AND circuit AND6 is "1" and the comparison result Q5 of the input comparator 25 is "0", which becomes the selection signal of "1" (other combinations are "0"), and serves as the output V of the end detection circuit 36. time6 The selection signal, when the comparison result Q6 of comparator 26 is "1" and the comparison result Q5 of comparator 25 is "0", terminates the output V of detection circuit 36. time6 The input is fed into timer 6 via the OR circuit.

[0102] The signal obtained by inverting the comparison result Q6 of comparator 26 input to AND7 circuit is used as the output V of end detection circuit 37. time7 The selection signal, when the comparison result Q6 of comparator 27 is "0", ends the output V of detection circuit 37. time7 The input is fed into timer 6 via the OR circuit.

[0103] Therefore, when the analog potential A is input in Exceeding the reference potential V ref0 In this case, the selection circuit 8C selects comparator 20, and the comparison operation time of comparator 20 is measured by timer 6. When the input analog potential A... in Reference potential V ref0 ~V ref1 In this case, the selection circuit 8C selects comparator 21, and the comparison operation time of comparator 21 is measured by timer 6. When the input analog potential A... in Reference potential V ref1 ~V ref2 In this case, the selection circuit 8C selects comparator 22, and the timer 6 measures the comparison operation time of comparator 22. When the input analog potential A... in Reference potential V ref2 ~V ref3 In this case, the selection circuit 8C selects comparator 23, and the comparison operation time of comparator 23 is measured by timer 6. When the input analog potential A... in Reference potential V ref3 ~V ref4 In this case, the selection circuit 8C selects comparator 24, and the comparison operation time of comparator 24 is measured by timer 6. When the input analog potential A... in Reference potential V ref4 ~Vref5 In this case, the selection circuit 8C selects comparator 25, and the comparison operation time of comparator 25 is measured by timer 6. When the input analog potential A... in Reference potential V ref5 ~V ref6 In this case, the selection circuit 8C selects comparator 26, and the timer 6 measures the comparison operation time of comparator 26. When the input analog potential A... in Below the reference potential V ref6 In this case, the selection circuit 8C selects comparator 27, and the timer 6 measures the comparison operation time of comparator 27.

[0104] like Figure 11 As shown, the decoder circuit 7C stores the input analog potentials A. in and reference potential V ref0 ~V ref7 The correlation characteristics between the various potential differences and the comparison operation times (measured values) in comparators 20-27. Decoder circuit 7C uses comparator 2, which is determined according to the same logic as selection circuit 8C. * The relevant characteristics of the output are based on the input analog potential A calculated from the measured value count of timer 6. in The numerical conversion value CODE.

[0105] like Figure 11 As shown, the decoder circuit 7C only uses the input analog potential A. in Reference potential V ref* Large areas ( Figure 7 The area X shown * The relevant characteristics in ) . In this case, after determining comparator 2 * Afterwards, it is possible to achieve this without using the comparison result Q. B* In this case, the digital conversion value CODE is calculated based on the count value measured by timer 6. Alternatively, only the input analog potential A can be used. in Reference potential V ref* Small area ( Figure 7 The region Y shown * The relevant characteristics in ).

[0106] (Fifth Embodiment)

[0107] Reference Figure 12 The AD converter 1D of the fifth embodiment includes: a voltage divider circuit 5D that generates a lower limit reference potential V. REFL ~Upper limit reference potential V REFH Between multiple different reference potentials V ref0 ~V ref3 V ref1 -Vref2 intermediate potential V ref(1-2) Multiple comparators 20-21, which are used to input analog potential A in and multiple reference potentials V ref0 ~V ref1 Compare them separately; Comparator 2 A Its response to the input analog potential A in With intermediate potential V ref1-2 Comparison; multiple comparators 2 B0 ~2 B1 They affect the input analog potential A in With multiple reference potentials V ref2 ~V ref3 The comparisons are performed separately; multiple end-of-life detection circuits 30-33, which respectively detect multiple comparators 20-21, 2... B0 ~2 B1 The comparison operations have ended; timers 60-63 respectively measure the operation of multiple comparators 20-21, 2... B0 ~2 B1 The comparison operation time; and the decoder circuit 7D, which is based on comparator 2 A Select the count from the measured values ​​count0 to count3 of timers 60 to 63. * And from multiple comparators 20-21, 2 B2 ~2 B3 Comparison results Q0~Q1, Q2 B2 ~Q B3 Comparator 2 determined in * Comparison results Q * Output the digital conversion value CODE.

[0108] As with the AD converter 1A in the second embodiment, the comparators 20 to 23 are configured as CMOS-type SRAMs, and the power supplies (power supply voltage Vcc, ground voltage Vss) are respectively connected to the reference power supply (upper limit reference potential V) for AD conversion. REFH Lower limit reference potential V REFL Under the same single power supply conditions, when the input analog potential A in and reference potential V ref3 When both sides are low, P1 and P2 of the P-channel MOS transistors cannot be fully turned on, and the circuit will become unstable.

[0109] Therefore, the AD converter 1D at the input analog potential A in In the lower region, comparator 2 will have a PMOS-type SRAM configuration. B0 ~2 B1 Used for AD conversion.

[0110] like Figure 13 As shown, comparator 2 B* The circuit is constructed by adding an N-channel MOS transistor NTO, which functions as a power switch 24, to a general PMOS SRAM memory cell 23. The gate of the N-channel MOS transistor NTO becomes a comparator 2 that receives the input start signal START. B* The start signal input terminal.

[0111] The memory cell 23 has N-channel MOS transistors NT1 and NT2 and P-channel MOS transistors PT1, PT2, PT3, and PT4.

[0112] P-channel MOS transistor PT1 and N-channel MOS transistor NT1 constitute the first CMOS inverter. The source of N-channel MOS transistor NT1 is connected to ground voltage Vss via power switch 24, and the drain of N-channel MOS transistor NT1 is connected to the drain of P-channel MOS transistor PT1. The source of P-channel MOS transistor PT1 is connected to power supply voltage Vcc.

[0113] P-channel MOS transistor PT2 and N-channel MOS transistor NT2 constitute the second CMOS inverter. The source of N-channel MOS transistor NT2 is connected to ground voltage Vss via power switch 24, and the drain of N-channel MOS transistor NT2 is connected to the drain of P-channel MOS transistor PT2. The source of P-channel MOS transistor PT2 is connected to power supply voltage Vcc.

[0114] Furthermore, the connection point between the input of the first CMOS inverter (i.e., the gate of the P-channel MOS transistor PT1 and the gate of the N-channel MOS transistor NT1) and the output of the second CMOS inverter (i.e., the drain of the P-channel MOS transistor PT1 and the drain of the N-channel MOS transistor NT1) becomes the output comparison result Q. B* Inverted output Q B* - Comparator 2 B* The inverting output terminal.

[0115] Furthermore, the connection point between the input of the second CMOS inverter (i.e., the gate of the P-channel MOS transistor PT2 and the gate of the N-channel MOS transistor NT2) and the output of the first CMOS inverter (i.e., the drain of the P-channel MOS transistor PT2 and the drain of the N-channel MOS transistor NT2) becomes the output comparison result Q. B* Comparator 2 B* The output terminals.

[0116] P-channel MOS transistor PT3 is connected in parallel with P-channel MOS transistor PT1, and the gate of P-channel MOS transistor PT3 becomes the input reference potential V. ref* Comparator 2 B* The second input terminal.

[0117] P-channel MOS transistor PT4 is connected in parallel with P-channel MOS transistor PT2. The gate of P-channel MOS transistor PT4 becomes the input analog potential A. in Comparator 2 B* The first input terminal.

[0118] Reference Figure 14 Comparators 20-21, 2 B0 ~2 B1 Comparison of action time and input analog potential A in and reference potential V ref0 ~V ref3 The various potential differences are related, and the input analog potential A is related. in With reference potential V ref0 ~V ref3 The smaller the potential differences between the input analog potentials, the shorter the comparison time relative to the input analog potential A. in The greater the change, the better. Furthermore, the voltage divider circuit 5D, with the comparison operation time of comparators 20-23 in their respective characteristics, relative to the input analog potential A... in The variation is sufficiently large in the overlapping region to generate the reference potential V. ref0 ~V ref3 .

[0119] In addition, in the case of 2 B* In all cases, when the input analog potential A is... in and reference potential V ref0 When both sides are high, the N-channel MOS transistors NT1 and NT2 cannot be fully turned on, and the circuit will become unstable.

[0120] In addition, such as Figure 14 As shown, regarding comparators 20-21 and 2 B0 ~2 B1 The correlation characteristics between action time and potential difference differ. Therefore, the decoder circuit 7D determines the input analog potential A based on the different characteristics of the action time and potential difference. in With intermediate potential V ref1-2 Comparator 2 for comparison A The output comparison result Q A Select comparators 20-21 and 2 B0 ~2 B1 Any one of them.

[0121] In comparator 2 AComparison results Q A When the signal is "1" (high level Hi), the decoder circuit 7D selects the largest measured value (count0-count3) from the comparator operation time measurements of comparators 20-21. * Comparator 2, which has the longest comparison time, is determined to be the largest. * Then, the decoder circuit 7D uses the determined comparator 2. * Based on the relevant characteristics of the determined comparator 2 * Comparison results Q * and the selected measurement value count * The operation inputs the digital conversion value CODE of the analog potential Ain.

[0122] The decoder circuit 7D is based on the determined comparator 2. * Comparison results Q * When = "1" (high level Hi), use the determined comparator 2. * Input analog potential A in Reference potential V ref* Large areas ( Figure 14 The area X shown * The relevant characteristics in the data are used to determine the input analog potential A corresponding to the selected comparison action time (measured value). in The input analog potential A obtained by calculation in Convert the numerical value CODE and output it.

[0123] Decoder circuit 7 in the determined comparator 2 * Comparison results Q * When the value is "0" (low level), the determined comparator 2 is used. * Input analog potential A in Reference potential V ref* Small area ( Figure 7 The region Y shown * The relevant characteristics in the data are used to determine the input analog potential A corresponding to the selected comparison action time (measured value). in The input analog potential A obtained by calculation in Convert the numerical value CODE and output it.

[0124] In comparator 2 A Comparison results Q A When the signal is "0" (low level), the decoder circuit 7D selects comparator 2. B0 ~2 B1 The largest of the measured values ​​count2 to count3 for comparing action times. *Comparator 2, which has the longest comparison time, is determined to be the largest. B* Then, the decoder circuit 7D uses the determined comparator 2. B* Based on the relevant characteristics of the determined comparator 2 B* Comparison results Q B* and the selected measurement value count * The operation inputs the digital conversion value CODE of the analog potential Ain.

[0125] The decoder circuit 7D is based on the determined comparator 2. B* Comparison results Q B* When = "1" (high level Hi), use the determined comparator 2. B* Input analog potential A in Reference potential V ref* Large areas ( Figure 14 The area X shown B* The relevant characteristics in the data are used to determine the input analog potential A corresponding to the selected comparison action time (measured value). in The input analog potential A obtained by calculation in Convert the numerical value CODE and output it.

[0126] Decoder circuit 7 in the determined comparator 2 B* Comparison results Q B* When the value is "0" (low level), the determined comparator 2 is used. B* Input analog potential A in Reference potential V ref* Small area ( Figure 7 The region Y shown B* The relevant characteristics in the data are used to determine the input analog potential A corresponding to the selected comparison action time (measured value). in The input analog potential A obtained by calculation in Convert the numerical value CODE and output it.

[0127] Additionally, comparator 2 A It can be in any form, but it is preferred to compare comparators 20-21 and 2. B0 ~2 B1 Perform the operation at high speed so that comparator 2 A The action time is not a bottleneck.

[0128] Furthermore, in the AD converter 1D, comparators 20-21 and 2 of different types (characteristics) are used. B0 ~2 B1Therefore, when using multiple comparators 2 of different types, it is necessary to select which type of comparator 2 to use to perform the A / D conversion. In this case, it can be done as with A / D converter 1B, based on the input analog potential A. in You can choose based on the combination of the comparison result Q of each comparator 2 and the comparison action time.

[0129] In the embodiments described above, a comparator 2 is configured to be determined. * According to the determined comparator 2 * The comparison operation time is used to calculate the digital conversion value CODE. However, it is also possible to determine multiple comparators 2. * According to multiple comparators 2 * The comparison operation time is used to calculate the digital conversion value CODE.

[0130] As explained above, according to this embodiment, an analog-to-digital converter 1 receives an input analog voltage A. in The analog-to-digital converter 1 converts the input analog potential A to a digital value CODE, wherein the analog-to-digital converter 1 has: a comparator 2 that adjusts the input analog potential A. in With reference potential V ref The circuit performs a comparison; and a conversion circuit (TDC circuit 4) that measures the comparison operation time from the start to the end of the comparison operation of comparator 2, and outputs a digital conversion value CODE corresponding to the measured comparison operation time and the comparison result Q of comparator 2.

[0131] Based on this structure, since one comparator 2 can be used to complete one comparison operation, and the AD conversion can be completed by processing the result, a high-speed and small-size AD converter 1 can be provided. AD converter 1 does not require (2...) for a resolution of n bits, unlike flash AD converters. n -1) comparators and (2) n -1) reference potential, and only comparator 2 and reference potential are needed, which can achieve a significant reduction in circuit area. In addition, the AD converter 1 does not have the sample-and-hold and large capacitor components for CDAC that are required for successive approximation AD converters, which can significantly reduce the circuit area and avoid the current leakage problem of MOS transistors. Moreover, the AD converter 1, as the main structural element, can be constructed from MOS transistors and diodes, taking advantage of the miniaturization of the manufacturing process.

[0132] Furthermore, according to this embodiment, the conversion circuit is based on the input analog potential A. in and reference potential V Ref The correlation between the potential difference and the comparison action time of comparator 2 is used to calculate the digital conversion value CODE based on the comparison action time.

[0133] Based on this structure, by comparing the action time with the input analog potential V... in and reference potential V ref The potential difference-dependent comparator 2 is capable of performing AD conversion with high precision.

[0134] Furthermore, according to this embodiment, an analog-to-digital converter 1A receives an input analog potential A. in The analog-to-digital converter 1A converts the input analog potential A into a digital value. The analog-to-digital converter 1A has multiple comparators 20-23 that respond to the input analog potential A. in With multiple different reference potentials V ref0 ~V ref3 The comparisons are performed separately; and a conversion circuit (decoder circuit 7A) is used, the output of which is compared with that of comparator 2 determined from a plurality of comparators 20 to 23. * The digital conversion value (CODE) corresponding to the comparison action time from start to finish.

[0135] According to this structure, since a comparison operation can be completed using fewer comparators 2 and the AD conversion can be completed by processing the result, a high-speed and small-sized AD converter 1 can be provided.

[0136] Furthermore, according to this embodiment, the conversion circuit stores the input analog potential A. in and reference potential V Ref0 ~V ref3 The correlation characteristics between each potential difference and the comparison operation time of the multiple comparators 20-23, based on the determined comparator 2 * Based on the relevant characteristics, the digital conversion value CODE is calculated according to the comparison action time.

[0137] Based on this structure, it is possible to compare the change in action time relative to the input analog potential A. in The correlation characteristics of a large area enable high-precision AD conversion.

[0138] Furthermore, according to this embodiment, the conversion circuit determines the comparator 2 based on the comparison operation time. * .

[0139] Based on this structure, the maximum measured value, count, is determined. * Comparator 2 * It can use the change in action time relative to the input analog potential A to compare the changes in action time. in The correlation characteristics of a large area enable high-precision AD conversion.

[0140] Furthermore, according to this embodiment, the conversion circuit (decoder circuit 7C) determines the comparator 2 based on the comparison results of the plurality of comparators 20 to 27. * Based on this structure, comparator 2 can be quickly determined with a simple structure. * .

[0141] Furthermore, according to this embodiment, comparator 2 has the function of an intermediate potential comparator. A0 ~2 A2 The comparator 2 A0 ~2 A2 For A in With reference potential V ref0 ~V ref3 Intermediate potential V ref(0-1) V ref(1-2) V ref(2-3) The comparison and conversion circuit (decoder circuit 7B) is based on comparator 2. A0 ~2 A2 The comparator is determined by comparing the results.

[0142] Based on this structure, comparator 2 can be quickly determined with a simple structure. * .

[0143] Furthermore, according to this embodiment, multiple comparators 20-21, 2 B0 ~2 B1 Composed of combinations of different types, the conversion circuit (decoder circuit 7D) determines the comparator 2, which functions as an intermediate potential comparator. A The type is selected based on the comparison results (comparator 20-21 or 2). B0 ~2 B1 Comparator *或B* .

[0144] According to this structure, since different types of comparators 2 can be used, it is possible to prevent the use of comparators 2 in unstable regions (potentials) and to perform AD conversion with high precision.

[0145] The present invention has been described above with specific embodiments. However, the above embodiments are only examples, and of course, modifications and implementations can be made without departing from the spirit of the present invention.

Claims

1. An analog-to-digital converter that converts an input analog potential into a digital value, the analog-to-digital converter being characterized by having: Multiple comparators compare the input analog potential with multiple different reference potentials, respectively; A conversion circuit that outputs a digital conversion value corresponding to the comparison operation time from the start to the end of the comparison operation of the comparators, determined from the plurality of comparators; and The termination detection circuit, composed of XOR logic circuitry, detects the end of the comparator's comparison operation. Each of the plurality of comparators includes a power switch composed of a P-channel MOS transistor and a memory cell of CMOS SRAM. In the comparator, the comparison time, from the start of the comparison operation to the end of the comparison operation, is related to the potential difference between the input analog potential and the reference potential. The smaller the potential difference between the input analog potential and the reference potential, the longer the comparison time; conversely, the larger the potential difference between the input analog potential and the reference potential, the shorter the comparison time. The conversion circuit stores various correlation characteristics between the potential difference between the input analog potential and the reference potential and the comparison action times of the plurality of comparators. Based on the correlation characteristics of the selected comparator, the digital conversion value is calculated according to the comparison action times. The conversion circuit determines the comparator based on the comparison operation time.

2. An analog-to-digital converter that converts an input analog potential into a digital value, the analog-to-digital converter being characterized by having: Multiple comparators compare the input analog potential with multiple different reference potentials, respectively; A conversion circuit that outputs a digital conversion value corresponding to the comparison operation time from the start to the end of the comparison operation of the comparators, determined from the plurality of comparators; and The termination detection circuit, composed of XOR logic circuitry, detects the end of the comparator's comparison operation. Each of the plurality of comparators includes a power switch composed of a P-channel MOS transistor and a memory cell of CMOS SRAM. In the comparator, the comparison time, from the start of the comparison operation to the end of the comparison operation, is related to the potential difference between the input analog potential and the reference potential. The smaller the potential difference between the input analog potential and the reference potential, the longer the comparison time; conversely, the larger the potential difference between the input analog potential and the reference potential, the shorter the comparison time. The conversion circuit stores various correlation characteristics between the potential difference between the input analog potential and the reference potential and the comparison action times of the plurality of comparators. Based on the correlation characteristics of the selected comparator, the digital conversion value is calculated according to the comparison action times. The analog-to-digital converter includes an intermediate potential comparator that compares the input analog potential with an intermediate potential between a plurality of reference potentials. The conversion circuit determines the comparator based on the comparison result of the intermediate potential comparator. The comparators are composed of combinations of different types. The conversion circuit determines the type of comparator selected based on the comparison result of the intermediate potential comparator.

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