A low-power single-slope ADC circuit based on clock locking
By using a clock-locked, low-power two-step single-slope ADC circuit structure, the problem of high power consumption in traditional single-slope ADCs is solved, achieving reduced power consumption and improved device portability.
CN116015305BActive Publication Date: 2026-06-12DALIAN UNIV OF TECH
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- DALIAN UNIV OF TECH
- Filing Date
- 2022-12-12
- Publication Date
- 2026-06-12
Smart Images
Figure CN116015305B_ABST
Abstract
The application provides a low-power single-ramp ADC circuit based on clock locking, and belongs to the field of analog integrated circuits. The low-power single-ramp ADC circuit comprises a ramp generation circuit, a sample-and-hold circuit, a comparator, three registers, an inverter and a switch. PIXEL As a non-inverting input terminal of the comparator, V RAMP As an inverting input terminal of the comparator. According to the basic property of the comparator, if the input signal V PIXEL is greater than the comparison signal V RAMP , the output V COMP_out of the comparator is high; if the input signal V PIXEL is less than the comparison signal, the output V COMP_out of the comparator is low. The application adopts a dichotomy method to determine the range corresponding to the input voltage, shorten and lock the working interval of the counter, reduce the switching power consumption of the counter, and further reduce the power consumption of the single-ramp ADC.
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