Image sensing device and operating method thereof

Abstract

The present application relates to an image sensing device and an operation method thereof. An image sensing device is disclosed, which includes: a plurality of selectors that generate a plurality of selected pixel signals corresponding to one of a plurality of pixel signals; a plurality of signal converters that: set a plurality of initial voltages different from each other based on a plurality of initialization signals during an initialization period, and generate a plurality of converted pixel signals reflecting the plurality of initial voltages respectively based on a plurality of selected pixel signals and a ramp signal during a readout period; and a calculation circuit that averages the plurality of converted pixel signals.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to semiconductor design technology, and more particularly, to an image sensing device and an operating method thereof. Background Art

[0002] An image sensing device is a device that captures an image using the characteristics of a semiconductor that reacts to light. Image sensing devices can be roughly divided into charge coupled device (CCD) image sensing devices and complementary metal oxide semiconductor (CMOS) image sensing devices. Recently, CMOS image sensing devices are widely used because they enable both analog control circuits and digital control circuits to be directly implemented on a single integrated circuit (IC). Summary of the invention

[0003] Various embodiments of the present disclosure are directed to an image sensing device for reducing noise included in a pixel signal.

[0004] According to an embodiment of the present disclosure, an image sensing device may include: a plurality of selectors, which generate a plurality of selected pixel signals corresponding to one of a plurality of pixel signals; a plurality of signal converters, which: set a plurality of initial voltages different from each other based on a plurality of initialization signals during an initialization period, and generate a plurality of converted pixel signals respectively reflecting the plurality of initial voltages based on a plurality of selected pixel signals and a ramp signal during a readout period; and a calculation circuit, which averages the plurality of converted pixel signals.

[0005] According to an embodiment of the present disclosure, an image sensing device may include: a pixel array that generates multiple pixel signals; a selection circuit that generates multiple selected pixel signals corresponding to at least one of the multiple pixel signals; a signal conversion circuit that sets multiple initial voltages based on a ramp signal and multiple initialization signals during an initialization period, and generates multiple converted pixel signals that respectively reflect the multiple initial voltages based on the multiple selected pixel signals and the ramp signal during a readout period; and a calculation circuit that averages the multiple converted pixel signals.

[0006] According to an embodiment of the present disclosure, an operating method of an image sensing device may include: setting multiple initial voltages; generating multiple selected pixel signals respectively reflecting the multiple initial voltages; generating multiple digital signals based on the multiple selected pixel signals and a ramp signal; and calculating an average value of the multiple digital signals.

[0007] According to an embodiment of the present disclosure, an image sensing device may include: a timing control circuit that generates M initialization signals that remain enabled for different amounts of time during an initialization period; M converters, each of the M converters including: a comparator that generates a corresponding comparison signal at an output node by comparing a ramp signal provided to a first input node and a comparison pixel signal provided to a second input node; a switch that connects the output node and the second input node while a corresponding one of the initialization signals remains enabled; a capacitive circuit that is connected between the second input node and a node through which a pixel signal is provided during a readout period; a counter that generates a corresponding converted pixel signal based on the corresponding comparison signal and a clock signal; and a calculator that averages the M converted pixel signals to generate an average pixel signal including average noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating an image sensing device according to an embodiment of the present disclosure.

[0009] Figure 2 is an example of an embodiment according to the present disclosure Figure 1 The circuit diagram of the signal conversion group is shown in .

[0010] Figure 3 is an example of an embodiment according to the present disclosure Figure 1 0 is a timing diagram of the operation of the image sensing device shown in .

[0011] Figure 4 is a diagram illustrating noise included in a pixel signal according to an embodiment of the present disclosure.

[0012] Figure 5 is an example of an embodiment according to the present disclosure Figure 1 Flowchart of the operation of the image sensing device shown in . DETAILED DESCRIPTION

[0013] Various embodiments of the present disclosure are described below with reference to the accompanying drawings in order to describe the present disclosure in detail so that a person skilled in the art to which the present disclosure belongs can easily realize the technical spirit of the present disclosure.

[0014] It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected to or directly coupled to the other element, or electrically connected to or coupled to the other element with one or more elements interposed therebetween. In addition, it should be understood that the use of the terms "comprises," "comprising," "includes," and "comprising" in this specification does not exclude the presence of one or more other elements, but may further include or have one or more other elements, unless otherwise specified. Throughout the description of the specification, some components are described in the singular, but the present disclosure is not limited thereto, and it should be understood that components may be formed in the plural.

[0015] Figure 1 is a block diagram illustrating an image sensing device 100 according to an embodiment.

[0016] Reference Figure 1 , the image sensing device 100 may include a pixel array 110 , a selection circuit 120 , a signal conversion circuit 130 , a calculation circuit 140 , a ramp signal generation circuit 150 , and a timing control circuit 160 .

[0017] The pixel array 110 may include a plurality of pixels PX disposed at intersections of a plurality of rows and a plurality of columns. The plurality of pixels PX may output a plurality of pixel signals VPX through a plurality of column lines during a plurality of row line periods. <11> To VPX <nm>For example, pixels arranged in a first row among the plurality of pixels PX may output a plurality of pixel signals VPX through a plurality of column lines during a first row line period. <11> To VPX <nm>, and the pixels arranged in the second row among the plurality of pixels PX may output a plurality of pixel signals VPX through a plurality of column lines during a second row line period <11> To VPX <nm>. Multiple pixel signals VPX <11> To VPX <nm>Each of can be an analog signal.

[0018] The selection circuit 120 can select a plurality of pixel signals VPX according to the mode. <11> To VPX <nm>and outputs the selected pixel signal as a plurality of selected pixel signals VSIG through a plurality of selection lines. <11> To VSIG <nm>For example, the selection circuit 120 can be configured to select a plurality of pixel signals VPX in a normal mode. <11> To VPX <nm>One-to-one corresponds to a plurality of selection lines to output a plurality of selected pixel signals VSIG <11> To VSIG <nm>, and in multi-sampling mode by making multiple pixel signals VPX <11> To VPX <nm>At least one of them corresponds to multiple selection lines one by one to output multiple selected pixel signals VSIG <11> To VSIG <nm>.

[0019] The selection circuit 120 may include first to Nth selection groups SG1 to SGN, where "N" is a natural number equal to or greater than 1. The first to Nth selection groups SG1 to SGN may include first to Mth selectors S11 to S1M, ..., and SN1 to SNM, respectively, where "M" is a natural number equal to or greater than 2. The first selection group SG1 is representatively described among the first to Nth selection groups SG1 to SGN. The first to Mth selectors S11 to S1M included in the first selection group SG1 may be respectively connected to output first to Mth pixel signals VPX in a plurality of column lines. <11> The first to Mth column lines connected to VPX<1M> and respectively connected to the output first to Mth selected pixel signals VSIG in a plurality of selection lines <11> The first to Mth selectors S11 to S1M may couple the first to Mth column lines to the first to Mth select lines in a one-to-one manner in the normal mode and couple one of the first to Mth column lines to the first to Mth select lines in the multi-sampling mode.

[0020] The signal conversion circuit 130 may set the first to Mth initial voltages based on the ramp signal VRMP and the first to Mth initialization signals AZ<1:M> during the initialization period P1, and may generate the first to Mth initial voltages based on the plurality of selected pixel signals VSIG during the readout period P2. <11> to VSIG<1M> and the ramp signal VRMP to generate a plurality of converted pixel signals D reflecting the first to Mth initial voltages. <11> To D <nm>. A plurality of converted pixel signals D <11> To D <nm>Each of can be a digital signal.

[0021] The signal conversion circuit 130 may include first to Nth signal conversion groups AG1 to AGN. The first to Nth signal conversion groups AG1 to AGN may include first to Mth signal converters ADC11 to ADC1M, ..., and ADCN1 to ADCNM, respectively. The first signal conversion group AG1 is representatively described among the first to Nth signal conversion groups AG1 to AGN. The first to Mth signal converters ADC11 to ADC1M included in the first signal conversion group AG1 may receive corresponding first to Mth selected pixel signals VSIG <11> to VSIG<1M> and the corresponding first to Mth initialization signals AZ<1:M>, receive the common ramp signal VRMP, and generate the first to Mth converted pixel signals D <11> To D<1M>.

[0022] The calculation circuit 140 may be enabled in the multi-sampling mode and disabled in the normal mode. The calculation circuit 140 may calculate a plurality of converted pixel signals D for each group. <11> To D <nm>The average value of , to generate the first to Nth average pixel signals AD<1:N>. That is, the calculation circuit 140 can generate the first average pixel signal AD <1> As a set of converted pixel signals D <11> The average value of D<1M> to D<1M> generates a second average pixel signal AD <2> As a set of converted pixel signals D <21> to D<2M>, and generates the Nth average pixel signal AD <n>As a set of converted pixel signals D <n1>To D <nm>For example, the calculation circuit 140 may calculate the average value of the first to Mth converted pixel signals D output from the first signal conversion group AG1. <11> to D<1M> to generate a first average pixel signal AD <1> , and the first to Mth converted pixel signals D output from the Nth signal conversion group AGN can be calculated <n1>To D <nm>The average value of the pixel signal AD is generated by <n>The first average pixel signal AD <1> The first average pixel signal AD may correspond to a pixel signal VPX<1x> corresponding to a pixel selected by the first selection group SG1. <1> It can be a signal in which noise derived (or caused) from one pixel (hereinafter referred to as "pixel noise") and noise derived from or related to the first signal conversion group AG1 (hereinafter referred to as "conversion noise") are reduced compared to a pixel signal VPX<1x>.

[0023] The ramp signal generating circuit 150 may generate a ramp signal VRMP that ramps at a predetermined slope during the initialization period P1 and ramps at a predetermined pattern during the readout period P2. For example, the ramp signal VRMP may ramp within a first voltage range during the initialization period P1, ramp within a second voltage range during a reset period P21 of the readout period P2, and ramp within a third voltage range different from the second voltage range during a signal period P22 of the readout period P2 (see Figure 3 ). The first voltage range may be the same as or different from the second voltage range. For example, the first voltage range may be equal to or less than the second voltage range. The slope of the ramp signal VRMP generated during the initialization period P1 and the slope of the ramp signal VRMP generated during the reset period P21 may be the same as or different from each other.

[0024] The timing control circuit 160 may generate first to Mth initialization signals AZ<1:M> that are sequentially deactivated during the initialization period P1. For example, the first initialization signal AZ among the first to Mth initialization signals AZ<1:M> may be deactivated first. <1> , and the M-th initialization signal AZ among the first to M-th initialization signals AZ<1:M> may be deactivated last. <m>.

[0025] Figure 2 is an example of an embodiment according to the present disclosure Figure 1 0 is a circuit diagram of an example of the first signal conversion group AG1 shown in FIG.

[0026] The first signal conversion group AG1 may include first to Mth signal converters ADC11 to ADC1M.

[0027] The first signal converter ADC11 may include a first comparator CP11 , a first switch SW11 , a first capacitor C11 , and a first counter CNT11 .

[0028] The first comparator CP11 can receive the ramp signal VRMP through its positive input terminal (+), and receive the first comparison pixel signal V <11> and outputs a first comparison signal C through its output terminal <11> The first comparator CP11 can compare the ramp signal VRMP with the first comparison pixel signal V <11> Compare and generate a first comparison signal C corresponding to the comparison result <11> .

[0029] The first switch SW11 may be coupled between the negative input terminal (-) and the output terminal. The first switch SW11 may be switched based on the first initialization signal AZ <1> For example, the first switch SW11 can be switched based on the activated first initialization signal AZ <1> The first switch is turned on and the first initialization signal AZ is deactivated. <1> The first switch is open.

[0030] The first capacitor C11 may be connected between the negative input terminal (-) and the first selected pixel signal VSIG. <11> The first capacitor C11 may initialize the negative input terminal (-) to a first initial voltage during the initialization period P1. For example, the first capacitor C11 may sample a first initial voltage corresponding to the voltage level of the ramp signal VRMP when the first switch SW11 is open in the initialization period P1, and may sample a first initial voltage corresponding to the voltage level of the ramp signal VRMP during the readout period P2 by sampling the first selected pixel signal VSIG. <11> Sampling is performed, and a first comparison pixel signal V reflecting a first initial voltage is generated through a negative input terminal (-) <11> .

[0031] The first counter CNT11 can be based on the first comparison signal C <11> and a clock signal (not shown) to generate a first converted pixel signal D <11> .

[0032] The second signal converter ADC12 may include a second comparator CP12 , a second switch SW12 , a second capacitor C12 , and a second counter CNT12 .

[0033] The second comparator CP12 can receive the ramp signal VRMP through its positive input terminal (+), and receive the second comparison pixel signal V <12> , and outputs a second comparison signal C through its output terminal <12> The second comparator CP12 can compare the ramp signal VRMP with the second comparison pixel signal V <12> , and generates a second comparison signal C corresponding to the comparison result <12> .

[0034] The second switch SW12 may be connected between the negative input terminal (-) and the output terminal. The second switch SW12 may be switched based on the second initialization signal AZ <2> For example, the second switch SW12 can be switched based on the activated second initialization signal AZ <2> and short-circuited, and based on the deactivated second initialization signal AZ <2> And open the way.

[0035] The second capacitor C12 may be connected between the negative input terminal (-) and the second selected pixel signal VSIG. <12> The second capacitor C12 can initialize the negative input terminal (-) to a second initial voltage during the initialization period P1. For example, the second capacitor C12 can sample the second initial voltage corresponding to the voltage level of the ramp signal VRMP when the second switch SW12 is open in the initialization period P1, and can sample the second initial voltage corresponding to the voltage level of the ramp signal VRMP during the readout period P2 by sampling the second selected pixel signal VSIG. <12> Sampling is performed, and a second comparison pixel signal V reflecting the second initial voltage is generated through the negative input terminal (-) <12> The second initial voltage may have a lower level than the first initial voltage.

[0036] The second counter CNT12 can be based on the second comparison signal C <12> and the clock signal to generate a second converted pixel signal D <12> .

[0037] The Mth signal converter ADC1M may include an Mth comparator CP1M, an Mth switch SW1M, an Mth capacitor C1M, and an Mth counter CNT1M.

[0038] The Mth comparator CP1M may receive the ramp signal VRMP through its positive input terminal (+), receive the Mth comparison pixel signal V<1M> through its negative input terminal (-), and output the Mth comparison signal C<1M> through its output terminal. The Mth comparator CP1M may compare the ramp signal VRMP with the Mth comparison pixel signal V<1M>, and generate the Mth comparison signal C<1M> corresponding to the comparison result.

[0039] The Mth switch SW1M may be coupled between the negative input terminal (-) and the output terminal. The Mth switch SW1M may be switched based on the Mth initialization signal AZ <m>For example, the Mth switch SW1M can be switched based on the activated Mth initialization signal AZ <m>and short-circuited and based on the disabled Mth initialization signal AZ <m>And open the way.

[0040] The Mth capacitor C1M may be coupled between the negative input terminal (-) and the output terminal of the Mth selected pixel signal VSIG<1M>. The Mth capacitor C1M may initialize the negative input terminal (-) to the Mth initial voltage during the initialization period P1. For example, the Mth capacitor C1M may sample the Mth initial voltage corresponding to the voltage level of the ramp signal VRMP when the Mth switch SW1M is open in the initialization period P1, and generate the Mth comparison pixel signal V<1M> reflecting the Mth initial voltage through the negative input terminal (-) by sampling the Mth selected pixel signal VSIG<1M> during the readout period P2.

[0041] The Mth counter CNT1M may generate an Mth converted pixel signal D<1M> based on the Mth comparison signal C<1M> and the clock signal.

[0042] In the following, reference is made to Figures 3 to 5 The operation of the image sensing device 100 having the above configuration according to the embodiment will be described. For example, Figures 3 to 5 is a diagram illustrating an operation according to a multi-sampling mode, and in particular, an operation associated with the first signal conversion group AG1 .

[0043] Figure 3 is an example of an embodiment according to the present disclosure Figure 1 1 is a timing diagram of an operation method of the image sensing device 100 shown in FIG.

[0044] Reference Figure 3 During the initialization period P1, the ramp signal generating circuit 150 may generate a ramp signal VRMP ramped within a first voltage range. The first voltage range may be equal to or less than the second voltage range. The ramp signal VRMP generated during the initialization period P1 may have the same or different slope as the ramp signal VRMP generated during the reset period P21. For example, the slope of the ramp signal VRMP generated during the initialization period P1 may be steeper or gentler than the slope of the ramp signal VRMP generated during the reset period P21. The ramp signal VRMP may have a gradually decreasing voltage level.

[0045] During the initialization period P1, the timing control circuit 160 may generate first to Mth initialization signals AZ which are sequentially disabled. <1> To AZ <m>For example, in the first to Mth initialization signals AZ <1> To AZ <m>The first initialization signal AZ may be disabled first. <1> , and the Mth initialization signal AZ may be disabled last <m>Therefore, the first to M-th signal converters ADC11 to ADC1M may respectively generate the first to M-th initialization signals AZ based on the ramp signal VRMP and the first to M-th initialization signals VRMP. <1> To AZ <m>To set the first to M-th initial voltages with different voltage levels. For example, the first to M-th signal converters ADC11 to ADC1M can sample the first to M-th initial voltages as the first to M-th comparison pixel signals V <11> The voltage level difference GDN among the first to Mth initialization voltages may correspond to the first to Mth initialization signals AZ <1> To AZ <m>The first to Mth initialization signals AZ may be determined or adjusted according to the slope of the ramp signal VRMP generated during the initialization period P1. <1> To AZ <m>The deactivation time interval GT in.

[0046] During the readout period P2, the timing control circuit 160 may maintain the first to Mth initialization signals AZ <1> To AZ <m>The ramp signal generating circuit 150 may generate a ramp signal VRMP that ramps in a predetermined pattern. For example, the ramp signal generating circuit 150 may generate a ramp signal VRMP that ramps in a second voltage range during a reset period P21 of the readout period P2, and ramps in a third voltage range during a signal period P22 of the readout period P2. The ramp signal VRMP may have a gradually decreasing voltage level during the reset period P21, and have a gradually decreasing voltage level during the signal period P22.

[0047] During the readout period P2, the pixel array 110 may generate first to M-th pixel signals VPX from pixels arranged in one row. <11> For example, the pixel array 110 may generate the first to Mth pixel signals VPX corresponding to the reset level during the reset period P21. <11> to VPX<1M>, and generates first to M-th pixel signals VPX corresponding to the signal levels during the signal period P22 <11> To VPX<1M>.

[0048] During the readout period P2, the first to Mth selectors S11 to S1M may select the first to Mth pixel signals VPX <11> A pixel signal corresponding to a predetermined pixel in VPX<1M> (eg, VPX <11> ), and generates a pixel signal corresponding to the selected pixel (eg, VPX <11> ) of the first to Mth selected pixel signals VSIG <11> to VSIG<1M>.

[0049] During the readout period P2, the first to M-th signal converters ADC11 to ADC1M may respectively generate a signal based on the ramp signal VRMP and the first to M-th selected pixel signals VSIG. <11> to VSIG<1M> to generate the first to Mth converted pixel signals D reflecting the first to Mth initial voltages <11> For example, the first to M-th signal converters ADC11 to ADC1M may generate first to M-th comparison pixel signals V reflecting the first to M-th initial voltages. <11> The first to M-th signal converters ADC11 to ADC1M may respectively convert the first to M-th comparison pixel signals V <11> to V<1M> are compared with the ramp signal VRMP, and the first to Mth converted pixel signals D corresponding to the comparison results are generated. <11> Subsequently, the first to M-th signal converters ADC11 to ADC1M may convert the first to M-th comparison pixel signals V <11> to V<1M> are compared with the ramp signal VRMP, and the first to Mth converted pixel signals D corresponding to the comparison results are generated. <11> To D<1M>.

[0050] The first to Mth comparison pixel signals V <11> Each of V<1M> to V<1M> may include pixel noise VnPIX derived from one pixel. Since the pixel noise VnPIX is thermal noise that varies randomly, the first to Mth comparison pixel signals V <11> VnPIX1 to VnPIXM may include pixel noises having different analog levels (hereinafter referred to as "first to Mth comparison noises VnPIX1 to VnPIXM"). In addition, the first to Mth converted pixel signals D <11> D<1M> to D<1M> may include first to Mth conversion noises VnADC1 to VnADCM, respectively, each of which has a digital level derived from the first to Mth signal converters ADC11 to ADC1M. The first to Mth conversion noises VnADC1 to VnADCM may also be randomly varying thermal noises.

[0051] During the readout period P2 or a subsequent period of the readout period P2, the calculation circuit 140 may calculate the first to Mth converted pixel signals D <11> to D<1M>, and generates a first average pixel signal AD <1> The first to Mth comparison noises VnPIX1 to VnPIXM and the first to Mth conversion noises VnADC1 to VnADCM may be included in the first average pixel signal AD <1> However, the first to Mth comparison noises VnPIX1 to VnPIXM and the first to Mth conversion noises VnADC1 to VnADCM may be unrelated by the calculation circuit 140 .

[0052] In an embodiment, the first to M-th pixel signals VPX may be read after the readout period P2. <11> To other pixel signals in VPX<1M> (e.g., VPX <12> The operation of the readout period P2 is repeated from VPX<1M> to VPX<1M>. Alternatively, in an embodiment, the first to M-th pixel signals VPX<1M> may be processed after the readout period P2. <11> To other pixel signals in VPX<1M> (e.g., VPX <12> to VPX<1M>) repeatedly perform the operation of the initialization period P1 and the operation of the readout period P2.

[0053] Figure 4 is an example of an embodiment of the present disclosure including a first average pixel signal AD <1> A diagram of the noise in (hereinafter referred to as “first average noise Vn1”).

[0054] refer to Figure 4 The calculation circuit 140 can generate a first average pixel signal AD corresponding to one pixel through an addition operation ∑ and a division operation 1 / M. <1> The first average pixel signal AD <1> A first average noise Vn1 may be included. The relationship between the first average noise Vn1, the first to M-th pixel noises VnPIX1 to VnPIXM, and the first to M-th conversion noises VnADC1 to VnADCM may be expressed as shown in the following equation 1 (here, VnPIX1≡…≡VnPIXM≡VnPIX, VnADC1≡…≡VnADCM≡VnADC, where “≡” indicates that the corresponding standard deviations of the noises are the same as each other).

[0055] [Equation 1]

[0056]

[0057] In this document, the symbol "ˉ" may refer to an average value. The first average noise Vn1 may be obtained using the root mean square (RMS). The first average noise Vn1 may reduce the pixel noise VnPIX and the conversion noise VnADC by (1 / √M) times. It can be seen that the larger "M" is, the smaller the first average noise Vn1 is.

[0058] Figure 5 is an example of an embodiment according to the present disclosure Figure 1 Flow chart of the operating method of the image sensing device 100 shown in FIG.

[0059] Reference Figure 5 The operating method of the image sensing device (100) may include: setting first to Mth initial voltages in operation S101, generating first to Mth selected pixel signals VSIG reflecting the first to Mth initial voltages respectively in operation S103. <11> to VSIG<1M>, based on the first to Mth selected pixel signals VSIG in operation S105 <11> to VSIG<1M> and the ramp signal to generate the first to Mth converted pixel signals (ie, digital signals) D <11> to D<1M>, and the first to Mth converted pixel signals D are calculated in operation S107. <11> to the average value of D<1M>.

[0060] First to Mth selected pixel signals VSIG <11> to VSIG<1M> may correspond to a pixel signal (ie, a first pixel signal VPX) generated from one pixel. <11> ). A pixel signal (ie, the first pixel signal VPX <11> ) may correspond to calculating the first to Mth converted pixel signals D <11> to D<1M> and obtain a signal (ie, a first average pixel signal AD <1> The one signal (ie, the first average pixel signal AD <1> ) corresponds to a signal from which noise derived from one pixel has been removed.

[0061] According to an embodiment of the present disclosure, noise included in a pixel signal may be reduced, and in particular, pixel noise may be reduced as a result of combining a plurality of initialization signals that are sequentially deactivated and a ramp signal that gradually ramps to a lower voltage level.

[0062] According to an embodiment of the present disclosure, noise included in a pixel signal can be reduced, which makes it possible to improve a signal-to-noise ratio of the pixel signal.

[0063] Although the present disclosure has been illustrated and described with respect to specific embodiments, the disclosed embodiments are provided for description and are not intended to be limiting. In addition, it should be noted that, as will be appreciated by those skilled in the art in light of the present disclosure, the present disclosure may be implemented in various ways by substitutions, changes and modifications falling within the scope of the appended claims. In addition, the embodiments may be combined to form additional embodiments.

[0064] CROSS-REFERENCE TO RELATED APPLICATIONS

[0065] This application claims priority to Korean Patent Application No. 10-2021-0139399 filed on October 19, 2021, the disclosure of which is incorporated herein by reference in its entirety.< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / nm> < / nm> < / n> < / nm> < / nm> < / nm> < / nm> < / nm> < / nm> < / nm> < / nm> < / nm> < / nm> < / nm> < / nm> < / nm>

Claims

1. An image sensing device, the image sensing device include: a plurality of selectors that generate a plurality of selected pixel signals corresponding to one of the plurality of pixel signals; A plurality of signal converters, wherein the plurality of signal converters: setting a plurality of initial voltages different from each other based on the ramp signal and the plurality of initialization signals during the initialization period, and generating a plurality of converted pixel signals respectively reflecting the plurality of initial voltages based on the plurality of selected pixel signals and the ramp signal during a readout period; as well as a calculation circuit that averages the plurality of converted pixel signals, Wherein, each of the plurality of signal converters comprises: a comparator that compares the ramp signal input through its positive input terminal with a comparison pixel signal input through its negative input terminal and outputs a comparison signal corresponding to a result of the comparison through its output terminal; and A capacitor is coupled to the negative input terminal and initializes the negative input terminal to a corresponding initial voltage during the initialization period.

2. The image sensing device according to claim 1, further comprising: include: a ramp signal generating circuit that generates the ramp signal, the ramp signal ramping during the initialization period in which the plurality of converted pixel signals are not generated, and ramping in a predetermined pattern during the readout period; as well as A timing control circuit generates a plurality of initialization signals during the initialization period, the plurality of initialization signals being sequentially deactivated.

3. The image sensing device according to claim 2, in, The ramp signal ramps within a first voltage range during the initialization period, ramps within a second voltage range during a reset period of the readout period, and ramps within a third voltage range during a signal period of the readout period.

4. The image sensing device according to claim 3, in, The first voltage range is the same as or different from the second voltage range, and the third voltage range is different from the second voltage range.

5. The image sensing device according to claim 1, in, Each of the plurality of signal converters further comprises: a switch coupling the negative input terminal and the output terminal based on a corresponding initialization signal among the plurality of initialization signals, The capacitor generates the comparison pixel signal reflecting the corresponding initial voltage by sampling the corresponding selected pixel signal during the readout period.

6. An image sensing device, the image sensing device include: A pixel array, wherein the pixel array generates a plurality of pixel signals; a selection circuit that generates a plurality of selected pixel signals through a plurality of selection lines by making the plurality of pixel signals correspond one-to-one to the plurality of selection lines in a first mode, and generates the plurality of selected pixel signals through the plurality of selection lines by making at least one of the plurality of pixel signals correspond one-to-many to the plurality of selection lines in a second mode; a signal conversion circuit that sets a plurality of initial voltages different from each other based on a ramp signal and a plurality of initialization signals during an initialization period, and generates a plurality of converted pixel signals that respectively reflect the plurality of initial voltages based on the plurality of selected pixel signals and the ramp signal during a readout period; as well as a calculation circuit that averages the plurality of converted pixel signals, Wherein, the signal conversion circuit includes a plurality of signal converters, each of the plurality of signal converters includes: a comparator that compares the ramp signal input through its positive input terminal with a comparison pixel signal input through its negative input terminal and outputs a comparison signal corresponding to a result of the comparison through its output terminal; and A capacitor is coupled to the negative input terminal and initializes the negative input terminal to a corresponding initial voltage during the initialization period.

7. The image sensing device according to claim 6, further comprising: include: a ramp signal generating circuit that generates a ramp signal that ramps during the initialization period and ramps in a predetermined pattern during the readout period; as well as A timing control circuit generates the plurality of initialization signals during the initialization period, the plurality of initialization signals being sequentially deactivated.

8. The image sensing device according to claim 7, in, The ramp signal ramps within a first voltage range during the initialization period, ramps within a second voltage range during a reset period of the readout period, and ramps within a third voltage range during a signal period of the readout period.

9. The image sensing device according to claim 8, in, The first voltage range is the same as or different from the second voltage range, and the third voltage range is different from the second voltage range.

10. The image sensing device according to claim 6, in, Each of the plurality of signal converters further comprises: a switch coupling the negative input terminal and the output terminal based on a corresponding initialization signal among the plurality of initialization signals, The capacitor generates the comparison pixel signal reflecting the corresponding initial voltage by sampling the corresponding selected pixel signal during the readout period.

11. An operating method of an image sensing device, the operating method The following steps are involved: The plurality of signal converters are used to set a plurality of initial voltages different from each other based on the ramp signal and the plurality of initialization signals; generating, by a plurality of selectors, a plurality of selected pixel signals respectively reflecting the plurality of initial voltages, wherein the plurality of selected pixel signals correspond to one pixel signal generated from one pixel; generating, by the plurality of signal converters, a plurality of digital signals based on the plurality of selected pixel signals and a ramp signal; and calculating an average value of the plurality of digital signals by a calculation circuit, wherein the one pixel signal corresponds to one signal obtained by calculating the average value of the plurality of digital signals, and wherein the one signal corresponds to a signal from which noise derived from the one pixel has been removed, Wherein, each of the plurality of signal converters comprises: a comparator that compares the ramp signal input through its positive input terminal with a comparison pixel signal input through its negative input terminal and outputs a comparison signal corresponding to a result of the comparison through its output terminal; and A capacitor is coupled to the negative input terminal and initializes the negative input terminal to a corresponding initial voltage during an initialization period.

12. An image sensing device, the image sensing device include: a plurality of selectors that generate a plurality of selected pixel signals corresponding to one of the plurality of pixel signals; a timing control circuit that generates M initialization signals that respectively remain enabled for different amounts of time during an initialization period; as well as M converters, the M converters setting a plurality of initial voltages different from each other based on a ramp signal and the M initialization signals during the initialization period, each of the M converters comprising: a comparator, the comparator generating a corresponding comparison signal at an output node by comparing the ramp signal provided to the first input node with the comparison pixel signal provided to the second input node; a switch coupling the output node and the second input node while a corresponding one of the initialization signals remains enabled; a capacitive circuit coupled between the second input node and a node through which the selected pixel signal is provided during a readout period; a counter that generates a corresponding converted pixel signal reflecting the initial voltage based on the corresponding comparison signal and a clock signal; and A calculator averages the M converted pixel signals to generate an average pixel signal including average noise.

13. The image sensing device according to claim 12, in, The average noise is expressed by the following equation: Here, "ˉ" represents an average value, "Vn1" represents an average noise, "VnPIX" represents thermal noise included in a pixel signal, and "VnADC" represents thermal noise caused by each of the converters.

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