Display panel and display device

Abstract

The application provides a display panel and a display device, and belongs to the technical field of display. In the display panel, the driving power line and the pull-down power line coupled with the pixel each include at least two metal layers stacked in sequence, each two adjacent metal layers are coupled with each other, and the orthographic projection of one metal layer on the substrate covers the orthographic projection of other metal layers on the substrate except the metal layer. Since the driving power line and the pull-down power line are each implemented by multiple metal layers, the impedance of the driving power line and the impedance of the pull-down power line are both small. Correspondingly, the voltage drop at both ends of the driving power line and the voltage drop at both ends of the pull-down power line are both small, that is, the voltage loss of the driving voltage and the voltage loss of the pull-down voltage are both low, thereby the power consumption and loss of the display panel during operation can be effectively reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are widely used in various display devices due to their advantages such as self-illumination, small thickness, light weight and high luminous efficiency.

[0003] In related technologies, OLED display panels generally include multiple pixels. Each pixel is coupled to a driving power line (i.e., VDD line) and a pull-down power line (i.e., VSS line), and can emit light under the driving voltage provided by the driving power line and the pull-down voltage provided by the pull-down power line.

[0004] However, OLED display panels in related technologies consume a lot of power and have high losses when they are working. Summary of the Invention

[0005] This application provides a display panel and a display device, which can solve the problems of high power consumption and high loss during operation of display panels in related technologies. The technical solution is as follows:

[0006] On one hand, a display panel is provided, the display panel comprising:

[0007] Substrate;

[0008] In addition, a driving power line, a pull-down power line, and a plurality of pixels are located on one side of the substrate; each pixel is coupled to the pull-down power line and the driving power line respectively, and is used to emit light under the driving voltage provided by the driving power line and the pull-down voltage provided by the pull-down power line.

[0009] The driving power line and the pull-down power line each include: at least two metal layers stacked sequentially in a direction away from the substrate, and a first insulating layer located between each pair of adjacent metal layers. Each pair of adjacent metal layers is coupled through a via penetrating the first insulating layer. Among the at least two metal layers, the orthographic projection of the target metal layer on the substrate covers the orthographic projection of other metal layers on the substrate except for the target metal layer.

[0010] Optionally, the target metal layer is located on the side of the other metal layers away from the substrate.

[0011] Optionally, the number of metal layers included in the drive power line is the same as the number of metal layers included in the pull-down power line.

[0012] Optionally, both the drive power line and the pull-down power line include two metal layers.

[0013] Optionally, the pixel includes: an active layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, which are sequentially stacked along a direction away from the substrate;

[0014] The driving power line includes two metal layers that are located in the same layer as the first source / drain metal layer and the second source / drain metal layer, respectively.

[0015] The pull-down power cable includes two metal layers that are located on the same layer as the first source / drain metal layer and the second source / drain metal layer, respectively.

[0016] Optionally, the number of metal layers included in the pull-down power line is greater than the number of metal layers included in the drive power line.

[0017] Optionally, the drive power line includes two metal layers. The pull-down power line includes three metal layers.

[0018] Optionally, the pixel includes: an active layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer, which are sequentially stacked along a direction away from the substrate;

[0019] The driving power line includes two metal layers that are located in the same layer as the first source / drain metal layer and the second source / drain metal layer, respectively.

[0020] The three metal layers included in the pull-down power cable are located on the same layer as the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer.

[0021] Optionally, the display panel further includes: a data line located on one side of the substrate, each pixel being coupled to the data line and used to emit light under the drive of the driving voltage, the pull-down voltage, and the data signal provided by the data line;

[0022] The data line and the third source / drain metal layer are located in the same layer.

[0023] Optionally, each pixel includes: a pixel circuit and a light-emitting element, wherein the pixel circuit is coupled to the driving power line and the first electrode of the light-emitting element respectively, the second electrode of the light-emitting element is coupled to the pull-down power line, and the first electrode and the second electrode of the light-emitting element are arranged sequentially in a direction away from the at least two metal layers;

[0024] The display panel further includes: a transfer electrode and a second insulating layer, wherein the transfer electrode is located on the same layer as the first electrode of the light-emitting element and is coupled to the second electrode of the light-emitting element, and the second insulating layer is located between the transfer electrode and the at least two metal layers;

[0025] In the pull-down power line, which includes at least two metal layers, the metal layer closest to the adapter electrode is coupled to the adapter electrode through a via penetrating the second insulating layer.

[0026] Optionally, the display panel is a flexible organic light-emitting diode (OLED) display panel.

[0027] Optionally, the substrate has a display area and a peripheral area surrounding the display area;

[0028] The drive power line is located in the display area, and the pull-down power line is located in the peripheral area.

[0029] On the other hand, a display device is provided, the display device comprising: a driver integrated circuit, and a display panel as described above;

[0030] The driver integrated circuit is coupled to the drive power line and pull-down power line in the display panel. The driver integrated circuit is used to transmit drive voltage to the drive power line and pull-down voltage to the pull-down power line.

[0031] In summary, the beneficial effects of the technical solutions provided in this application embodiment can include at least the following:

[0032] A display panel and a display device are provided. In the display panel, the driving power line and pull-down power line for pixel coupling each include at least two metal layers stacked sequentially. Each pair of adjacent metal layers is coupled to each other, and the orthogonal projection of one metal layer on the substrate covers the orthogonal projections of all other metal layers on the substrate. Since both the driving power line and the pull-down power line are implemented with multiple metal layers, the impedance of both the driving power line and the pull-down power line is relatively small. Correspondingly, the voltage drop across the driving power line and the voltage drop across the pull-down power line are both small, that is, the voltage loss of the driving voltage and the voltage loss of the pull-down voltage are both low, thereby effectively reducing the power consumption and losses during the operation of the display panel. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0035] Figure 2 This is a cross-sectional view of a display panel provided in an embodiment of this application;

[0036] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of this application;

[0037] Figure 4 This is a cross-sectional view of another display panel provided in an embodiment of this application;

[0038] Figure 5 This is a cross-sectional view of a pixel provided in an embodiment of this application;

[0039] Figure 6 This is a cross-sectional view of another display panel provided in the embodiments of this application;

[0040] Figure 7 This is a cross-sectional view of another pixel provided in an embodiment of this application;

[0041] Figure 8 This is a schematic diagram of the structure of another display panel provided in the embodiments of this application;

[0042] Figure 9 This is a schematic diagram of a pixel structure provided in an embodiment of this application;

[0043] Figure 10 This is a schematic diagram of another pixel structure provided in an embodiment of this application;

[0044] Figure 11 This is a structural layout of a pixel circuit provided in an embodiment of this application;

[0045] Figure 12 This is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0046] Figure 13 This is a schematic diagram of another display device provided in an embodiment of this application.

[0047] Explanation of icon numbers:

[0048] 00 - Display panel, 10 - Driver integrated circuit;

[0049] 01-Substrate, 02-Pixel, 03-Metal layer, 04-First insulating layer, 05-Transfer electrode, 06-Second insulating layer, ILD-Interlayer stabilizing layer, 07-Crack dam, 08-Crack detection circuit, 09-Blocking dam, k0-Through-through-first insulating layer 04, k1-Through-through-second insulating layer, EL-Light emitting layer;

[0050] VDD - Drive power line, VSS - Pull-down power line, V1 - Reset power line, RE1 - Reset line, G1 - Gate line, D1 - Data line, EM - Light control line, VGH - First power line, VGL - Second power line;

[0051] 021-Pixel circuit, 022-Light-emitting element, T0-Driving transistor, T1-Data writing transistor, T2-Compensation transistor, T3-First reset transistor, T4-Second reset transistor, T5-First light-emitting control transistor, T6-Second light-emitting control transistor, C1-Storage capacitor;

[0052] P1 - Active layer, GATE1 - First gate metal layer, GATE2 - Second gate metal layer, SD1 - First source / drain metal layer, SD2 - Second source / drain metal layer, SD3 - Third source / drain metal layer, BUFFER - Buffer layer, GI1 - First gate insulating layer, GI1 - Second gate insulating layer, ILD - Interlayer stabilizing layer, PLN1 - First planarization layer, PLN2 - Second planarization layer, PLN3 - Third planarization layer, EOA - Light emission control driving circuit, GOA - Gate driving circuit, ESD - Electrostatic discharge component, FPC - Flexible printed circuit board, F1 - First fan-out region, F2 - Second fan-out region. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0054] The terminology used in the embodiments section of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. For example, the words "first," "second," and "third," and similar terms used in the embodiments and claims of this application do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similarly, the words "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The words "comprising" or "including," and similar terms mean that the elements or objects preceding "comprising" or "including" cover the elements or objects listed after "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The words "connected" or "coupled," and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," and "right," etc., are only used to indicate relative positional relationships, and the relative positional relationships may also change accordingly when the absolute position of the described object changes. The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0055] For OLED display panels, each pixel contains a current-driven OLED device, meaning the brightness of the pixel is determined by the magnitude of the driving current flowing through it. Generally, a larger driving current results in brighter light emission, while a smaller driving current results in dimmer light emission. The magnitude of the driving current depends on the voltage difference between the driving voltage Vdd provided by the VDD line coupled to the pixel and the pull-down voltage Vss provided by the VSS line coupled to the pixel: Vdd - Vss. Generally, a larger voltage difference results in a larger driving current, and a smaller voltage difference results in a smaller driving current. Furthermore, both the VDD and VSS lines are coupled to a driver integrated circuit (IC). The driving voltage Vdd transmitted from the VDD line to the pixel and the pull-down voltage Vss transmitted from the VSS line to the pixel both originate from this driver IC. Due to the impedance of the VDD line, the driving voltage Vdd ultimately transmitted from the VDD line to the pixel is generally less than the voltage provided by the driver IC to the VDD line; that is, there is a certain voltage drop across the VDD line. Furthermore, the higher the impedance of the VDD line, the greater the voltage drop across the VDD line, and correspondingly, the smaller the driving voltage Vdd transmitted from the VDD line to the pixel. In other words, the greater the voltage loss provided by the driver IC to the VDD line, the greater the power loss of the driver IC. The same applies to the VSS line, and will not be elaborated further here.

[0056] Based on the above analysis, taking the VDD line as an example, given a fixed demand for driving current and a relatively high impedance, the driver IC needs to provide a larger voltage to the VDD line. This results in higher power consumption for the driver IC, leading to higher power consumption and poorer battery life for the OLED display panel. Tests show that if the driving voltage Vdd transmitted to the pixels is set to 4.6 volts (V) and the pull-down voltage Vss is -3V (i.e., Vdd - Vss = 4.6 + 3 = 7.6V), then under the test conditions of displaying a 255-level grayscale white image on a 6.7-inch OLED display panel with a brightness of 500 nits and a refresh rate of 60 Hz, the power consumption of this OLED display panel is approximately 1.72 watts (W).

[0057] This application provides a display panel in which the impedance of both the VDD and VSS lines is low. This results in lower power loss and reduced power consumption during operation, thus improving the display panel's battery life.

[0058] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. For example... Figure 1 As shown, the display panel 00 includes: a substrate 01, and a driving power line VDD (i.e., VDD line), a pull-down power line VSS (i.e., VSS line) and a plurality of pixels 02 located on one side of the substrate 01.

[0059] Each pixel 02 is coupled to a driving power line VDD and a pull-down power line VSS, and emits light under the driving voltage provided by the driving power line VDD and the pull-down voltage provided by the pull-down power line VSS. Based on the above analysis, the brightness of pixel 02 is positively correlated with the voltage difference between the driving voltage and the pull-down voltage. That is, the larger the voltage difference, the brighter the light emission; the smaller the voltage difference, the dimmer the light emission.

[0060] It should be noted that the reference Figure 1 As can be seen, the display panel can include one pull-down power line VSS and multiple drive power lines VDD, and the multiple pixels O2 included in the display panel can be arranged in an array. Based on this, the number of drive power lines VDD included in the display panel can be equal to the number of columns of the multiple pixels O2, and pixels O2 located in the same column can be coupled to the same drive power line VDD.

[0061] exist Figure 1 Based on, and refer to Figure 2As shown in the cross-sectional view of the display panel, the drive power line VDD and pull-down power line VSS described in this application embodiment both include: at least two metal layers 03 stacked sequentially in a direction away from the substrate 01, and a first insulating layer 04 located between each pair of adjacent metal layers 03. Each pair of adjacent metal layers 03 is coupled through a via k0 penetrating the first insulating layer 04 (the first insulating layer 04 refers to the first insulating layer 04 located between the two metal layers 03 to be coupled). Furthermore, among the at least two metal layers 03, the orthographic projection of the target metal layer 03 on the substrate 01 covers the orthographic projections of the other metal layers 03 on the substrate 01.

[0062] For example, refer to Figure 2 The drive power line VDD and pull-down power line VSS shown both include two metal layers 03 and a first insulating layer 04 located between the two metal layers 03. The two metal layers 03 are coupled through a via k0 penetrating the first insulating layer 04. Furthermore, the orthogonal projection of the metal layer 03 furthest from the substrate 01 onto the substrate 01 covers the metal layer 03 closest to the substrate 01. That is, the metal layer 03 furthest from the substrate 01 is the target metal layer 03.

[0063] Since parallel metal layers can reduce the impedance of signal lines, and the larger the overlap area of ​​the two parallel metal layers, the smaller the impedance of the resulting signal line, the impedance of the driving power line VDD and the pull-down power line VSS provided in this embodiment are both low. Therefore, combined with the above analysis, it can be seen that the voltage drop across the driving power line VDD and the pull-down power line VSS are both small, meaning that the voltage loss of the driving voltage and the voltage loss of the pull-down voltage are both small. Consequently, to drive pixel O2 to achieve a certain luminous brightness, the voltages supplied by the driving IC to the driving power line VDD and the pull-down power line VSS can be set relatively small, resulting in low power consumption during driving IC operation. Correspondingly, the display panel has low power consumption and strong battery life.

[0064] In summary, this application provides a display panel. In this display panel, both the driving power line and the pull-down power line for pixel coupling include at least two sequentially stacked metal layers. Each pair of adjacent metal layers is coupled to each other, and the orthogonal projection of one metal layer onto the substrate covers the orthogonal projections of all other metal layers on the substrate. Since both the driving power line and the pull-down power line are implemented using multiple metal layers, the impedance of both the driving power line and the pull-down power line is relatively low. Consequently, the voltage drop across the driving power line and the pull-down power line is also relatively low, meaning that the voltage loss of the driving voltage and the voltage loss of the pull-down voltage are both low, thereby effectively reducing the power consumption and losses during the operation of the display panel.

[0065] Figure 3This is a schematic diagram of the structure of another display panel provided in an embodiment of this application. For example... Figure 3 As shown, the substrate 01 may have a display area A1 and a peripheral area A2 surrounding the display area A1.

[0066] In this embodiment of the application, the multiple drive power lines VDD can be located in the display area A1, and the pull-down power line VSS can be located in the peripheral area A2.

[0067] As an optional implementation, in this embodiment, the number of metal layers 03 included in the drive power line VDD can be the same as the number of metal layers 03 included in the pull-down power line VSS.

[0068] Example, Figure 4 It shows Figure 3 The image shows a cross-sectional view of the display panel in the MM' direction. (Combined with...) Figure 2 and Figure 4 As can be seen, the driving power line VDD and pull-down power line VSS described in the embodiments of this application can both include two metal layers 03. Correspondingly, the display panel can include only a first insulating layer 04 located between the two metal layers 03.

[0069] Based on this, refer to Figure 5 As shown in the pixel schematic diagram, the pixel 02 described in this application embodiment may include: an active layer P1, a first gate metal layer GATE1, a second gate metal layer GATE2, a first source / drain metal layer SD1, and a second source / drain metal layer SD2, which are sequentially stacked along a direction away from the substrate 01.

[0070] Combined Figure 4 It can be seen that the two metal layers 03 included in the pull-down power line VSS can be located on the same layer as the first source-drain metal layer SD1 and the second source-drain metal layer SD2 included in the pixel 02, respectively. That is, of the two metal layers 03 included in the pull-down power line VSS, one metal layer 03 can be located on the same layer as the first source-drain metal layer SD1, and the other metal layer 03 can be located on the same layer as the second source-drain metal layer SD2. In this way, the pull-down voltage can be transmitted to the pixel 02 through the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0071] Furthermore, the two metal layers 03 included in the driving power line VDD can also be located on the same layer as the first source-drain metal layer SD1 and the second source-drain metal layer SD2 included in the pixel 02, respectively. That is, of the two metal layers 03 included in the driving power line VDD, one metal layer 03 can be located on the same layer as the first source-drain metal layer SD1, and the other metal layer 03 can be located on the same layer as the second source-drain metal layer SD2. In this way, the driving voltage can also be transmitted to the pixel 02 through the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0072] In addition, combined Figure 5 The positional relationship between the first source / drain metal layer SD1 and the second source / drain metal layer SD2 shown indicates that... Figure 4 Of the two metal layers 03 shown, the metal layer 03 located in the same layer as the first source / drain metal layer SD1 is closer to the substrate 01 than the metal layer 03 located in the same layer as the second source / drain metal layer SD2.

[0073] In this context, "located in the same layer" can refer to a layer structure formed by using the same film deposition process to create a film layer for forming a specific pattern, and then using the same photomask to pattern this film layer through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and formed through the same single patterning process. Therefore, by setting the two metal layers 03 included in the pull-down power line VSS and the two metal layers 03 included in the drive power line VDD to be located in the same layer as the first source / drain metal layer SD1 and the second source / drain metal layer SD2 included in pixel 02, the manufacturing process can be simplified, manufacturing costs can be saved, and manufacturing efficiency can be accelerated.

[0074] It should be noted that, due to Figure 4 The cross-sectional view shown is a cross-sectional view of the peripheral region A1 of substrate 01, therefore Figure 4 Only the two metal layers 03 included in the pull-down power line VSS are shown.

[0075] As another optional implementation, in this embodiment, the number of metal layers 03 included in the pull-down power line VSS can be greater than the number of metal layers 03 included in the drive power line VDD. That is, the number of metal layers 03 included in the pull-down power line VSS can be different from the number of metal layers 03 included in the drive power line VDD.

[0076] Example, Figure 6 It shows Figure 3 The diagram shows another cross-sectional view of the display panel in the MM' direction. (Combined with...) Figure 2 and Figure 6 As can be seen, the drive power line VDD described in the embodiments of this application may include two metal layers 03. The pull-down power line VSS may include three metal layers 03. Accordingly, refer to Figure 6It is understood that the display panel may include two first insulating layers 04, one of which may be located between the first and second metal layers 03 of the three metal layers 03, and the other first insulating layer 04 may be located between the second and third metal layers 03. The first metal layer 03 refers to the metal layer 03 close to the substrate 04, the third metal layer 03 refers to the metal layer 03 away from the substrate 01, and the second metal layer 03 refers to the metal layer 03 located between the first and second metal layers 03.

[0077] Based on this, refer to Figure 7 As shown in the pixel schematic diagram, the pixel 02 described in this application embodiment may include: an active layer P1, a first gate metal layer GATE1, a second gate metal layer GATE2, a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3, which are sequentially stacked along a direction away from the substrate 01.

[0078] Combined Figure 4 and Figure 6 It can be seen that the two metal layers 03 included in the driving power line VDD can be located on the same layer as the first source-drain metal layer SD1 and the second source-drain metal layer SD2, respectively. That is, of the two metal layers 03 included in the driving power line VDD, one metal layer 03 can be located on the same layer as the first source-drain metal layer SD1, and the other metal layer 03 can be located on the same layer as the second source-drain metal layer SD2. In this way, the driving voltage can also be transmitted to the pixel 02 through the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0079] Furthermore, the three metal layers 03 included in the pull-down power line VSS can be located on the same layer as the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3, respectively. That is, of the three metal layers 03 included in the pull-down power line VSS, one metal layer 03 can be located on the same layer as the first source-drain metal layer SD1, another metal layer 03 can be located on the same layer as the second source-drain metal layer SD2, and yet another metal layer 03 can be located on the same layer as the third source-drain metal layer SD3. In this way, the pull-down voltage can be transmitted to the pixel 02 through the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3.

[0080] In addition, combined Figure 7 The positional relationship between the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3 shown indicates that... Figure 6Of the three metal layers 03 shown, the metal layer 03 located in the same layer as the first source / drain metal layer SD1 is closer to the substrate 01 than the metal layer 03 located in the same layer as the second source / drain metal layer SD2, and the metal layer 03 located in the same layer as the second source / drain metal layer SD2 is closer to the substrate 01 than the metal layer 03 located in the same layer as the third source / drain metal layer SD3.

[0081] As can be seen from the above embodiments, by setting the metal layer 03 included in the pull-down power line VSS and the metal layer 03 included in the drive power line VDD to be located on the same layer as the source and drain metal layers included in the pixel 02, the manufacturing process can be simplified, manufacturing costs can be saved, and manufacturing efficiency can be accelerated.

[0082] Furthermore, it should be noted that, compared to the previous optional implementation, this implementation includes a third source / drain metal layer SD3 and another first insulating layer 04 located between the third source / drain metal layer SD3 and the second source / drain metal layer SD2. Therefore, two additional masks are required in the manufacturing process to fabricate the third source / drain metal layer SD3 and the other first insulating layer 04. Moreover, because the pull-down power line VSS in this implementation includes more metal layers 03, the impedance of the pull-down power line VSS is further effectively reduced, thereby further reducing the voltage drop across the pull-down power line VSS. This results in lower power consumption for the driver IC and correspondingly lower power consumption during display.

[0083] It should also be noted that, because Figure 7 The cross-sectional view shown is a cross-sectional view of the peripheral region A1 of substrate 01, therefore Figure 7 Only the three metal layers 03 included in the pull-down power line VSS are shown.

[0084] Figure 8 A schematic diagram of another type of display panel is shown. For example... Figure 8 As shown, the display panel 00 may further include: a data line D1 located on one side of the substrate 01, each pixel 02 being coupled to the data line D1 and used to emit light under the drive of a driving voltage, a pull-down voltage, and a data signal provided by the data line D1. Furthermore, reference... Figure 8 It can be seen that the display panel can include multiple data lines D1, and the number of these multiple data lines D1 can be equal to the number of columns of multiple pixels 02. Pixels 02 located in the same column can be coupled to the same driving power line VDD. Furthermore, combined with... Figure 8 It can be seen that the multiple data lines D1 can be located in the display area A1.

[0085] Based on this, for Figure 6In the embodiment of this application, the data line D1 can be located on the same layer as the third source-drain metal layer SD3, that is, the data signal provided by the data line D1 can be transmitted to the pixel 02 through the third source-drain metal layer SD3.

[0086] Since both the driving power line VDD and the data line D1 are located in the display area, by setting the driving power line VDD to be on the same layer as the first source-drain metal layer SD1 and the second source-drain metal layer SD2 included in pixel 02, and setting the data line D2 to be on the same layer as the third source-drain metal layer SD3 included in pixel 02, that is, by setting the driving voltage and data signal to be transmitted to pixel 02 through different source-drain metal layers, signal crosstalk between the driving voltage and data signal can be effectively prevented while reducing loss and power consumption.

[0087] for Figure 4 In the embodiment of this application, the data line D1 can be located on the same layer as the second source-drain metal layer SD2, that is, the data signal provided by the data line D1 can be transmitted to the pixel 02 through the second source-drain metal layer SD2.

[0088] Figure 9 This is a schematic diagram of a pixel structure provided in an embodiment of this application. For example... Figure 9 As shown, pixel 02 may include: pixel circuit 021 and light-emitting element 022.

[0089] The pixel circuit 021 can be coupled to the driving power line VDD and the first electrode of the light-emitting element 022, respectively. The second electrode of the light-emitting element 022 can be coupled to the pull-down power line VSS.

[0090] Based on this, it is necessary to clarify that the above... Figure 5 and Figure 7 The cross-sectional views shown are schematic diagrams of the pixel circuit 021 included in pixel 02. That is, the pixel circuit 021 in pixel 02 actually includes an active layer P1, a first gate metal layer GATE1, a second gate metal layer GATE2, a first source / drain metal layer SD1, and a second source / drain metal layer SD2, stacked sequentially along the direction away from the substrate 01. Alternatively, it includes an active layer P1, a first gate metal layer GATE1, a second gate metal layer GATE2, a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3, stacked sequentially along the direction away from the substrate 01.

[0091] In addition, combined Figure 4 and Figure 6It can be seen that the first electrode and the second electrode of the light-emitting element 022 can be arranged sequentially in a direction away from at least two metal layers 03. Optionally, the first electrode of the light-emitting element 022 is generally an anode, and the second electrode of the light-emitting element 022 is generally a cathode. The anode of the light-emitting element 022 is generally located in the display area A1, and the cathode of the light-emitting element 022 is generally located in the display area A1 and the peripheral area A2. Figure 4 and Figure 6 The figures shown are all cross-sectional views of the peripheral region A2, therefore only the cathode of the light-emitting element 022 is shown in each figure. Furthermore, Figure 4 and Figure 6 The light-emitting layer (EL) located between the anode and cathode of the light-emitting element 022 is also shown. Furthermore, the display panel 00 may also include: a transition electrode 05 and a second insulating layer 06.

[0092] The transition electrode 05 can be located on the same layer as the first electrode (not shown) of the light-emitting element 022, and the transition electrode 05 can be coupled to the second electrode of the light-emitting element 021. The second insulating layer 06 can be located between the transition electrode 05 and at least two metal layers 03. Further reference is made to this. Figure 4 and Figure 6 It can be seen that among the at least two metal layers 03 included in the pull-down power line VSS, the metal layer 03 near the adapter electrode 05 can be coupled to the adapter electrode 05 through the via k1 penetrating the second insulating layer 06.

[0093] That is, for Figure 4 In the structure shown, the pull-down voltage can be transmitted through a metal layer 03 located in the same layer as the first source-drain metal layer SD1, through a via k0 penetrating the first insulating layer 04 to another metal layer 03 located in the same layer as the second source-drain metal layer SD2; then through another metal layer 03 located in the same layer as the second source-drain metal layer SD2, through a via k1 penetrating the second insulating layer 06 to the transition electrode 05 located in the same layer as the anode of the light-emitting element 022; finally, it is transmitted to the cathode of the light-emitting element 022 through the transition electrode 05.

[0094] for Figure 6In the structure shown, the pull-down voltage can be transmitted through a metal layer 03 located in the same layer as the first source / drain metal layer SD1, through a via k0 penetrating the first insulating layer 04, to another metal layer 03 located in the same layer as the second source / drain metal layer SD2; then through another metal layer 03 located in the same layer as the second source / drain metal layer SD2, through a via k0 penetrating another first insulating layer 04, to yet another metal layer 03 located in the same layer as the third source / drain metal layer SD3; then through yet another metal layer 03 located in the same layer as the third source / drain metal layer SD3, to the transfer electrode 05 located in the same layer as the anode of the light-emitting element 022; finally, it is transmitted through the transfer electrode 05 to the cathode of the light-emitting element 022.

[0095] Optional, see reference Figure 5 and Figure 7 It is understood that, in addition to the aforementioned film layers, pixel circuit 021 may also include: a buffer layer BUFFER located between substrate 01 and active layer P1; a first gate insulating layer GI1 located between active layer P1 and first gate metal layer GATE1; a second gate insulating layer GI2 located between first gate metal layer GATE1 and second gate metal layer GATE2; an interlayer stabilizing layer ILD located between second gate metal layer GATE2 and first source / drain metal layer SD1; a first planarization layer PLN1 located between first source / drain metal layer SD1 and second source / drain metal layer SD2; and a second planarization layer PLN2 located between second source / drain metal layer SD2 and third source / drain metal layer SD3. Furthermore, referring to… Figure 7 It is understood that the pixel circuit 021 also includes a third planarization layer PLN3 located on the side of the third source / drain metal layer SD3 away from the substrate 01. The first planarization layer PLN1, the second planarization layer PLN2, and the third planarization layer PLN3 are the first insulating layer 04 described in the above embodiment. In addition, the display panel may also include a pixel stabilization layer PDL and a support layer PS stacked sequentially on the side of the anode of the light-emitting element 022 away from the substrate 01.

[0096] For example, with Figure 5Taking the structure shown below as an example, Table 1 below shows the optional materials for each layer included in pixel 02. Referring to Table 1, it can be seen that substrate 01 generally includes: a first flexible material layer PI1, a first barrier layer 1, a second flexible material layer PI2, and a second barrier layer PI2, stacked sequentially along the buffer layer BUFFER. The first flexible material layer PI1 and the second flexible material layer PI2 are both made of polyimide (Pi). The first barrier layer PI1 is made of silicon dioxide (SiO2). The second barrier layer PI2, the buffer layer BUFFER, and the interlayer stabilizing layer ILD each include two layers stacked sequentially, one layer being made of SiO2 and the other of silicon nitride (SiNx). The active layer P1 is made of silicon (Si). The first gate insulating layer GI1 is made of SiO2. The first gate metal layer GATE1 and the second gate metal layer GATE2 are both made of molybdenum (Mo). The second gate insulating layer GI2 is made of SiNx. The materials of the first source / drain metal layer SD1 and the second source / drain metal layer SD2 can both be titanium / aluminum / titanium (Ti / Al / Ti). The material of the anode of the light-emitting element 022 can be indium-tin oxide (ITO) / silver / indium-tin oxide (ITO / Ag / ITO). The materials of the first planarization layer PLN1, the second planarization layer PLN2, the pixel stabilization layer PDL, and the support layer PS can all be organic materials.

[0097] Table 1

[0098]

[0099]

[0100] by Figure 4 and Figure 5 Taking the structure shown as an example, as can be seen from Table 1, in this embodiment of the application, at least 11 mask processes are required to manufacture the display panel. These 11 mask processes are used to manufacture: the active layer PI, the first gate metal layer GATE1, the second gate metal layer GATE2, via k0, the first source / drain metal layer SD1, via k1, the first planarization layer PLN1, the second source / drain metal layer SD2, the second planarization layer PLN2, the anode of the light-emitting element 022, the pixel stabilization layer PDL, and the support layer PS.

[0101] It should be noted that the materials of the above-mentioned film layers are only illustrative and are not limited in this application.

[0102] Optional, see reference Figure 9 As can be seen, in this embodiment, the coupling of pixel 02 to data line D1 actually means that pixel circuit 021 is coupled to data line D1. Furthermore, pixel circuit 021 can also be coupled to gate line G1, reset line RE1, reset power supply line V1, and light emission control line EM, respectively. Under the control of the driving voltage, data signal, gate driving signal provided by gate line G1, reset signal provided by reset line RE1, reset power supply signal provided by reset power supply line V1, and light emission control signal provided by light emission control line EM, pixel circuit 021 can transmit driving current to light-emitting element 022 to drive light-emitting element 022 to emit light.

[0103] by Figure 9 Taking the structure shown as an example, Figure 10 A schematic diagram of the structure of another pixel 02 is shown. (See diagram below.) Figure 10 As shown, the pixel circuit 021 may include: a driving transistor T0, a data writing transistor T1, a compensation transistor T2, a first reset transistor T3, a second reset transistor T4, a first light-emitting control transistor T5 and a second light-emitting control transistor T6, totaling seven transistors, and a storage capacitor C1.

[0104] In this design, the gates of both the data writing transistor T1 and the compensation transistor T2 can be coupled to the gate line G1. The first terminal of the data writing transistor T1 can be coupled to the data line D1, and the second terminals of both the data writing transistor T1 and the compensation transistor T2 can be coupled to the gate of the driving transistor T0. The first terminal of the compensation transistor T2 can be coupled to the second terminal of the driving transistor T0. When the gate line G1 provides a gate drive signal with an effective potential, both the data writing transistor T1 and the compensation transistor T2 are turned on. At this time, the data signal provided by the data line D1 can be transmitted to the gate of the driving transistor T0 via the data writing transistor T1 to charge the gate of the driving transistor T0. Furthermore, the compensation transistor T2 can adjust the potential of the gate of the driving transistor T0 according to the potential of the second terminal of the driving transistor T0 to compensate for the drift of the threshold voltage of the driving transistor T0, so that the driving current ultimately transmitted to the light-emitting element 022 is independent of the threshold voltage of the driving transistor T0.

[0105] The gates of the first reset transistor T3 and the second reset transistor T4 can both be coupled to the reset line RE1. The first terminals of both the first reset transistor T3 and the second reset transistor T4 can both be coupled to the reset power supply line V1. The second terminal of the first reset transistor T3 can be coupled to the gate of the driving transistor T0, and the second terminal of the second reset transistor T2 can be coupled to the first terminal of the light-emitting element 022. When the reset line RE1 provides a valid reset signal, both the first reset transistor T3 and the second reset transistor T4 are turned on. At this time, the reset signal provided by the reset power supply line V1 can be transmitted through the first reset transistor T3 to the gate of the driving transistor T0 to reset the gate of the driving transistor T0. Furthermore, the reset signal provided by the reset power supply line V1 can be transmitted through the second reset transistor T4 to the first terminal of the light-emitting element 022 to reset the first terminal of the light-emitting element 022.

[0106] The gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can both be coupled to the light-emitting control line EM. The first terminal of the first light-emitting control transistor T5 can be coupled to the driving power line VDD, and the second terminal of the first light-emitting control transistor T5 can be coupled to the first terminal of the driving transistor T1. The first terminal of the second light-emitting control transistor T6 can be coupled to the second terminal of the driving transistor T1, and the second terminal of the second light-emitting control transistor T6 can be coupled to the first terminal of the light-emitting element 022. When the light-emitting control line EM provides a valid light-emitting control signal, both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. At this time, the driving voltage provided by the driving power line VDD can be transmitted to the first terminal of the driving transistor T1 via the first light-emitting control transistor T5. The driving transistor T1 generates a driving current based on this driving voltage and the potential at its gate. The driving current is transmitted to the light-emitting element 022 via the turned-on second light-emitting control transistor T6, thereby causing the light-emitting element 022 to emit light. That is, a path can be formed between the first light-emitting control transistor T5, the driving transistor T0, the second light-emitting control transistor T7, and the light-emitting element 022.

[0107] One end of the storage capacitor C1 can be coupled to the gate of the driving transistor T0, and the other end of the storage capacitor C1 can be coupled to the driving power line VDD. Through its bootstrap function, the storage capacitor C1 can adjust the gate potential of the driving transistor T0 based on the driving voltage provided by the driving power line VDD.

[0108] It should be noted that the pixel circuit 021 described in the embodiments of this application can be... Figure 10 The 7T1C structure shown (i.e., 7 transistors and 1 capacitor) can also be other structures, such as 6T1C.

[0109] It should also be noted that each transistor in the pixel circuit 021 can be an N-type transistor. Accordingly, as described in the above embodiment, the effective potential can be a high potential. Of course, each transistor in the pixel circuit can also be a P-type transistor. Accordingly, the effective potential can be a low potential.

[0110] Optional, with Figure 6 and Figure 10 Taking the structure shown as an example, Figure 11 A structural layout of pixel circuit 021 is shown. (Reference) Figure 11 It can be further seen that the drive power line VDD described in the embodiments of this application may include two metal layers 03 stacked sequentially, and these two metal layers 03 are located on the same layer as the first source-drain metal layer SD1 and the second source-drain metal layer SD2, respectively. The data line D1 is located on the same layer as the third source-drain metal layer SD3. In addition, Figure 11 It also indicates the reset power line V1, reset line RE1, gate line G1, and light control line EM.

[0111] Optional, still refer to Figures 4 to 7 It can also be seen that the display panel described in the embodiments of this application may further include: an interlayer stabilizing layer (ILD) located between a substrate 01 and at least two metal layers 03, an emissive light-emitting electrode (EOA) and a gate-driving electrode (GOA) located on the same layer as the interlayer stabilizing layer (ILD), a plurality of crack dams 07, a plurality of crack detection circuits 08, and a plurality of barrier dams 09.

[0112] For example, Figure 4 and Figure 6 Each circuit displays two crack dams (07), two crack detection circuits (08), and two barrier dams (09). Furthermore, Figure 4 and Figure 6 A cross-sectional view of the reset power supply line V1 is also shown. Based on this, Figure 3 The reset power lines V1 and GOA located in the peripheral area A2 are also shown.

[0113] Along the direction close to the display area A1, multiple crack dams 07, multiple crack detection circuits 08, multiple blocking dams 09, at least two metal layers 03, EOA, GOA, and a reset power line V1 are arranged sequentially. Each crack dam 07 can directly contact the substrate 01 and is used to prevent water and oxygen in the air from entering the display area A1 through cracks (also called fissures) generated at the edge of the display panel. Each crack detection circuit 08 can contact the interlayer fixing layer ILD and is used to detect whether cracks have been generated at the edge of the display panel. GOA can be coupled to the gate line G1 and is used to provide a gate drive signal to the gate line G1. EOA can be coupled to the light emission control line EM and is used to provide a light emission control signal to the light emission control line EM.

[0114] Optionally, in this embodiment, the target metal layer 03 may be located on the side of the other metal layers that is away from the substrate 01. That is, among the multiple metal layers 03, the orthogonal projection of the metal layer 03 furthest from the substrate 01 onto the substrate 01 covers the orthogonal projections of the other metal layers 03 onto the substrate 01.

[0115] Because in the peripheral area A2, the metal layer 03 on the side closer to the substrate 01 also includes GOA and EOA on the side closer to the display area A1, and the metal layer 03 on the side farther from the substrate 01 also needs to be coupled to the cathode of the light-emitting element 022 located in the display area A1 and the peripheral area A2 through the transition electrode 05, the target metal layer 03 can be located on the side of other metal layers farther from the substrate 01. This can effectively reduce the impedance of the pull-down power line VSS, avoid unnecessary crosstalk between the signals transmitted by GOA and EOA, and facilitate the effective coupling of the metal layer 03 and the cathode of the light-emitting element 022.

[0116] Optionally, the display panel 00 described in the embodiments of this application can be a flexible organic light-emitting diode (OLED) display panel.

[0117] In summary, this application provides a display panel. In this display panel, both the driving power line and the pull-down power line for pixel coupling include at least two sequentially stacked metal layers. Each pair of adjacent metal layers is coupled to each other, and the orthogonal projection of one metal layer onto the substrate covers the orthogonal projections of all other metal layers on the substrate. Since both the driving power line and the pull-down power line are implemented using multiple metal layers, the impedance of both the driving power line and the pull-down power line is relatively low. Consequently, the voltage drop across the driving power line and the pull-down power line is also relatively low, meaning that the voltage loss of the driving voltage and the voltage loss of the pull-down voltage are both low, thereby effectively reducing the power consumption and losses during the operation of the display panel.

[0118] Figure 12 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 12 As shown, the display device includes: a driver IC 10, and as shown in the figure. Figures 1 to 8 Any of the display panels shown, 00.

[0119] The driver IC 10 is coupled to the drive power line VDD and the pull-down power line VSS in the display panel 00, and the driver IC 10 is used to transmit the drive voltage to the drive power line VDD and the pull-down voltage to the pull-down power line VSS.

[0120] Optionally, taking display panel 00 as a flexible display panel as an example, Figure 13 A schematic diagram of another display device is shown. (Reference) Figure 13It can be seen that the display panel 00 in the display device may also include: a panel test assembly located on the substrate 01, multiple first electrostatic discharge (ESD) circuits ESD1, a first power line VGH and a second power line VGL.

[0121] The GOA can be coupled to the first power line VGH and the second power line VGL, and operates in response to a first power signal provided by the first power line VGH and a second power signal provided by the second power line VGL. The panel test assembly can be coupled to each signal line located on the substrate 01 and is used to test each signal line before shipment. Each ESD1 is coupled to each signal line located on the substrate 01 and is used to discharge static electricity generated on each signal line.

[0122] In addition, refer to Figure 13 It can also be seen that the display device may include a bonding portion located on one side of the substrate 01 (the lower side shown in the figure). This bonding portion may have a first fan-out region F1, a second fan-out region F2, and a bending region, with the first fan-out region F1, the bending region, and the second fan-out region F2 arranged sequentially along the direction close to the substrate 01. Furthermore, this bonding portion may also be provided with a flexible printed circuit (FPC), a driver IC 10, multiple second electrostatic discharge circuits ESD2, and a substrate testing assembly.

[0123] The signal lines located on substrate 01 can be led out from the FPC and introduced onto substrate 01 via the driver IC 10 from the first fan-out area F1 through the bending area and then through the second fan-out area F2. For example, the pull-down power line VSS can be led out from the FPC and introduced onto substrate 01 via the driver IC 10, and can extend along the left, right, and top borders on substrate 01. The portion located on the side of the bending area away from substrate 01 can be bent from the bending area to the back side of substrate 01. Each ESD2 is coupled to each signal line located on the bonding portion and is used to discharge static electricity generated on the signal line. The substrate test assembly is located between the bending area and the second fan-out area F2 and is used to test the signal lines located on the bonding portion before shipment.

[0124] Optionally, the display device described in the embodiments of this application can be any product or component with display function, such as an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a television, a monitor, a laptop computer, or a navigator.

[0125] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel (00), characterized in that, The display panel (00) includes: Substrate (01); In addition, a driving power line (VDD), a pull-down power line (VSS), and a plurality of pixels (02) are located on one side of the substrate (01); each pixel (02) is coupled to the pull-down power line (VSS) and the driving power line (VDD) respectively, and is used to emit light under the driving voltage provided by the driving power line (VDD) and the pull-down voltage provided by the pull-down power line (VSS); The drive power line (VDD) and the pull-down power line (VSS) each include: at least two metal layers (03) stacked sequentially in a direction away from the substrate (01), and a first insulating layer (04) located between each two adjacent metal layers (03). Each two adjacent metal layers (03) are coupled through a via (k0) penetrating the first insulating layer (04). Among the at least two metal layers (03), the orthographic projection of the target metal layer (03) on the substrate (01) covers the orthographic projection of other metal layers (03) on the substrate (01) except for the target metal layer (03). The pixel (02) includes: an active layer (P1), a first gate metal layer (GATE1), a second gate metal layer (GATE2), a first source / drain metal layer (SD1), and a second source / drain metal layer (SD2) stacked sequentially in a direction away from the substrate (01); the two metal layers (03) included in the driving power line (VDD) are located on the same layer as the first source / drain metal layer (SD1) and the second source / drain metal layer (SD2), respectively.

2. The display panel (00) according to claim 1, characterized in that, The target metal layer (03) is located on the side of the other metal layers (03) away from the substrate (01).

3. The display panel (00) according to claim 1, characterized in that, The number of metal layers (03) included in the drive power line (VDD) is the same as the number of metal layers (03) included in the pull-down power line (VSS).

4. The display panel (00) according to claim 3, characterized in that, Both the drive power line (VDD) and the pull-down power line (VSS) include two layers of the metal layer (03).

5. The display panel (00) according to claim 4, characterized in that, The pull-down power line (VSS) includes two metal layers (03) that are located on the same layer as the first source / drain metal layer (SD1) and the second source / drain metal layer (SD2), respectively.

6. The display panel (00) according to claim 1, characterized in that, The number of metal layers (03) included in the pull-down power line (VSS) is greater than the number of metal layers (03) included in the drive power line (VDD).

7. The display panel (00) according to claim 6, characterized in that, The drive power line (VDD) includes two metal layers (03); the pull-down power line (VSS) includes three metal layers (03).

8. The display panel (00) according to claim 7, characterized in that, The pixel (02) further includes a third source / drain metal layer (SD3) located on the side of the second source / drain metal layer (SD2) facing away from the substrate (01). The pull-down power line (VSS) includes three metal layers (03) that are located on the same layer as the first source-drain metal layer (SD1), the second source-drain metal layer (SD2), and the third source-drain metal layer (SD3).

9. The display panel (00) according to claim 8, characterized in that, The display panel (00) further includes: a data line (D1) located on one side of the substrate (01), and each pixel (02) is also coupled to the data line (D1) and used to emit light under the drive of the driving voltage, the pull-down voltage and the data signal provided by the data line (D1); The data line (D1) and the third source / drain metal layer (SD3) are located on the same layer.

10. The display panel (00) according to any one of claims 1 to 9, characterized in that, Each pixel (02) includes a pixel circuit (021) and a light-emitting element (022). The pixel circuit (021) is coupled to the driving power line (VDD) and the first electrode of the light-emitting element (022) respectively. The second electrode of the light-emitting element (022) is coupled to the pull-down power line (VSS). The first electrode and the second electrode of the light-emitting element (022) are arranged sequentially in a direction away from the at least two metal layers (03). The display panel (00) further includes: a transition electrode (05) and a second insulating layer (06), wherein the transition electrode (05) is located on the same layer as the first electrode of the light-emitting element (022), and the transition electrode (05) is coupled to the second electrode of the light-emitting element (021), and the second insulating layer (06) is located between the transition electrode (05) and the at least two metal layers (03); Among the at least two metal layers (03) included in the pull-down power line (VSS), the metal layer (03) near the adapter electrode (05) is coupled to the adapter electrode (05) through a via (k1) penetrating the second insulating layer (06).

11. The display panel (00) according to any one of claims 1 to 9, characterized in that, The display panel (00) is a flexible organic light-emitting diode (OLED) display panel.

12. The display panel (00) according to any one of claims 1 to 9, characterized in that, The substrate (01) has a display area (A1) and a peripheral area (A2) surrounding the display area (A1); The drive power line (VDD) is located in the display area (A1), and the pull-down power line (VSS) is located in the peripheral area (A2).

13. A display device, characterized in that, The display device includes: a driver integrated circuit (10), and a display panel (00) as described in any one of claims 1 to 12. The driving integrated circuit (10) is coupled to the driving power line (VDD) and pull-down power line (VSS) in the display panel (00). The driving integrated circuit (10) is used to transmit driving voltage to the driving power line (VDD) and pull-down voltage to the pull-down power line (VSS).

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