Spin orbit torque magnetoresistive random access memory and method of making the same

Abstract

The application discloses a spin-orbit torque magnetoresistive random access memory and a manufacturing method thereof. The spin-orbit torque magnetoresistive random access memory comprises an insulator, conductive bodies arranged oppositely at the bottom of the insulator, metal bodies symmetrically arranged in the insulator and electrically connected with the conductive bodies respectively, wherein the upper surfaces of the metal bodies are in a stepped shape, the first upper surface of the insulator between the metal bodies is flush with the highest horizontal surface of the metal bodies, and the highest horizontal surface is close to the interior of the insulator relative to the adjacent horizontal surface. A laminated structure is arranged on the first upper surface and the highest horizontal surface, and the laminated structure comprises an orbit layer and a magnetic tunnel junction stack. The diameter of the first upper surface is smaller than the diameter of the bottom of the magnetic tunnel junction stack. The upper surfaces of the metal bodies are in a stepped shape, the highest horizontal surface of the metal bodies is close to the interior of the insulator relative to the adjacent horizontal surface, the spacing of the insulator between the metal bodies is reduced, the length of the orbit layer is reduced, and the probability of the orbit layer being penetrated and power consumption are reduced.

Description

Technical Field

[0001] This application relates to the field of magnetic storage technology, and in particular to a spin-orbit torque magnetoresistive random access memory and its manufacturing method. Background Technology

[0002] Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM) utilizes the spin-orbit torque effect generated by spin current as the information writing method. It adopts a three-terminal magnetic tunnel junction structure to separate the read and write paths, resulting in faster write speeds and enhanced stability of read data.

[0003] In existing SOT-MRAMs, the oxide insulating layer between the metal bodies has a uniform width at both ends and a large width, resulting in a large track layer length, equal to the distance between the relative edges of the metal bodies, exceeding 200 nanometers. The top of the metal body is a flat surface, flush with the top surface of the surrounding silicon nitride insulating layer. During etching, the magnetic tunnel junction stack generates metal back sputtering. This backsputtered metal encapsulates the layer structure above the track layer, causing a short circuit. To reduce short circuits caused by metal back sputtering during etching, over-etching is typically used to remove the backsputtered portions. However, due to the small thickness of the track layer (less than 10 nanometers), it is easily etched through during over-etching, causing a break and rendering the memory unusable, thus reducing yield. Furthermore, due to the excessive length of the track layer, most of it is not effectively utilized, leading to high heat generation and power consumption during operation due to high resistance.

[0004] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a spin-orbit torque magnetoresistive random access memory and a method for manufacturing the same, so as to improve the yield of the spin-orbit torque magnetoresistive random access memory and reduce power consumption.

[0006] To address the aforementioned technical problems, this application provides a spin-orbit torque magnetoresistive random access memory, comprising:

[0007] Insulator;

[0008] Conductors located opposite to the bottom of the insulator;

[0009] The metal bodies are symmetrically arranged within the insulator and electrically connected to the conductors respectively. The upper surface of the metal bodies is stepped. The first upper surface of the insulator located between the metal bodies is flush with the highest horizontal surface of the metal bodies, and the highest horizontal surface is close to the interior of the insulator relative to the adjacent horizontal plane.

[0010] A stacked structure located on the first upper surface and the highest horizontal surface, the stacked structure including an orbital layer and a magnetic tunnel junction stack layer, wherein the diameter of the first upper surface is smaller than the bottom diameter of the stacked structure.

[0011] Optionally, the metal body is a one-piece metal body.

[0012] Optionally, the metal body includes a plurality of electrically connected metal blocks, with adjacent metal blocks made of different materials.

[0013] Optionally, the second upper surface of the insulator located outside the metal body is a downwardly inclined surface.

[0014] Optionally, the difference between the diameter of the first upper surface and the bottom diameter of the stacked structure is between 5 nanometers and 10 nanometers, including the endpoint values.

[0015] This application also provides a method for manufacturing a spin-orbit torque magnetoresistive random access memory, including:

[0016] A pretreated insulator with conductors disposed on its bottom is obtained;

[0017] The pre-treated insulator is etched to a local area corresponding to the conductor, and the etching stops at the upper surface of the conductor, forming symmetrically distributed stepped grooves in the pre-treated insulator; the width of the uppermost first groove in the stepped groove is greater than the width of the adjacent groove, and the portion of the first groove that is greater than the adjacent groove extends into the interior of the pre-treated insulator.

[0018] Metal is deposited in the stepped grooves to form a metal body to be etched;

[0019] The metal body to be etched in the first groove is etched to form a second groove, resulting in a metal body with a stepped upper surface; the depth of the second groove is less than the depth of the first groove, the length of the second groove is less than the length of the first groove, and the outer edge of the second groove is flush with the outer edge of the first groove.

[0020] An insulating material is deposited in the second groove to form a reprocessed insulator with the preprocessed insulator, the upper surface of the reprocessed insulator being flush with the highest horizontal surface of the metal body;

[0021] An etchable stacked structure is formed on the upper surface of the reprocessed insulator and the highest horizontal surface, and the etchable stacked structure is formed by etching the stacked structure, which includes an orbital layer and a magnetic tunnel junction stacked layer.

[0022] The reprocessed insulator located outside the highest horizontal surface is over-etched to form an insulator, resulting in a spin-orbit torque magnetoresistive random access memory. The first upper surface of the insulator located between the metal bodies is flush with the highest horizontal surface, and the spacing of the first upper surface is smaller than the bottom diameter of the stacked structure.

[0023] Optionally, when the metal body is a single-piece metal body, depositing metal in the stepped grooves to form the metal body to be etched includes:

[0024] Metal is deposited in the stepped grooves in a single process to form the metal body to be etched.

[0025] Optionally, when the metal body comprises multiple electrically connected metal blocks, and adjacent metal blocks are made of different materials, depositing metal in the stepped grooves to form the metal body to be etched includes:

[0026] Metal is deposited sequentially in the stepped grooves to form multiple electrically connected metal blocks, with different metal materials deposited in adjacent deposits.

[0027] Optionally, etching the stacked structure to be etched to form a stacked structure includes:

[0028] The etched structure is formed by etching the etched layered structure using ion beam etching technology.

[0029] Optionally, forming the etchable stacked structure on the upper surface of the reprocessed insulator and the highest horizontal surface includes:

[0030] A physical vapor deposition method is used to form a stacked structure to be etched on the upper surface and the highest horizontal surface of the reprocessed insulator.

[0031] This application provides a spin-orbit torque magnetoresistive random access memory (RAM), comprising an insulator; conductors disposed opposite each other at the bottom of the insulator; metal bodies symmetrically disposed within the insulator and electrically connected to the conductors respectively, the upper surface of the metal bodies being stepped, a first upper surface of the insulator located between the metal bodies being flush with the highest horizontal surface of the metal bodies, and the highest horizontal surface being close to the interior of the insulator relative to adjacent horizontal surfaces; and a stacked structure located on the first upper surface and the highest horizontal surface, the stacked structure comprising an orbital layer and a magnetic tunnel junction stack layer, wherein the diameter of the first upper surface is smaller than the bottom diameter of the magnetic tunnel junction stack layer.

[0032] As can be seen, in this application's SOT-MRAM, the upper surface of the metal body is stepped, and the first upper surface of the insulator located between the metal bodies is flush with the highest horizontal surface of the metal body. Furthermore, the highest horizontal surface is closer to the interior of the insulator than the adjacent horizontal surface. That is, compared to existing SOT-MRAM, the diameter (length) of the insulator located between the metal bodies is shorter, which also means the diameter (length) of the first upper surface is shorter. The track layer is located between the first upper surface and the highest horizontal surface of the metal body, so the diameter (length) of the track layer is shorter, thereby reducing the current-induced thermal effect during SOT-MRAM operation, reducing power consumption, and reducing the probability of the track layer being penetrated during over-etching, thus improving yield. Moreover, since the upper surface of the metal body is stepped, and the highest horizontal surface of the metal body is closer to the interior of the insulator than the adjacent horizontal surface, the thickness of the insulator in the over-etched area is increased, which can reduce or even avoid metal back sputtering caused by over-etching, thereby reducing the probability of short circuits and improving yield.

[0033] In addition, this application also provides a manufacturing method with the above advantages. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic diagram of the existing SOT-MRAM structure;

[0036] Figure 2 A schematic diagram of the structure of a spin-orbit torque magnetoresistive random access memory provided in an embodiment of this application;

[0037] Figure 3 A schematic diagram of another spin-orbit torque magnetoresistive random access memory provided in an embodiment of this application;

[0038] Figure 4 A flowchart illustrating a method for fabricating a spin-orbit torque magnetoresistive random access memory provided in an embodiment of this application;

[0039] Figures 5 to 12 A process flow diagram of a spin-orbit torque magnetoresistive random access memory provided in an embodiment of this application;

[0040] Figures 13 to 18 A process flow diagram of another spin-orbit torque magnetoresistive random access memory provided in an embodiment of this application. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0043] The existing structural diagram of SOT-MRAM is as follows: Figure 1 As shown, the oxide insulating layer 1” located between the metal bodies 4 has a consistent width W at the top and bottom, and is relatively wide. The track layer 5 spans across the metal body 4, and the track layer 5 is relatively long. Most of the track layer 5 is not effectively utilized, resulting in high heat generation and power consumption during use due to high resistance. It also increases the probability of the track layer 5 being penetrated during over-etching. In addition, during the etching process, the magnetic tunnel junction stack layer generates metal back sputtering, which can cause short circuits in the memory. The back sputtering part is usually removed by over-etching, but because the track layer 5 is relatively thin, it is easily etched through during over-etching, causing a circuit break, which leads to memory failure and reduced yield. Among them, the top of the SOT-MRAM is provided with an upper electrode 13 (or metal layer 13).

[0044] In view of this, this application provides a spin-orbit torque magnetoresistive random access memory, please refer to... Figure 2 and Figure 3 ,include:

[0045] Insulator;

[0046] Conductors 3 are located opposite to the bottom of the insulator;

[0047] Metal bodies 4 are symmetrically arranged within the insulator and electrically connected to the conductors 3 respectively. The upper surface of the metal bodies 4 is stepped. The first upper surface of the insulator located between the metal bodies 4 is flush with the highest horizontal surface of the metal bodies 4, and the highest horizontal surface is close to the interior of the insulator relative to the adjacent horizontal plane.

[0048] The stacked structure located on the first upper surface and the highest horizontal surface includes an orbital layer 5 and a magnetic tunnel junction stacked layer 6. The diameter D1 of the first upper surface is smaller than the bottom diameter D2 of the stacked structure.

[0049] Orbit layer 5 is used to provide the spin-orbit torque effect.

[0050] The insulator includes a first insulating layer 1 and a second insulating layer 2, and the conductor 3 is located in the region below the second insulating layer 2. The first insulating layer 1 can be an oxide insulating layer, and the second insulating layer 2 can be a silicon nitride insulating layer.

[0051] The material of the conductor 3 includes, but is not limited to, metallic materials such as copper, cobalt, and ruthenium. There are two conductors 3, and correspondingly, there are also two metallic bodies 4.

[0052] This application does not specifically limit the material of the metal body 4, and it can be selected by the applicant. For example, the material of the metal body 4 includes, but is not limited to, any one or any combination of tungsten, cobalt, ruthenium, copper, and tantalum.

[0053] It should be noted that the spin-orbit torque magnetoresistive random access memory also includes a third insulating layer 8 located on the second upper surface and surrounding the stacked structure; a fourth insulating layer 9 located around the third insulating layer 8, wherein the upper surfaces of the third insulating layer 8 and the fourth insulating layer 9 are flush with the upper surface of the stacked structure; and upper electrodes (or metal layers) 13 located on the third insulating layer 8, the fourth insulating layer 9, and the upper surface of the stacked structure to achieve electrical connection. The third insulating layer 8 can be a silicon nitride insulating layer, and the fourth insulating layer 9 can be an oxide insulating layer.

[0054] The stacked structure includes, from bottom to top, an orbital layer 5 and a magnetic tunnel junction stacked layer 6, as well as a metal hard mask layer 7 stacked on the upper surface of the magnetic tunnel junction stacked layer 6. The magnetic tunnel junction stacked layer 6 includes, from bottom to top, a magnetic free layer, an insulating tunneling layer, and a magnetic reference layer. The magnetization direction of the magnetic free layer can be changed by a spin polarization current, and the magnetic free layer is electrically connected to the orbital layer 5. The stacked structure is frustum-shaped.

[0055] The materials of the orbital layer 5 include, but are not limited to, tungsten, tantalum, platinum, bismuth selenide alloy, and bismuth tellurium alloy. The orbital layer 5 needs to be electrically connected to the metal body 4, so the orbital layer 5 is in contact with the highest horizontal surface of the metal body 4.

[0056] Optionally, during over-etching, the second upper surface of the insulator located outside the metal body 4 can be formed as a downwardly sloping surface. Of course, it can also be a horizontal surface.

[0057] The following section describes metal body 4 based on its different structures.

[0058] In one specific embodiment, the metal body 4 is a one-piece metal body, and the structural schematic diagram of the spin-orbit torque magnetoresistive random access memory is shown below. Figure 2 As shown.

[0059] Figure 2 The metal body 4 has two stepped surfaces, labeled 4a and 4b, each of which is a horizontal surface. The highest horizontal surface is step surface 4a. However, this application does not limit the number of steps (i.e., the number of stepped surfaces), and it can be three, four, or even more. It is important to emphasize that, regardless of the number of stepped surfaces, it is necessary to ensure that the highest horizontal surface of the metal body 4 is close to the interior of the insulator relative to the adjacent horizontal surface. The purpose is to shorten the distance between the highest horizontal surfaces of the metal body 4, that is, to reduce the diameter D1 of the first upper surface of the insulator located between the metal bodies 4, so that the diameter D1 of the first upper surface is smaller than the bottom diameter D2 of the magnetic stack structure, thereby reducing the length of the track layer 5, reducing power consumption, and reducing the probability of the track layer 5 being penetrated.

[0060] Optionally, the difference between the diameter D1 of the first upper surface and the bottom diameter D2 of the stacked structure is between 5 nanometers and 10 nanometers, including the endpoint values.

[0061] The second upper surface 1a of the insulator is a downward sloping surface, which is formed by over-etching. Since the metal body 4 is stepped, the distance between the horizontal surface of the metal body 4 other than the highest horizontal surface and the upper surface of the insulator before over-etching is increased. During over-etching, the metal body 4 can be avoided, and metal back sputtering can be eliminated.

[0062] In another specific embodiment, the metal body 4 includes multiple electrically connected metal blocks 41, with adjacent metal blocks 41 made of different materials; that is, the metal body 4 is a composite metal body, such as... Figure 3 As shown.

[0063] It should be noted that this application does not specify the number of metal blocks 41 in the metal body 4; for example, it can be two. Figure 3 As shown, there can also be three, four, or even more. Figure 3 The middle metal body 4 has two stepped surfaces, namely 4c and 4d. Each stepped surface is a horizontal surface, and the highest horizontal surface is the stepped surface 4c. The two stepped surfaces are formed by the uppermost metal block 41.

[0064] This application does not specify the number of stepped surfaces; there can be three, four, or even more. Furthermore, this application does not specify the number of metal blocks 41 forming the stepped surfaces; the metal blocks 41 located below the uppermost metal block 41 can also be combined with the uppermost metal block 41 to form more stepped surfaces.

[0065] It is important to emphasize that, regardless of the number of step surfaces or the number of metal blocks 41, it is necessary to ensure that the highest horizontal surface of the metal body 4 is close to the interior of the insulator relative to the adjacent horizontal surface. The purpose is to shorten the distance between the highest horizontal surfaces of the metal body 4, that is, to reduce the diameter D1 of the first upper surface of the insulator located between the metal bodies 4, thereby reducing the diameter D2 of the track layer 5, reducing power consumption, and reducing the probability of the track layer 5 being penetrated.

[0066] Optionally, the difference between the diameter D1 of the first upper surface and the bottom diameter D2 of the stacked structure is between 5 nanometers and 10 nanometers, including the endpoint values.

[0067] The second upper surface 1a of the insulator is a downward sloping surface, which is formed by over-etching. Since the metal body 4 is stepped, the distance between the horizontal surface of the metal body 4 other than the highest horizontal surface and the upper surface of the insulator before over-etching is increased. During over-etching, the metal body 4 can be avoided, and metal back sputtering can be eliminated.

[0068] In this SOT-MRAM, the upper surface of the metal body 4 is stepped. The first upper surface of the insulator located between the metal bodies 4 is flush with the highest horizontal surface of the metal body 4, and the highest horizontal surface is closer to the interior of the insulator than the adjacent horizontal surface. That is, compared with the existing SOT-MRAM, the diameter (length) of the insulator located between the metal bodies 4 is shorter, that is, the diameter (length) of the first upper surface is shorter. The track layer 5 is located between the first upper surface and the highest horizontal surface of the metal body 4, so the diameter (length) of the track layer 5 is shorter, thereby reducing the current thermal effect during SOT-MRAM operation, reducing power consumption, and reducing the probability of the track layer 5 being penetrated during over-etching, thus improving yield. Furthermore, since the upper surface of the metal body 4 is stepped, and the highest horizontal surface of the metal body 4 is closer to the interior of the insulator than the adjacent horizontal surface, that is, the thickness of the insulator in the over-etched area is increased, so during over-etching, metal back sputtering caused by over-etching can be reduced or even avoided, thereby reducing the probability of short circuits and improving yield.

[0069] This application also provides a method for manufacturing a spin-orbit torque magnetoresistive random access memory (RAM), please refer to [reference needed]. Figure 4 The method includes:

[0070] Step S101: Obtain a pre-treated insulator with a conductor disposed on its bottom.

[0071] Step S102: Etch the local area of ​​the pretreated insulator corresponding to the conductor, cutting off the etching to the upper surface of the conductor, forming symmetrically distributed stepped grooves in the pretreated insulator; the width of the uppermost first groove in the stepped groove is greater than the width of the adjacent groove, and the portion of the first groove that is greater than the adjacent groove extends into the interior of the pretreated insulator.

[0072] The depth of the first groove is specifically set based on the amount of loss from subsequent secondary etching and over-etching.

[0073] The stepped grooves can be prepared using the double damask process, the specific process of which is well known to those skilled in the art and will not be described in detail here.

[0074] Step S103: Deposit metal in the stepped groove to form a metal body to be etched.

[0075] It should be noted that this application does not limit the method of forming the metal body to be etched, and can be set by the user. For example, chemical vapor deposition, sputtering, etc. can be used.

[0076] It should also be noted that after the metal body to be etched is formed, the upper surface of the metal body to be etched needs to be smoothed by chemical mechanical planarization and made flush with the upper surface of the pretreated insulator.

[0077] In one specific embodiment, when the metal body is a one-piece metal body, depositing metal in the stepped grooves to form the metal body to be etched includes:

[0078] Metal is deposited in the stepped grooves in a single process to form the metal body to be etched.

[0079] In another specific embodiment, when the metal body comprises a plurality of electrically connected metal blocks, and the materials of adjacent metal blocks are different, depositing metal in the stepped grooves to form the metal body to be etched includes:

[0080] Metal is deposited sequentially in the stepped grooves to form multiple electrically connected metal blocks, with different metal materials deposited in adjacent deposits.

[0081] Step S104: Etch the metal body to be etched in the first groove to form a second groove, resulting in a metal body with a stepped upper surface; the depth of the second groove is less than the depth of the first groove, the length of the second groove is less than the length of the first groove, and the outer edge of the second groove is flush with the outer edge of the first groove.

[0082] The reason why the outer edge of the second groove is flush with the outer edge of the first groove is that, since the length of the second groove is less than the length of the first groove, aligning the outer edge of the second groove with the outer edge of the first groove causes the remaining metal body in the first groove to move closer to the interior of the insulator, reducing the diameter of the insulator within the range of the remaining metal body in the first groove, thereby shortening the length of the track layer.

[0083] Step S105: Deposit insulating material in the second groove to form a reprocessed insulator with the preprocessed insulator, wherein the upper surface of the reprocessed insulator is flush with the highest horizontal surface of the metal body.

[0084] Chemical vapor deposition can be used to deposit insulating materials.

[0085] After the insulating material is deposited in the second groove, the deposited insulating material in the second groove is smoothed out by chemical mechanical planarization.

[0086] Step S106: Form a stacked structure to be etched on the upper surface of the reprocessed insulator and the highest horizontal surface, and etch the stacked structure to be etched to form a stacked structure, the stacked structure including an orbital layer and a magnetic tunnel junction stack layer.

[0087] The etched stacked structure includes, from bottom to top, a track layer to be etched, a magnetic tunnel junction stacked layer to be etched, a metal hard mask layer to be etched, and an oxide hard mask layer to be etched. In addition to the track layer and magnetic tunnel junction stacked layer, the stacked structure also includes the metal hard mask layer. That is, during the etching process, the oxide hard mask layer to be etched is completely etched away. The specific etching process is well known to those skilled in the art and will not be described in detail here.

[0088] Optionally, forming the etchable stacked structure on the upper surface of the reprocessed insulator and the highest horizontal surface includes: forming the etchable stacked structure on the upper surface of the reprocessed insulator and the highest horizontal surface using physical vapor deposition. However, this application does not specifically limit this, and chemical vapor deposition can also be used to form the etchable stacked structure.

[0089] It should be noted that the etching method for the stacked structure to be etched is not specifically limited in this application, and can be selected at will. For example, etching the stacked structure to be etched to form a stacked structure includes: using ion beam etching technology to etch the stacked structure to be etched to form a stacked structure. Alternatively, reactive ion etching technology can be used to etch the stacked structure to be etched to form a stacked structure.

[0090] Step S107: Over-etch the reprocessed insulator located outside the highest horizontal surface to form an insulator and obtain a spin-orbit torque magnetoresistive random access memory. The first upper surface of the insulator located between the metal bodies is flush with the highest horizontal surface, and the spacing of the first upper surface is smaller than the bottom diameter of the stacked structure.

[0091] Optionally, during over-etching, the second upper surface of the insulator can be made into an inclined surface, or it can be a horizontal surface.

[0092] It should be noted that after excessive etching causes the reprocessed insulator to form an insulator, the process also includes:

[0093] A third insulating layer is deposited on the second upper surface, the third insulating layer surrounding the laminated structure;

[0094] A fourth insulating layer is deposited on the upper surface of the third insulating layer, and the upper surfaces of the third and fourth insulating layers are ground flush with the upper surface of the stacked structure by a chemical mechanical planarization process.

[0095] An upper electrode or metal layer is deposited on the surface of the third insulating layer, the fourth insulating layer, and the stacked structure to achieve electrical connectivity, thereby obtaining a spin-orbit torque magnetoresistive random access memory.

[0096] In the SOT-MRAM fabrication method of this application, the upper surface of the metal body is stepped, and the first upper surface of the insulator located between the metal bodies is flush with the highest horizontal surface of the metal body. Moreover, the highest horizontal surface is closer to the interior of the insulator than the adjacent horizontal surface. That is, compared with the existing SOT-MRAM, the diameter (length) of the insulator located between the metal bodies is shorter, that is, the diameter (length) of the first upper surface is shorter. The track layer is located between the first upper surface and the highest horizontal surface of the metal body, so the diameter (length) of the track layer is shorter, thereby reducing the current thermal effect during SOT-MRAM operation, reducing power consumption, and reducing the probability of the track layer being penetrated during over-etching, thus improving yield. Furthermore, since the upper surface of the metal body is stepped, and the highest horizontal surface of the metal body is closer to the interior of the insulator than the adjacent horizontal surface, that is, the thickness of the insulator in the over-etched area is increased, so during over-etching, metal back sputtering caused by over-etching can be reduced or even avoided, thereby reducing the probability of short circuits and improving yield.

[0097] The following section describes the fabrication methods of spin-orbit torque magnetoresistive random access memory based on different structures of the metal body.

[0098] Example 1: The metal body is a single piece of metal, with two stepped surfaces as an example.

[0099] Step 1: Obtain a pre-treated insulator with a conductor 3 disposed on its bottom.

[0100] Please refer to the following steps. Figure 5 The pre-treated insulator includes a pre-treated first insulating layer 1' and a pre-treated second insulating layer 2', and the conductor 3 is located in the region below the pre-treated second insulating layer 2'.

[0101] Step 2: Etch a local area of ​​the pretreated insulator corresponding to the conductor 3 to form two relatively distributed stepped grooves 10 in the pretreated insulator; the width W1 of the uppermost first groove is greater than the width W2 of the adjacent groove, and the portion of the first groove that is greater than the adjacent groove extends into the interior of the pretreated insulator.

[0102] Please refer to the following steps. Figure 6 The bottom of the stepped groove 10 is the upper surface of the conductor 3, so that the metal body formed by subsequent deposition can be electrically connected to the conductor 3.

[0103] Step 3: Deposit metal in the stepped groove 10 in one step to form the metal body 4' to be etched, and then grind the metal body 4' to be etched by chemical mechanical planarization.

[0104] Please refer to the following steps. Figure 7 The upper surface of the metal body 4' to be etched is flush with the upper surface of the pre-treated first insulating layer 1'.

[0105] Step 4: Etch the metal body 4' to be etched in the first groove to form a second groove 11, resulting in a metal body 4 with a stepped upper surface; the depth S1 of the second groove 11 is less than the depth S2 of the first groove, the length of the second groove is less than the length of the first groove, and the outer edge of the second groove is flush with the outer edge of the first groove.

[0106] Please refer to the following steps. Figure 8 .

[0107] Step 5: Deposit insulating material again in the second groove to form a reprocessed insulator, and grind it flat by chemical mechanical planarization until the highest horizontal surface 4a of the metal body 4 is exposed.

[0108] Please refer to the following steps. Figure 9 Then, the upper surface of the insulator is made flush with the highest horizontal surface 4a of the metal body 4 so that the subsequent track layer can be electrically connected to the metal body 4.

[0109] Step 6: Using physical vapor deposition or chemical vapor deposition, sequentially deposit the orbital layer 5' to be etched, the magnetic tunnel junction stack layer 6' to be etched, the metal hard mask layer 7' to be etched, and the oxide hard mask layer 12 to be etched on the upper surface of the reprocessed insulator and the highest horizontal surface of the metal body 4.

[0110] Please refer to the following steps. Figure 10 .

[0111] Step 7: Sequentially etch the oxide hard mask layer 12 to be etched, the metal hard mask layer 7' to be etched, the magnetic tunnel junction stacked layer 6' to be etched, and the orbital layer 5' to be etched to obtain the orbital layer 5, the magnetic tunnel junction stacked layer 6, and the metal hard mask layer 7, and perform over-etching to form a downwardly inclined second upper surface 1a to obtain an insulator.

[0112] Please refer to the following steps. Figure 11 Over-etching stops on the surface of the insulating material filled in the second groove. The metal body 4 will not be etched during the over-etching process, eliminating metal back sputtering. There is electrical connection between the orbital layer and the metal body 4. The insulator includes a first insulating layer 1 and a second insulating layer 2.

[0113] Step 8: Deposit a third insulating layer 8 on the second upper surface, and deposit a fourth insulating layer 9 on the upper surface of the third insulating layer 8, and use chemical mechanical planarization to grind it flat until the upper surface of the metal hard mask layer 7 is exposed.

[0114] Please refer to the following steps. Figure 12 .

[0115] Step 9: Deposit an upper electrode or metal layer on the surface of the third insulating layer 8, the fourth insulating layer 9, and the stacked structure to obtain a spin-orbit torque magnetoresistive random access memory.

[0116] Example 2: The metal body is a composite metal body, taking the metal body as including two metal blocks and two step surfaces of the metal body as an example.

[0117] Step 1: Obtain a pre-treated insulator with a conductor placed on its bottom.

[0118] Step 2: Etch a local area of ​​the pretreated insulator corresponding to the conductor to form two oppositely distributed stepped grooves in the pretreated insulator; the width of the uppermost first groove is greater than the width of the adjacent groove, and the portion of the first groove that is greater than the adjacent groove extends into the interior of the pretreated insulator.

[0119] Step 3: Deposit metal sequentially in the stepped grooves to form multiple electrically connected metal blocks 41, with different metal materials deposited in adjacent deposits.

[0120] Please refer to the following steps. Figure 13 The metal body to be etched includes two metal blocks 41. The uppermost metal block 41 is the metal block to be etched. The material of the uppermost metal block 41 can be tantalum nitride, titanium nitride, etc.

[0121] Step 4: Etch the metal body to be etched in the first groove to form a second groove 11, resulting in a metal body with a stepped upper surface; the depth S1 of the second groove 11 is less than the depth S2 of the first groove, the length of the second groove is less than the length of the first groove, and the outer edge of the second groove is flush with the outer edge of the first groove.

[0122] Please refer to the following steps. Figure 14 .

[0123] Step 5: Deposit insulating material again in the second groove to form a reprocessed insulator, and grind it flat to expose the highest horizontal surface 4c of the metal body by chemical mechanical planarization.

[0124] Please refer to the following steps. Figure 15 Then, the upper surface of the insulator is made flush with the highest horizontal surface 4c of the metal body so that the subsequent track layer and the metal body can be electrically connected.

[0125] Step 6: Using physical vapor deposition or chemical vapor deposition, sequentially deposit the orbital layer 5' to be etched, the magnetic tunnel junction stack layer 6' to be etched, the metal hard mask layer 7' to be etched, and the oxide hard mask layer 12 to be etched on the upper surface of the reprocessed insulator and the highest horizontal surface of the metal body.

[0126] Please refer to the following steps. Figure 16 .

[0127] Step 7: Sequentially etch the oxide hard mask layer 12 to be etched, the metal hard mask layer 7' to be etched, the magnetic tunnel junction stacked layer 6' to be etched, and the orbital layer 5' to be etched to obtain the orbital layer 5, the magnetic tunnel junction stacked layer 6, and the metal hard mask layer 7, and perform over-etching to form a downwardly inclined second upper surface 1a to obtain an insulator.

[0128] Please refer to the following steps. Figure 17 The metal body will not be etched during the over-etching process, eliminating metal back sputtering, and there is electrical connection between the orbital layer 5 and the metal body.

[0129] Step 8: Deposit a third insulating layer 8 on the second upper surface, and deposit a fourth insulating layer 9 on the upper surface of the third insulating layer 8, and use chemical mechanical planarization to grind it flat until the upper surface of the metal hard mask layer 7 is exposed.

[0130] Please refer to the following steps. Figure 18 .

[0131] Step 9: Deposit an upper electrode or metal layer on the surface of the third insulating layer, the fourth insulating layer, and the stacked structure to obtain a spin-orbit torque magnetoresistive random access memory.

[0132] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0133] The spin-orbit torque magnetoresistive random access memory and its manufacturing method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for manufacturing a spin-orbit torque magnetoresistive random access memory, characterized in that, include: A pretreated insulator with conductors disposed on its bottom is obtained; The pre-treated insulator is etched to a local area corresponding to the conductor, and the etching stops at the upper surface of the conductor, forming symmetrically distributed stepped grooves in the pre-treated insulator; the width of the uppermost first groove in the stepped groove is greater than the width of the adjacent groove, and the portion of the first groove that is greater than the adjacent groove extends into the interior of the pre-treated insulator. Metal is deposited in the stepped grooves to form a metal body to be etched; The metal body to be etched in the first groove is etched to form a second groove, resulting in a metal body with a stepped upper surface; the depth of the second groove is less than the depth of the first groove, the length of the second groove is less than the length of the first groove, and the outer edge of the second groove is flush with the outer edge of the first groove. An insulating material is deposited in the second groove to form a reprocessed insulator with the preprocessed insulator, the upper surface of the reprocessed insulator being flush with the highest horizontal surface of the metal body; An etchable stacked structure is formed on the upper surface and the highest horizontal surface of the reprocessed insulator, and the etchable stacked structure is etched to form a stacked structure, the stacked structure including an orbital layer and a magnetic tunnel junction stack layer; the stacked structure is frustum-shaped; The reprocessed insulator located outside the highest horizontal surface is over-etched to form an insulator, resulting in a spin-orbit torque magnetoresistive random access memory. The first upper surface of the insulator located between the metal bodies is flush with the highest horizontal surface, and the spacing between the first upper surfaces is smaller than the bottom diameter of the stacked structure. The difference between the diameter of the first upper surface and the bottom diameter of the stacked structure is between 5 nanometers and 10 nanometers, including the endpoint values. The second upper surface of the insulator located outside the metal bodies is a downwardly sloping surface. When the metal body is a single metal body, depositing metal in the stepped grooves to form the metal body to be etched includes: Metal is deposited in the stepped grooves in a single process to form the metal body to be etched; When the metal body comprises multiple electrically connected metal blocks, and adjacent metal blocks are made of different materials, depositing metal in the stepped grooves to form the metal body to be etched includes: Metal is deposited sequentially in the stepped grooves to form multiple electrically connected metal blocks, with different metal materials deposited in adjacent deposits.

2. The method for manufacturing a spin-orbit torque magnetoresistive random access memory as described in claim 1, characterized in that, The etching of the laminated structure to be etched to form the laminated structure includes: The etched structure is formed by etching the etched layered structure using ion beam etching technology.

3. The method for manufacturing a spin-orbit torque magnetoresistive random access memory as described in any one of claims 1 to 2, characterized in that, The process of forming the etchable stacked structure on the upper surface and the highest horizontal surface of the reprocessed insulator includes: A physical vapor deposition method is used to form a stacked structure to be etched on the upper surface and the highest horizontal surface of the reprocessed insulator.

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