Neuronal device and method of manufacturing thereof

Abstract

The application relates to a neuron device which realizes neuromorphic computing based on a two-dimensional material channel layer, and by inserting a work function layer in a contact area of the channel layer at both source / drain ends, forms an asymmetric Schottky contact at the contact interface, and combines a defect capture and release mechanism introduced by a gate dielectric layer, realizes a resistance change characteristic and further realizes an LIF neuron device based on a single device, namely a single-device neuron.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and specifically to a neuron device and its fabrication method. Background Technology

[0002] In recent years, memristor devices have attracted widespread attention due to their significant advantages in neuromorphic computing. Novel memristor devices, such as ferroelectric memristors, phase-change memristors, and magnetoresistive tunneling memristors, have been reported to have advantages over CMOS devices, such as simple structure, low power consumption, and rich dynamic characteristics, and are thus applied to neuromorphic computing.

[0003] Two-dimensional (2D) material-based devices have been used for neuromorphic computing due to their advantages such as good miniaturization and rich dynamic characteristics. However, due to the inherent limitations of 2D materials, such as contact defects, research on 2D material-based neuromorphic devices, especially neuronal devices, has not yet been fully developed.

[0004] Therefore, developing a neuronal device based on two-dimensional materials has become a new research topic. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a neuronal device. This neuronal device realizes neuromorphic computing based on a two-dimensional material channel layer. By inserting a work function layer at the contact area between the source and drain ends and the channel layer, an asymmetric Schottky contact is formed at the contact interface. Combined with the defect charge trapping and release mechanism introduced by the gate dielectric layer, resistive switching characteristics are realized, and a single-device LIF (leaky-integral-fire) neuronal device, i.e., a single-device neuron, is further realized.

[0006] Another object of the present invention is to provide a method for fabricating the above-mentioned neuronal device.

[0007] To achieve the above objectives, the present invention provides the following technical solution.

[0008] A neuron device, comprising:

[0009] Substrate;

[0010] A gate dielectric layer, wherein the gate dielectric layer is disposed on the upper surface of the substrate;

[0011] A channel layer that covers a portion of the upper surface of the gate dielectric layer, and the channel layer is made of a two-dimensional material;

[0012] The source and the drain are both disposed above the channel layer and do not contact each other;

[0013] A first work function layer is disposed between the channel layer and the source; and

[0014] The second work function layer is disposed between the channel layer and the drain, and the second work function layer and the first work function layer are not in contact with each other.

[0015] A method for fabricating a neuron device includes the following steps:

[0016] Provide substrate;

[0017] A gate dielectric layer is formed on the substrate;

[0018] A channel layer is formed on the gate dielectric layer, covering a portion of the upper surface of the gate dielectric layer, and the channel layer is made of a two-dimensional material;

[0019] An initial work function layer is formed to cover the surface of the channel layer;

[0020] Photolithography is used to form the initial work function layer, creating an opening that exposes a portion of the upper surface of the channel layer, resulting in a first work function layer and a second work function layer; and

[0021] A source is formed on the surface of the first work function layer, and a drain is formed on the surface of the second work function layer.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] 1. This invention provides a neuronal device that realizes neuromorphic computing based on a two-dimensional material channel layer. By inserting a work function layer at the contact region between the source / drain ends and the channel layer, an asymmetric Schottky contact is formed at the contact interface. Combined with the defect charge trapping and release mechanism introduced by the gate dielectric layer, resistive switching characteristics are achieved, and a single-device LIF (leaky-integral-fire) neuronal device is further realized. Furthermore, the neuronal device of this invention has advantages such as good miniaturization and rich dynamic characteristics due to the use of two-dimensional materials.

[0024] This invention provides a new approach to realizing neuron devices by introducing a work function layer and growing a gate dielectric layer, offering insights for further realizing low-power neural network computing.

[0025] 2. The neuronal device based on two-dimensional materials of the present invention is compatible with silicon-based processes and is easy to integrate. Attached Figure Description

[0026] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0027] Figure 1 This is a schematic diagram of the neuron device of the present invention.

[0028] Figure 2-3 This is a schematic diagram of the neuron device of the present invention.

[0029] Figure 4-8 This is a schematic diagram of the structures obtained in each step of the fabrication method of the neuron device of the present invention.

[0030] Explanation of reference numerals in the attached figures:

[0031] 100 is the substrate, 200 is the gate dielectric layer, 300 is the channel layer, 400 is the initial work function layer, 400a is the first work function layer, 400b is the second work function layer, 500 is the source, 501 is the first metal layer, 502 is the second metal layer, 600 is the drain, 601 is the third metal layer, and 602 is the fourth metal layer. Detailed Implementation

[0032] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0033] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0034] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0035] Devices based on two-dimensional materials possess advantages such as good miniaturization and rich dynamic characteristics, making them suitable for neuromorphic computing. However, due to inherent limitations of two-dimensional materials, such as contact defects, research on neuromorphic devices, especially neuronal devices, based on two-dimensional materials has not yet been fully developed.

[0036] Through in-depth research, the inventors designed a neuronal device that realizes neuromorphic computation based on a two-dimensional material channel layer. By inserting a work function layer at the contact area between the source / drain ends and the channel layer, an asymmetric Schottky contact is formed at the contact interface. Combined with the defect charge trapping and release mechanism introduced by the gate dielectric layer, resistive switching characteristics are realized, and a LIF neuronal device based on a single device is further realized.

[0037] Specifically, the neuron device of the present invention includes: a substrate 100; a gate dielectric layer 200 disposed on the upper surface of the substrate 100; a channel layer 300 covering a portion of the upper surface of the gate dielectric layer 200, and the channel layer 300 being made of a two-dimensional material; a source electrode 500 and a drain electrode 600, both disposed above the channel layer 300 and not in contact with each other; a first work function layer 400a disposed between the channel layer 300 and the source electrode 500; and a second work function layer 400b disposed between the channel layer 300 and the drain electrode 600, and the second work function layer 400b and the first work function layer 400a not in contact with each other.

[0038] The present invention does not impose any particular restrictions on the material of the substrate 100. Any substrate 100 conventionally used in the art can be used in the present invention. For example, the substrate 100 can be a silicon-based substrate 100.

[0039] In some embodiments of the present invention, the gate dielectric layer 200 may be made of HfO2, Al2O3, SiO2, ZrO2 or La2O3.

[0040] The gate dielectric layer 200 is a defect charge accumulation layer. When the applied voltage is large enough, the defect charge accumulation can overcome the potential barrier and form a low-resistance state.

[0041] The channel layer 300 is made of a two-dimensional material. Preferably, the two-dimensional material may be selected from, for example, MoS2, WSe2, WS2, MoSe2, MoTe2, or WTe2.

[0042] The neuron device of the present invention is based on two-dimensional materials and has advantages such as good miniaturization and rich dynamic characteristics.

[0043] In some embodiments of the present invention, the material of the first work function layer 400a and the second work function layer 400b can both be TiO2.

[0044] The presence of the first work function layer 400a and the second work function layer 400b forms a Schottky barrier for electrons and holes, thereby providing a high-resistivity state for the device.

[0045] The innovation of this invention lies in inserting a first work function layer 400a and a second work function layer 400b into the contact region between the source and drain ends and the channel layer 300, forming an asymmetric Schottky contact at the contact interface. The gate dielectric layer 200, acting as a defect charge trapping-release layer, has the function of trapping and spontaneously releasing defect charges, enabling leakage and integration functions in LIF neurons. The asymmetric Schottky barrier, combined with the defect charge trapping-release process, forms the resistive switching of the device, enabling the excitation function in LIF neurons. The principle of the neuron device of this invention is as follows: Figure 2-3 As shown.

[0046] In some embodiments of the present invention, the source 500 is disposed above the gate dielectric layer 200 and the channel layer 300, and a first work function layer 400a is disposed between the channel layer 300 and the source 500, and between the gate dielectric layer 200 and the source 500. The drain 600 is disposed above the gate dielectric layer 200 and the channel layer 300, and a second work function layer 400b is disposed between the channel layer 300 and the drain 600, and between the gate dielectric layer 200 and the drain 600.

[0047] In some embodiments of the present invention, the source end 500 includes a first metal layer 501 and a second metal layer 502 from bottom to top. The first metal layer 501 may be made of Ti. The second metal layer 502 may be made of Au, Pt, Ni, Pd, or Cr.

[0048] In some embodiments of the present invention, the drain 600 includes a third metal layer 601 and a fourth metal layer 602 from bottom to top. The material of the third metal layer may be Ti. The material of the fourth metal layer may be Au, Pt, Ni, Pd, or Cr.

[0049] The present invention also provides a method for fabricating the aforementioned neuronal device, specifically including the following steps.

[0050] First, a substrate 100 is provided, such as Figure 4 As shown.

[0051] Then, a gate dielectric layer 200 is formed on the substrate 100, such as Figure 5 As shown.

[0052] Preferably, the gate dielectric layer 200 can be grown on the substrate 100 by atomic layer deposition (ALD).

[0053] Subsequently, a channel layer 300 is formed on the gate dielectric layer 200, covering a portion of the upper surface of the gate dielectric layer 200, and the channel layer 300 is made of a two-dimensional material. For example... Figure 6 As shown.

[0054] In some embodiments, forming the channel layer 300 includes:

[0055] A two-dimensional material was grown on the gate dielectric layer 200 using chemical vapor deposition.

[0056] By removing part of the two-dimensional material, a channel layer 300 is obtained.

[0057] In some specific embodiments, partial removal of the two-dimensional material can be achieved through photolithography and etching. Alternatively, partial removal of the two-dimensional material can be achieved through mechanical peeling and transfer.

[0058] Next, an initial work function layer 400 is formed, covering the surface of the channel layer 300, such as... Figure 7 As shown.

[0059] In some embodiments, the initial work function layer 400 can be formed by electron beam evaporation in a vacuum environment. The vacuum level of the vacuum environment can be 1 x 10⁻⁶. -9 For mbar and above, preferably 1 x 10 -4 mbar ~ 1x 10 -7 mbar, for example, can be 1 x 10 - 6 mbar.

[0060] Then, the initial work function layer 400 is photolithographically formed to create openings, exposing part of the upper surface of the channel layer 300, resulting in the first work function layer 400a and the second work function layer 400b, as shown. Figure 8 As shown.

[0061] Next, a source 500 is formed on the surface of the first work function layer 400a. A drain 600 is formed on the surface of the second work function layer 400b. The resulting structure is as follows. Figure 1 As shown.

[0062] In some embodiments, the source 500 and the drain 600 are formed simultaneously, and the formation method includes:

[0063] A photoresist layer is formed by spin coating, which covers the upper surfaces of the first work function layer 400a, the second work function layer 400b, and the channel layer 300.

[0064] Part of the photoresist layer is removed by photolithography, exposing the surfaces of the first work function layer 400a and the second work function layer 400b.

[0065] A metal layer is formed on the exposed surface using physical vapor deposition.

[0066] Remove the remaining photoresist layer to obtain source 500 and drain 600.

[0067] The metal layer may include a two-layer structure stacked vertically, such as a Ti metal layer and an Au metal layer stacked vertically. In one specific embodiment, a Ti metal layer may be deposited first to obtain a Ti metal layer, and then Au metal may be deposited on the Ti metal layer to obtain an Au metal layer.

[0068] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A neuron device, characterized in that, include: Substrate; A gate dielectric layer, wherein the gate dielectric layer is disposed on the upper surface of the substrate; A channel layer that covers a portion of the upper surface of the gate dielectric layer, and the channel layer is made of a two-dimensional material; The source and the drain are both disposed above the channel layer and do not contact each other; A first work function layer is disposed between the channel layer and the source. as well as The second work function layer is disposed between the channel layer and the drain, and the second work function layer and the first work function layer are not in contact with each other; The first work function layer and the second work function layer are both made of TiO2.

2. The neuron device according to claim 1, characterized in that, The source electrode is disposed above the gate dielectric layer and the channel layer, and the first work function layer is disposed between the channel layer and the source electrode, and between the gate dielectric layer and the source electrode.

3. The neuron device according to claim 1, characterized in that, The drain is disposed above the gate dielectric layer and the channel layer, and the second work function layer is disposed between the channel layer and the drain, and between the gate dielectric layer and the drain.

4. The neuron device according to claim 1, characterized in that, The source electrode comprises a first metal layer and a second metal layer from bottom to top. The first metal layer is made of Ti, and the second metal layer is made of Au, Pt, Ni, Pd, or Cr. The two metal layers are made of different materials. The drain electrode comprises a third metal layer and a fourth metal layer from bottom to top. The third metal layer is made of Ti, and the fourth metal layer is made of Au, Pt, Ni, Pd, or Cr, and the two metal layers are made of different materials.

5. The neuron device according to claim 1, characterized in that, The two-dimensional material is selected from MoS2, WSe2, WS2, MoSe2, MoTe2, and WTe2; The material of the gate dielectric layer is selected from HfO2, Al2O3, SiO2, ZrO2, and La2O3.

6. A method for fabricating a neuronal device, characterized in that, Includes the following steps: Provide substrate; A gate dielectric layer is formed on the substrate; A channel layer is formed on the gate dielectric layer, covering a portion of the upper surface of the gate dielectric layer, and the channel layer is made of a two-dimensional material; An initial work function layer is formed to cover the surface of the channel layer; The initial work function layer is photolithographically etched to form an opening, exposing part of the upper surface of the channel layer, thus obtaining the first work function layer and the second work function layer; as well as A source is formed on the surface of the first work function layer, and a drain is formed on the surface of the second work function layer.

7. The preparation method according to claim 6, characterized in that, The initial work function layer is formed by electron beam evaporation in a vacuum environment with a vacuum level of 1 x 10⁻⁶. -9 mbar or above.

8. The preparation method according to claim 6, characterized in that, The formation of the channel layer includes: A two-dimensional material layer was grown on the gate dielectric layer using chemical vapor deposition. The two-dimensional material is removed to obtain the channel layer.

9. The preparation method according to claim 6, characterized in that, The source and the drain are formed simultaneously, and the formation method includes: A photoresist layer is formed to cover the upper surfaces of the first work function layer, the second work function layer, and the channel layer; Remove part of the photoresist layer to expose the surfaces of the first work function layer and the second work function layer; A metal layer is formed on the exposed surface using physical vapor deposition. Remove the remaining photoresist layer to obtain the source and the drain.

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