A phase change memory cell and a method of fabricating the same

Abstract

The application relates to a phase change memory unit and a preparation method thereof, and belongs to the technical field of phase change memories. The phase change memory unit comprises a substrate, a bottom electrode layer arranged in the substrate, an upper contact surface of the bottom electrode layer being exposed outside the substrate and being flush with an upper surface of the substrate, a columnar phase change layer arranged in the middle of the upper contact surface of the bottom electrode layer, an insulating protective layer arranged at the periphery of the columnar phase change layer, and a top electrode layer arranged above the columnar phase change layer and the insulating protective layer. The preparation method can etch a small-size unit below 5 mu m, can improve the cycle number of the device, can reduce the power consumption in the phase change process of the device, can reduce the resistance drift, and can improve the stability, the data retention capability and other performances of the device.

Description

Technical Field

[0001] This invention belongs to the field of phase change memory technology, and particularly relates to a phase change memory cell and its preparation method. Background Technology

[0002] With the development of technology, people are paying increasing attention to information storage. Information needs long-term continuous storage and random access, which poses an insurmountable challenge to existing data centers. Currently, computing devices use the von Neumann architecture with independent computing and storage units, which exposes the drawback of the "memory bottleneck." Non-volatile memristors can simultaneously realize data storage and in-memory computing and hold the promise of overcoming this bottleneck. Phase-change random access memory (PCRAM) is considered one of the best solutions for next-generation non-volatile memory. Due to its high speed, good data retention, high density, and low power consumption, PCRAM has broad commercial prospects in in-memory computing applications.

[0003] Phase-change memory (PCRAM) works by using Joule heating generated by electrical pulses to induce a crystalline-to-amorphous transition in a phase-change material. The significant difference in resistivity before and after the phase transition allows switching between a lower-resistivity crystalline state and a higher-resistivity amorphous state, thus enabling storage. The reversible structural change in the thin film leads to significant changes in the material's reflectivity and resistivity, which can be measured during readout operations. The initial amorphous phase-change layer is crystallized by exposing it to a laser beam or electrical pulse of sufficient intensity to heat the material above its glass transition temperature; this is called the SET process. By using a short laser or electrical pulse of sufficient intensity to melt the phase-change layer, the crystalline phase can then be transformed into an amorphous phase after quenching. PCRAM offers advantages such as non-volatility, long cycle life, low power consumption, multi-level storage, high-speed readout, radiation resistance, and simple manufacturing process (compatible with CMOS processes). Compared to other novel memory technologies, PCRAM is considered a high-density memory technology with the potential to become the mainstream memory. Currently, there are two main research hotspots in phase-change memory (PCM) internationally. One is to conduct research on high-density 3D integration to achieve 3D stacking for application in high-data-density fields such as data centers. The other is to conduct research on multi-value storage to realize neuromorphic chips for application in the AI ​​field. Both of these have very high requirements for the manufacturing process. 3D stacking needs to withstand more rigorous thermal processing and has higher requirements for thermal stability. Neuromorphic chips need to achieve stable multi-resistivity states and require a lower resistance drift coefficient. Under the conditions of ordinary laboratories, it is difficult to carry out the research on these processes due to high costs and great difficulty. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the problems of complex manufacturing process, high cost and poor stability of phase change memory in the prior art.

[0005] To address the aforementioned technical problems, this invention provides a phase-change memory cell and its fabrication method.

[0006] The first objective of this invention is to provide a phase-change memory cell, the phase-change memory cell comprising:

[0007] Substrate;

[0008] A bottom electrode layer is disposed in the substrate, wherein the upper contact surface of the bottom electrode layer is exposed outside the substrate and is flush with the upper surface of the substrate;

[0009] A columnar phase change layer is disposed in the middle of the contact surface on the bottom electrode layer;

[0010] An insulating protective layer is disposed around the cylindrical phase change layer;

[0011] A top electrode layer is disposed above the cylindrical phase change layer and the insulating protective layer.

[0012] In one embodiment of the present invention, the substrate is made of silicon.

[0013] In one embodiment of the present invention, the thickness of the cylindrical phase change layer is 150nm-250nm, and the radius is 100nm-100μm. The central cylindrical structure of the cylindrical phase change layer is the region that actually participates in the phase change.

[0014] In one embodiment of the present invention, the material of the columnar phase change layer is Ge2Sb2Se4Te1. The material of the columnar phase change layer is a phase change material with three-dimensional confinement capability and small grain size.

[0015] In one embodiment of the invention, the total thickness of the insulating protective layer is 50 nm-100 nm thicker than the thickness of the cylindrical phase change layer. The insulating protective layer can prevent the top electrode from contacting the bottom electrode and prevent other areas besides the cylindrical phase change layer from being affected by the electrodes.

[0016] In one embodiment of the present invention, the insulating protective layer is made of SiO2. On the one hand, it can prevent phase transitions in other phase change films except for the central phase change region; on the other hand, the insulating layer covering the surface of the phase change layer can improve the thermal insulation and heat insulation effect of the material by utilizing its low thermal conductivity, thereby reducing heat conduction between the phase change material and the electrode, reducing heat radiation from the phase change material to the outside, and thus reducing operating power consumption.

[0017] In one embodiment of the present invention, the materials of the bottom electrode layer and the top electrode layer are both Ti, Au, Pt or W.

[0018] A second objective of this invention is to provide a method for preparing the aforementioned phase-change memory cell, comprising the following steps:

[0019] (1) A bottom electrode layer is embedded in a substrate, wherein the upper contact surface of the bottom electrode layer is exposed outside the substrate and is flush with the upper surface of the substrate;

[0020] (2) A columnar phase change layer is set in the middle of the contact surface on the bottom electrode layer using pulsed laser deposition and ion beam etching techniques;

[0021] (3) An insulating protective layer is deposited around the cylindrical phase change layer using ion beam deposition.

[0022] (4) A top electrode layer is deposited on the surface of the cylindrical phase change layer and the insulating protective layer by ion beam deposition to obtain the phase change storage unit.

[0023] In one embodiment of the present invention, in step (2), the gas pressure of the pulsed laser deposition method is less than 1 × 10⁻⁶. - 3 The pressure is 200-250 mJ. Under these conditions, the film is not oxidized during target sputtering, and the resulting phase change material is free of impurities. This laser energy and conditions ensure that all elements of the target material are sputtered, and the sputtered particles are sufficiently small, resulting in a smoother film.

[0024] In one embodiment of the present invention, in step (2), the cutting current of the ion beam etching technology is 700pA-30nA, and the cutting time is 1min-5min. Under these conditions, the cut surface can be smoother (too small a current will result in a rough cut, while too large a current will damage the sample), ensuring that the sample conforms to the cutting shape.

[0025] In one embodiment of the present invention, in step (4), the method for preparing the top electrode layer specifically includes the following steps: depositing an electrode wire leading out from the cylindrical phase change layer, and then depositing a square electrode plate at the end as the contact point of the test probe.

[0026] In one embodiment of the present invention, the side length of the square electrode plate is 20-30 μm.

[0027] The technical solution of the present invention has the following advantages compared with the prior art:

[0028] (1) The preparation method described in this invention can etch small-sized units of less than 5μm, which can increase the number of device cycles, reduce power consumption during the phase transition process of the device, reduce resistance drift, and improve the device stability, data retention and other performance.

[0029] (2) The preparation method described in this invention encapsulates the central phase change layer material with an insulating protective layer material, which can suppress the volatilization of the phase change material and maintain the stability of the phase change material components, thereby maintaining the reliability and stability of the device performance. Attached Figure Description

[0030] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein:

[0031] Figure 1 This is a flowchart illustrating the fabrication process of a phase-change memory cell with a radius of 1 μm according to Embodiment 1 of the present invention.

[0032] Figure 2 This is a cross-sectional schematic diagram of a phase-change memory cell with a radius of 1 μm according to Embodiment 1 of the present invention;

[0033] Figure 3 This is a SEM image of the central region of a phase change memory cell with a radius of 1 μm in Embodiment 1 of the present invention.

[0034] Figure 4 This is an overall SEM image of the phase change memory cell with a radius of 1 μm after the electrodes are brought out, according to Embodiment 1 of the present invention.

[0035] Figure 5 This is a pulse waveform diagram of a phase-change memory cell with a radius of 1 μm according to Embodiment 1 of the present invention;

[0036] Figure 6 The cycle count curve for the phase change memory cell with a radius of 100 μm according to the present invention;

[0037] Figure 7 The cycle count curve of the phase change memory cell with a radius of 50 μm in this invention;

[0038] Figure 8 The cycle count curve of the phase change memory cell with a radius of 10 μm in this invention;

[0039] Figure 9 The cycle count curve is for the phase change memory cell with a radius of 1 μm according to the present invention.

[0040] Figure 10 This is a comparison chart of the number of cycles for phase-change memory cells with different radii according to the present invention;

[0041] Figure 11 The diagram shows the electrothermal simulation analysis of phase change memory cells with different radii according to the present invention; where ad represents phase change memory cells with radii of 100μm, 50μm, 10μm and 1μm respectively.

[0042] Explanation of reference numerals in the attached figures: 1-top electrode layer, 2-insulating protective layer, 3-column phase change layer, 4-silicon substrate with bottom electrode layer. Detailed Implementation

[0043] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0044] Example 1

[0045] Reference Figure 1-2 As shown, a small-sized phase-change memory cell and its fabrication method specifically include the following steps:

[0046] S11. A silicon substrate 4 with a bottom electrode layer is provided, wherein the bottom electrode layer of the silicon substrate is selected from Pt electrode sheets.

[0047] In practice, the silicon substrate is first cleaned by placing it in acetone, ethanol, and deionized water for ultrasonic cleaning for about 10 minutes. After ultrasonic cleaning, the residual liquid on the surface is blown away with a nitrogen gun and dried for later use.

[0048] S12. A phase change layer is formed on the silicon substrate 4 with a bottom electrode layer:

[0049] In this process, the cleaned substrate is attached to the sputtering sample stage using adhesive tape. Thin films are prepared using pulsed laser deposition with the following parameters: gas pressure 1 × 10⁻⁶. -3 The laser energy was 200 mJ, and the deposition time was 5 min. After deposition, the sample was removed from the vacuum chamber and sealed for storage.

[0050] The phase change layer is made of Ge2Sb2Se4Te1 and has a thickness of 200 nm.

[0051] S13. Etching columnar phase transition layer 3 using an ion beam:

[0052] In practice, the prepared sample is attached to the SEM sample stage and placed in a vacuum chamber for preparation. Two concentric circles are drawn in the area to be cut, and the cutting area is the ring formed by these two circles. The cutting height is greater than 1.5 times the thickness of the cross-sectional film layer. The current of the cutting probe is set to 3nA, and the cutting time is controlled at 2 minutes. In SEM mode, a larger current (Iprobe>3nA) is selected for real-time observation. During observation, the sample stage must not be moved. BeamShift can be used for fine-tuning of the image position.

[0053] The radius of the etched cylindrical phase change layer 3 is 1 μm; the size of the etched ring is twice the diameter of the cylindrical phase change layer 3.

[0054] S14. Deposit an insulating protective layer 2 around the etched columnar phase change layer 3:

[0055] In practice, a dual-beam microscope was used to deposit insulating material SiO2 on the etched ring and the outer phase transition layer; the parameters of the deposition electrode were set as follows: the deposition recipe (300pA, 700pA) was selected, and the deposition time was controlled to be 2 min.

[0056] The thickness of the insulating protective layer is 50nm.

[0057] S15, Deposition of top electrode layer 1:

[0058] In practice, electrode material Pt is deposited on the surface of the insulating protective layer to form the top electrode layer 1. Before deposition, the state of the raw materials is checked and the parameters of the deposition electrode are set: select the deposition recipe (300pA, 700pA), modify the deposition thickness as needed, and control the deposition time to 2 minutes.

[0059] A central cylinder is selected as the starting point, and an electrode line is deposited as the lead-out point. At the same time, a square electrode plate with a side length of 30μm is deposited at the end point as the probe contact point during testing.

[0060] Test Example 1

[0061] The small-sized phase-change memory cell prepared in Example 1 was characterized, and the results are as follows: Figure 3-4 As shown. First, the surface morphology of the central cylinder was photographed using SEM. Figure 3 As can be seen, the central cylindrical region and phase change unit are present, with the phase change unit having a radius of 1 μm. This indicates that the phase change memory unit prepared in this invention is consistent with expectations and has a well-preserved structure. Next, an SEM image of the overall structure was captured. Figure 4 As can be seen, the electrode plate has a side length of 30 μm, and the conductive lines extending from the central cylinder are well connected, ensuring the requirements for subsequent testing. Placing a 10 μm diameter probe on the electrode plate allows for electrical-related tests.

[0062] Test Example 2

[0063] The resistance-voltage ratio during the Set / Reset process of the phase-change memory device fabricated in Example 1 was tested. A Keithley 4200A-SCS semiconductor device analyzer was used to obtain the resistance value, and a Keysight-33220A function generator was used to apply the pulse voltage required for the phase transition. The pulse waveform is shown below. Figure 5 As shown. From Figure 5As can be seen, the Reset waveform is a short, high pulse, corresponding to 100ns and 1.8V. The Set waveform is a wide, low pulse, corresponding to 200ns and 0.8V. The Read pulse is 0.1V, intended not to affect the resistance. First, several alternating Set / Reset pulses are applied, followed by a Read pulse after a Reset pulse to read the amorphous resistance. Similarly, applying a Read pulse after a Set pulse allows reading the crystalline resistance.

[0064] Figure 6-9 The following are pulse cycle test diagrams for phase change memory cells with radii of 100μm, 50μm, 10μm, and 1μm, respectively. Figure 6 As shown, an electrode with a radius of 100 μm was fabricated based on Example 1 and resistance cycling tests were performed, achieving a GSST phase change unit with over 1000 flip-flops. To further improve the performance of the phase change unit, 50 μm and 10 μm phase change memory units were fabricated, such as... Figure 7-8 As shown, the number of cycles was improved. Finally, the phase-change memory cell with a radius of 1 μm from Example 1 was tested, as shown... Figure 9 As shown, this phase-change memory cell with a radius of 1 μm can achieve up to 13,000 phase-change resistance cycles, meeting the requirements for multiple cycles in practical device applications. It also features a minimum trigger voltage of 0.8V, enabling low-power applications. Furthermore, the phase-change memory cell prepared in this invention exhibits excellent high-low resistance contrast, maintaining a 1000-fold difference. Therefore, a stable phase-change memory structure using GSST phase-change material was obtained through an electrical pulse method.

[0065] For ease of comparison, based on the results of previous cycle tests, the maximum number of cycles for phase-change memory cells of different sizes from 100μm to 1μm has been compiled together, as follows: Figure 10 As shown. From Figure 10 As can be seen, the cycling performance gradually improves with decreasing sample size, achieving a maximum of 13,000 switching cycles for the GSST material. This demonstrates that the phase-change memory unit of this invention exhibits excellent durability, which is beneficial for practical device applications.

[0066] Test Example 3

[0067] Based on Example 1, electrothermal simulation analysis was performed on phase change memory cells with radii of 100μm, 50μm, 10μm, and 1μm. Figure 11 As shown, electrothermal analysis was performed using COMSOL software, capturing the heating patterns in the central and peripheral regions. Figure 11a-11c are simulation images of phase change memory cells with radii of 100μm, 50μm, and 10μm, respectively. It can be seen that the two largest phase change memory cells generate significantly more heat at their centers than at the periphery. Therefore, the central region is more susceptible to damage after multiple phase changes, leading to failure. The sample with a radius of 10μm shows some improvement, but uneven heating between the center and periphery is still visible. In contrast, Figure 11 Figure d shows a 1μm phase change memory cell prepared using the new method. It can be observed that the internal and external heating is relatively uniform, thus enabling uniform phase change throughout the entire phase change layer. Electrothermal simulation analysis theoretically demonstrates that the phase change performance and durability of the phase change cell of this invention are further improved as the size decreases.

[0068] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A phase-change memory cell, characterized in that, The phase-change memory unit includes: Substrate; A bottom electrode layer is disposed in the substrate, wherein the upper contact surface of the bottom electrode layer is exposed outside the substrate and is flush with the upper surface of the substrate; A columnar phase change layer is disposed in the middle of the contact surface on the bottom electrode layer; the thickness of the columnar phase change layer is 150nm-250nm, and the radius is 100nm-100μm; the material of the columnar phase change layer is Ge2Sb2Se4Te1. An insulating protective layer is disposed around the cylindrical phase change layer; the total thickness of the insulating protective layer is 50nm-100nm thicker than the thickness of the cylindrical phase change layer. A top electrode layer is disposed above the cylindrical phase change layer and the insulating protective layer.

2. The phase-change memory unit according to claim 1, characterized in that, The substrate is made of silicon.

3. The phase-change memory unit according to claim 1, characterized in that, The insulating protective layer is made of SiO2.

4. The phase-change memory unit according to claim 1, characterized in that, The bottom electrode layer and the top electrode layer are both made of Ti, Au, Pt or W.

5. The method for preparing the phase-change memory cell according to any one of claims 1-4, characterized in that, Includes the following steps, (1) A bottom electrode layer is embedded in a substrate, wherein the upper contact surface of the bottom electrode layer is exposed outside the substrate and is flush with the upper surface of the substrate; (2) A columnar phase change layer is set in the middle of the contact surface on the bottom electrode layer using pulsed laser deposition and ion beam etching techniques; (3) An insulating protective layer is deposited around the cylindrical phase change layer using ion beam deposition. (4) A top electrode layer is deposited on the surface of the cylindrical phase change layer and the insulating protective layer by ion beam deposition to obtain the phase change storage unit.

6. The method for preparing a phase-change memory cell according to claim 5, characterized in that, In step (2), the gas pressure of the pulsed laser deposition method is less than 1×10⁻⁶. -3 Pa, laser energy is 200-250mJ.

7. The method for preparing a phase-change memory cell according to claim 5, characterized in that, In step (2), the cutting current of the ion beam etching technology is 700pA-30nA, and the cutting time is 1min-5min.

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