Resistive random access memory and methods of making the same

Abstract

The application provides a resistive random access memory and a preparation method thereof. The resistive random access memory comprises a first electrode, a resistive switching layer and a second electrode arranged in sequence. The second electrode comprises a first sub-electrode layer arranged on the resistive switching layer, a limiting layer arranged on the first sub-electrode layer and a second sub-electrode layer arranged on the limiting layer. The limiting layer is used for limiting the migration of metal atoms from the second sub-electrode layer to the first sub-electrode layer. The metal atom concentration of the second sub-electrode layer is greater than that of the first sub-electrode layer, and the metal atom concentration of the first sub-electrode layer is greater than that of the limiting layer. The application can improve the uniformity of the operating voltage of the resistive random access memory, improve the thermal stability without sacrificing the operating voltage, and meet the erasing error rate requirement.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a resistive random access memory and its preparation method. Background Technology

[0002] Resistive random-access memory (RRAM) is a type of non-volatile memory (NVM) that has gained increasing attention in the field due to its smaller size, faster read / write speeds, longer data retention times, lower power consumption, higher reliability, and compatibility with semiconductor fabrication processes. The basic structure of RRAM consists of a variable resistor layer sandwiched between upper and lower electrodes. An applied voltage causes the variable resistor material to switch between a high-resistance state (HRS) and a low-resistance state (LRS), and these different resistance states are then encoded as 1 or 0 to store and identify data.

[0003] Conductive bridge resistance random access memory (CBRRAM) is a commonly used resistive random access memory. Its top electrode, also called the active electrode, provides the metal raw material for the conductive filament. The top electrode affects the thermal stability of the CBRRAM, the operating voltage for filament formation, and the erasure performance of the filament; therefore, the top electrode process is crucial. Traditional top electrodes struggle to achieve good uniformity and simultaneously meet the requirements of high thermal stability, low operating voltage, and good erasure performance.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a resistive random access memory and its preparation method, which solves the problems in the prior art where it is difficult to achieve good uniformity of the top electrode, and it is also difficult to simultaneously meet the requirements of high thermal stability, low operating voltage and good erasure effect.

[0006] To achieve the above and other related objectives, the present invention provides a resistive random access memory (RRAM), comprising: a first electrode, a resistive switching memory layer, and a second electrode arranged sequentially; the second electrode comprising: a first sub-electrode layer disposed on the resistive switching memory layer; a confinement layer disposed on the first sub-electrode layer; and a second sub-electrode layer disposed on the confinement layer; the confinement layer is used to restrict the migration of metal atoms from the second sub-electrode layer to the first sub-electrode layer, wherein the metal atom concentration of the second sub-electrode layer is greater than the metal atom concentration of the first sub-electrode layer, and the metal atom concentration of the first sub-electrode layer is greater than the metal atom concentration of the confinement layer; wherein the metal atom concentration is the ratio of the number of metal atoms to the number of non-metal atoms in the corresponding layer, or the ratio of the number of metal atoms to the number of impurity metal atoms in the corresponding layer.

[0007] Optionally, during high-temperature annealing, the confinement layer restricts the migration of metal atoms from the second sub-electrode layer to the first sub-electrode layer. By controlling the temperature window and / or adjusting the thickness of the confinement layer, the number of metal atoms migrating from the second sub-electrode layer to the first sub-electrode layer can be controlled.

[0008] Optionally, the metal atom concentration of the second sub-electrode layer is 1.2 to 2 times that of the metal atom concentration of the first sub-electrode layer, and the metal atom concentration of the first sub-electrode layer is 1.1 to 1.7 times that of the metal atom concentration of the confinement layer.

[0009] Optionally, the metal atom concentration of the first sub-electrode layer ranges from 110% to 170%, the metal atom concentration of the confinement layer ranges from 101% to 145%, and the metal atom concentration of the second sub-electrode layer ranges from 125% to 200%.

[0010] Optionally, the thickness of the second sub-electrode layer is greater than the thickness of the confinement layer.

[0011] Optionally, the thickness of the limiting layer is greater than or equal to the thickness of the first sub-electrode layer.

[0012] Optionally, the thickness of the first sub-electrode layer ranges from 1 to 10 atomic layers, the thickness of the confinement layer ranges from 1 to 20 atomic layers, and the thickness of the second sub-electrode layer ranges from 100 atomic layers or more.

[0013] Optionally, the materials of the first sub-electrode layer, the confinement layer, and the second sub-electrode layer include one or more of metal nitrides, metal silicides, and metal germanides.

[0014] Optionally, the metals of the first sub-electrode layer, the confinement layer, and the second sub-electrode layer include one or more of copper, aluminum, and silver.

[0015] Optionally, the materials of the first sub-electrode layer, the confinement layer, and the second sub-electrode layer include metals doped with impurity metals, wherein the metals include one or more of copper, aluminum, and silver, and the impurity metals include one or more of titanium and tantalum.

[0016] Optionally, the resistive switching memory layer includes at least a reversible high-resistivity state and a low-resistivity state.

[0017] This invention also provides a method for fabricating a resistive random access memory (RAM), the method comprising the steps of: forming a first electrode, a resistive switching memory layer, and a second electrode arranged sequentially; forming the second electrode on the resistive switching memory layer, including: forming a first sub-electrode layer on the resistive switching memory layer; forming a confinement layer on the first sub-electrode layer; forming a second sub-electrode layer on the confinement layer; the confinement layer is used to restrict the migration of metal atoms from the second sub-electrode layer to the first sub-electrode layer, the metal atom concentration of the second sub-electrode layer is greater than the metal atom concentration of the first sub-electrode layer, the metal atom concentration of the first sub-electrode layer is greater than the metal atom concentration of the confinement layer, wherein the metal atom concentration refers to the ratio of the number of metal atoms to the number of non-metal atoms in the corresponding layer.

[0018] Optionally, forming a top electrode on the resistive switching memory layer includes: a) forming a first sub-electrode layer on the resistive switching memory layer by a metal compound sputtering process or an impurity metal doping sputtering process; b) increasing the compound ratio or the doping concentration of the impurity metal based on step a) and forming the confinement layer on the first sub-electrode layer by a metal compound sputtering process or an impurity metal doping sputtering process; c) forming a second sub-electrode layer on the confinement layer by a metal compound sputtering process or an impurity metal doping sputtering process.

[0019] Optionally, increasing the compound ratio or the doping concentration of the impurity metal based on step a) includes: for the metal compound sputtering process, reducing the sputtering power to decrease the sputtering speed of the metal target and / or increasing the reactive gas, thereby increasing the chemical reaction ratio between the metal atoms and the reactive gas; for the impurity metal doping sputtering process, increasing the sputtering speed of the impurity metal target to increase the concentration of impurity metal atoms.

[0020] As described above, the resistive random access memory and its fabrication method of the present invention have the following beneficial effects:

[0021] The top electrode of this invention comprises a sandwich structure of a first sub-electrode layer, a confinement layer, and a second sub-electrode layer. First, the first sub-electrode layer, closest to the resistive switching memory layer, is relatively thin, with a moderate and limited concentration of free metal atoms, ensuring it is insufficient to conduct the resistive switching memory layer under thermal migration. Second, the middle confinement layer, with a lower concentration of free metal atoms, effectively reduces the diffusion rate of free metal atoms from the second sub-electrode layer to the first sub-electrode layer, mitigating the thermal effect of the second sub-electrode layer on the first sub-electrode layer and thus increasing the thermal stability of the resistive random access memory. Third, the metal atom concentration of the first sub-electrode layer can be consistent with that of a conventional top electrode and can be adjusted according to actual needs, as it does not require substantial changes to the initial metal atom concentration of the first sub-electrode layer, thus having a smaller impact on the operating voltage. Fourth, sufficient thermal motion also improves the uniformity of the top electrode. Fifth, the second sub-electrode layer has a higher metal atom concentration, providing a sufficient metal atom reserve for the top electrode, resulting in the most active thermal motion of metal atoms and the best uniformity. This invention can improve the uniformity of the operating voltage of resistive random access memory, improve thermal stability without sacrificing the operating voltage, and meet the erase error rate requirements. Attached Figure Description

[0022] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0023] Figure 1 The diagram shown is a schematic of a resistive random access memory.

[0024] Figure 2 The diagram shows a schematic of another type of resistive random access memory.

[0025] Figures 3-7 The diagram shows the structural schematics of each step in the fabrication method of the resistive random access memory according to an embodiment of the present invention. Figure 7 The diagram shown is a structural schematic of a resistive random access memory according to an embodiment of the present invention.

[0026] Figure 8 The graphs shown represent the relationship between the metal atom concentration and thickness of the first sub-electrode layer, the confinement layer, and the second sub-electrode layer in an embodiment of the present invention.

[0027] Component labeling explanation: 101 bottom electrode, 102 resistive switching memory layer, 103 top electrode, 201 bottom electrode, 202 resistive switching memory layer, 203 first layer electrode, 204 second layer electrode, 301 bottom electrode, 302 resistive switching memory layer, 303 first sub-electrode layer, 304 confinement layer, 305 second sub-electrode layer. Detailed Implementation

[0028] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0030] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0031] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0032] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0033] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0034] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0035] like Figure 1 As shown, an RRAM structure includes a bottom electrode 101, a resistive switching memory layer 102, and a top electrode 103. The top electrode 103 has a single material structure, making it difficult to simultaneously meet the requirements for thermal stability and operating voltage. For example... Figure 2 The diagram shows another RRAM structure, which includes a bottom electrode 201, a resistive switching memory layer 202, and a top electrode. The top electrode is composed of a first layer electrode 203 and a second layer electrode 204. The difference between the first layer electrode 203 and the second layer electrode 204 is the difference in metal atom concentration. This design can meet the thermal stability requirements, but it has high process requirements for the first layer electrode 203, the operating voltage is not easy to control, and the uniformity is relatively poor.

[0036] like Figure 7 As shown, this embodiment provides a resistive random access memory (RAM). The resistive RAM includes: a bottom electrode 301; a resistive switching memory layer 302 having a variable resistance and disposed on the bottom electrode 301; and a top electrode disposed on the resistive switching memory layer 302. The top electrode includes: a first sub-electrode layer 303 disposed on the resistive switching memory layer 302; a confinement layer 304 disposed on the first sub-electrode layer 303; and a second sub-electrode layer 305 disposed on the confinement layer 304. The confinement layer 304 is used to confine metal atoms from the second sub-electrode layer 305. Sub-electrode layer 305 migrates to first sub-electrode layer 303. The metal atom concentration of second sub-electrode layer 305 is greater than that of first sub-electrode layer 303. The metal atom concentration of first sub-electrode layer 303 is greater than that of confinement layer 304. The metal atom concentration is the ratio of the number of metal atoms to the number of non-metal atoms in the corresponding layer, or the ratio of the number of metal atoms to the number of impurity metal atoms in the corresponding layer. The relationship between the metal atom concentration and thickness of first sub-electrode layer 303, confinement layer 304, and second sub-electrode layer 305 is as follows: Figure 8 As shown.

[0037] During high-temperature annealing, the confinement layer 304 restricts the migration of metal atoms from the second sub-electrode layer 305 to the first sub-electrode layer 303. By controlling the temperature window and / or adjusting the thickness of the confinement layer 304, the number of metal atoms migrating from the second sub-electrode layer 305 to the first sub-electrode layer 303 is controlled, thereby improving the thermal stability of the resistive random access memory, reducing the influence of temperature on the operating voltage, and improving uniformity.

[0038] In one embodiment, the resistive random access memory further includes an integrated chip. The integrated chip includes a substrate in which components such as transistors, or CMOS devices, are disposed. An interlayer dielectric and an interconnect layer are disposed on the substrate for the lead-out of the components. In some embodiments, the interlayer dielectric may be silicon dioxide, borosilicate glass, etc., and the interconnect layer may be a conductive metal clad in copper, aluminum, or tungsten.

[0039] like Figure 7 As shown, the bottom electrode 301 can directly contact the interconnect layer. In some embodiments, the bottom electrode 301 can be made of one or more materials from the group consisting of titanium (Ti), tantalum (Ta), nickel (Ni), copper (Cu), tungsten (W), hafnium (Hf), zirconium (Zr), niobium (Nb), yttrium (Y), zinc (Zn), cobalt (Co), aluminum (Al), silicon (Si), germanium (Ge), and their alloys.

[0040] like Figure 7 As shown, the resistive switching memory layer 302 is disposed above the bottom electrode 301. In some embodiments, the resistive switching memory layer 302 can directly contact the bottom electrode 301. The resistive switching memory layer 302 includes at least a reversible high-resistance state and a low-resistance state. Specifically, the resistive switching memory layer 302 is configured to include a high-resistance state in a first data state (e.g., 0) and a low-resistance state in a second data state (e.g., 1), and can undergo a reversible change between the high-resistance state and the low-resistance state to store data states. The resistive switching memory layer 302 includes a high-k dielectric material with variable resistance. For example, the resistive switching memory layer 302 can include transition metal oxides, such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (TaO), etc., and is not limited to the examples listed herein.

[0041] like Figure 7 As shown, in one embodiment, the metal atom concentration of the second sub-electrode layer 305 is 1.2 to 2 times that of the metal atom concentration of the first sub-electrode layer 303, and the metal atom concentration of the first sub-electrode layer 303 is 1.1 to 1.7 times that of the metal atom concentration of the confinement layer 304.

[0042] In one embodiment, the metal atom concentration of the first sub-electrode layer 303 ranges from 110% to 170%, the metal atom concentration of the confinement layer 304 ranges from 101% to 145%, and the metal atom concentration of the second sub-electrode layer 305 ranges from 125% to 200%.

[0043] In some embodiments, the thickness of the second sub-electrode layer 305 is greater than the thickness of the confinement layer 304, and the thickness of the confinement layer 304 is greater than or equal to the thickness of the first sub-electrode layer 303. For example, in one embodiment, the thickness of the first sub-electrode layer 303 ranges from 1 to 10 atomic layers to ensure that it is insufficient to conduct the resistive switching memory layer under thermal migration. The thickness of the confinement layer 304 ranges from 1 to 20 atomic layers and has a low concentration of free metal atoms to effectively reduce the rate at which free metal atoms from the second sub-electrode layer 305 diffuse into the first sub-electrode layer 303, thus mitigating the impact of the second sub-electrode layer 305 on the first sub-electrode layer 303 under thermal effects, thereby increasing the thermal stability of the resistive random access memory. The thickness of the second sub-electrode layer 305 ranges from 100 atomic layers or more to provide a sufficient metal atom reserve pool for the top electrode. Specifically, the thickness of the first sub-electrode layer 303 can be 5 atomic layers, the thickness of the confinement layer 304 can be 10 atomic layers, and the thickness of the second sub-electrode layer 305 can be 150 atomic layers.

[0044] In one embodiment, the materials of the first sub-electrode layer 303, the confinement layer 304, and the second sub-electrode layer 305 include one or more of metal nitrides, metal silicides, and metal germanides. The metal nitride may be, for example, aluminum nitride (AlNx), the metal silicide may be, for example, aluminum silicide (AlSix), copper silicide (CuSix), silver silicide (AgSix), etc., and the metal germanide may be, for example, aluminum germanide (AlGex), copper germanide (CuGex), silver germanide (AgGex). Taking aluminum nitride (AlNx) as an example, the metal atom concentration can be expressed as a 1:x value.

[0045] In one embodiment, the metals of the first sub-electrode layer, the confinement layer, and the second sub-electrode layer comprise one or more of copper, aluminum, and silver. In a specific example, the materials of the first sub-electrode layer 303, the confinement layer 304, and the second sub-electrode layer 305 comprise metals doped with impurity metals, wherein the metals comprise one or more of copper, aluminum, and silver, and the impurity metals comprise one or more of titanium and tantalum. For example, the impurity metal doped metal can be titanium-doped aluminum (AlTix), wherein the metal atom concentration can be expressed as a 1:x value.

[0046] The top electrode of the present invention includes a sandwich structure of a first sub-electrode layer 303, a confinement layer 304, and a second sub-electrode layer 305. First, the first sub-electrode layer 303, closest to the resistive switching memory layer, is relatively thin, with a moderate and limited concentration of free metal atoms, ensuring that it is insufficient to enable the resistive switching memory layer to conduct under thermal migration. Second, the middle confinement layer 304 has a low concentration of free metal atoms, which can effectively reduce the diffusion rate of free metal atoms from the second sub-electrode layer 305 to the first sub-electrode layer 303, thus mitigating the thermal effect of the second sub-electrode layer 305 on the first sub-electrode layer 303. The invention improves the uniformity of the operating voltage of resistive random access memory (RAM) by increasing thermal stability. Third, the metal atom concentration of the first sub-electrode layer 303 can be consistent with that of the traditional top electrode and can be adjusted as needed. Since the initial metal atom concentration of the first sub-electrode layer 303 does not need to be substantially changed, the impact on the operating voltage is also small. Fourth, sufficient thermal motion also improves the uniformity of the top electrode. Fifth, the second sub-electrode layer 305 has a higher metal atom concentration, providing a sufficient metal atom reserve for the top electrode, resulting in the most active thermal motion and the best uniformity.

[0047] In one embodiment, the resistive random access memory further includes a top insulating layer and a top interconnect layer, the top interconnect layer including a top metal via and a connecting metal portion disposed on the top insulating layer.

[0048] like Figures 3-7 As shown, the present invention also provides a method for fabricating a resistive random access memory (RAM). The basic structure of the resistive RAM can be found in the above embodiments. The fabrication method includes the following steps:

[0049] First, in step 1), a substrate (not shown) is provided on which an interconnect layer is formed.

[0050] For example, the substrate may contain components such as transistors or CMOS devices, and the substrate may have an interlayer dielectric and an interconnect layer for the lead-out of the components. In some embodiments, the interlayer dielectric may be silicon dioxide, borosilicate glass, etc., and the interconnect layer may be a conductive metal clad in copper, aluminum, or tungsten.

[0051] like Figure 3 As shown, then step 2) is performed to form a bottom electrode 301 on the interconnect layer.

[0052] For example, the bottom electrode 301 can be formed on the interconnect layer by a sputtering process (such as magnetron sputtering) or a metal vapor deposition process.

[0053] like Figure 4 As shown, then step 3) is performed to form a resistive switching memory layer 302 on the bottom electrode 301, the resistive switching memory layer 302 having a variable resistance.

[0054] For example, a resistive switching memory layer 302 can be formed on the bottom electrode 301 by means of processes such as sputtering, reactive sputtering, chemical vapor deposition, or atomic layer deposition.

[0055] like Figures 5-7 As shown, then step 4) is performed to form a top electrode on the resistive switching memory layer, including the following steps:

[0056] like Figure 5 As shown, step 4-1) is performed to form a first sub-electrode layer 303 on the resistive switching memory layer;

[0057] like Figure 6 As shown, then step 4-2) is performed to form a confinement layer 304 on the first sub-electrode layer 303;

[0058] like Figure 7 As shown, step 4-3 is performed last to form a second sub-electrode layer 305 on the confinement layer 304; the confinement layer 304 is used to restrict the migration of metal atoms from the second sub-electrode layer 305 to the first sub-electrode layer 303. The metal atom concentration of the second sub-electrode layer 305 is greater than the metal atom concentration of the first sub-electrode layer 303, and the metal atom concentration of the first sub-electrode layer 303 is greater than the metal atom concentration of the confinement layer 304. The metal atom concentration refers to the ratio of the number of metal atoms to the number of non-metal atoms in the corresponding layer.

[0059] In some embodiments, forming a top electrode on the resistive switching memory layer may specifically include the following steps:

[0060] Step a) The first sub-electrode layer 303 is formed on the resistive switching memory layer by a metal compound sputtering process or an impurity metal doping sputtering process;

[0061] Step b) Based on step a), increase the compound ratio or the doping concentration of the impurity metal, and form the confinement layer 304 on the first sub-electrode layer 303 by metal compound sputtering process or impurity metal doping sputtering process;

[0062] Optionally, increasing the compound ratio or the doping concentration of the impurity metal based on step a) includes:

[0063] For metal compound sputtering processes, the sputtering rate of the metal target can be reduced by decreasing the sputtering power, and / or by increasing the reactive gas, thereby increasing the chemical reaction ratio between metal atoms and the reactive gas. For example, if the first sub-electrode layer 303 and the confinement layer 304 are AlNx, the metal target material is Al, and the introduced reactive gas (nitrogen source gas) can be at least one selected from the gas group composed of N2O, NO2, NO, N2O2, N2, and NH3. The first method is to reduce the sputtering rate of the aluminum target by decreasing the sputtering power while maintaining the nitrogen source gas flow rate, thereby reducing the Al content in the AlNx material and thus reducing the metal atom concentration 1:x value. The second method is to maintain the sputtering rate of the aluminum target while increasing the nitrogen source gas flow rate, thereby increasing the N content in the AlNx material and thus reducing the metal atom concentration 1:x value.

[0064] In impurity metal doping sputtering processes (such as magnetron co-sputtering), the concentration of impurity metal atoms can be increased by increasing the sputtering velocity of the impurity metal target while decreasing or maintaining the sputtering velocity of the target itself. For example, for AlTix materials, the sputtering process uses two targets: an aluminum target and a titanium target. By increasing the sputtering velocity of the titanium target while maintaining or decreasing the sputtering velocity of the aluminum target, the Ti content in AlTix can be increased, thereby reducing the metal atom concentration 1:x. Alternatively, the effect of reducing the metal atom concentration 1:x can also be achieved by decreasing the sputtering velocity of the aluminum target while maintaining the sputtering velocity of the titanium target.

[0065] Step c), the second sub-electrode layer 305 is formed on the confinement layer 304 by a metal compound sputtering process or an impurity metal doping sputtering process.

[0066] It should be noted that the above examples provide a resistive random access memory and its fabrication method arranged in a vertical direction. In other examples, the resistive random access memory and its fabrication method can also be arranged in a horizontal direction or other arrangements, and are not limited to the examples listed above.

[0067] As described above, the resistive random access memory and its fabrication method of the present invention have the following beneficial effects:

[0068] The top electrode of the present invention includes a sandwich structure of a first sub-electrode layer 303, a confinement layer 304, and a second sub-electrode layer 305. First, the first sub-electrode layer 303, closest to the resistive switching memory layer, is relatively thin, with a moderate and limited concentration of free metal atoms, ensuring that it is insufficient to enable the resistive switching memory layer to conduct under thermal migration. Second, the middle confinement layer 304 has a low concentration of free metal atoms, which can effectively reduce the diffusion rate of free metal atoms from the second sub-electrode layer 305 to the first sub-electrode layer 303, thus mitigating the thermal effect of the second sub-electrode layer 305 on the first sub-electrode layer 303. The invention improves the uniformity of the operating voltage of resistive random access memory (RAM) by increasing thermal stability. Third, the metal atom concentration of the first sub-electrode layer 303 can be consistent with that of the traditional top electrode and can be adjusted as needed. Since the initial metal atom concentration of the first sub-electrode layer 303 does not need to be substantially changed, the impact on the operating voltage is also small. Fourth, sufficient thermal motion also improves the uniformity of the top electrode. Fifth, the second sub-electrode layer 305 has a higher metal atom concentration, providing a sufficient metal atom reserve for the top electrode, resulting in the most active thermal motion and the best uniformity.

[0069] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A resistive random access memory, characterized in that, The resistive random access memory includes: The first electrode, the resistive switching memory layer, and the second electrode are arranged in sequence. The second electrode includes: The first sub-electrode layer is disposed on the resistive switching memory layer; A limiting layer is disposed on the first sub-electrode layer; A second sub-electrode layer is disposed on the confinement layer; The confinement layer is used to restrict the migration of metal atoms from the second sub-electrode layer to the first sub-electrode layer. The metal atom concentration of the second sub-electrode layer is greater than that of the first sub-electrode layer, and the metal atom concentration of the first sub-electrode layer is greater than that of the confinement layer. The metal atom concentration is the ratio of the number of metal atoms to the number of non-metal atoms in the corresponding layer, or the ratio of the number of metal atoms to the number of impurity metal atoms in the corresponding layer. The metal atom concentration of the second sub-electrode layer is 1.2 to 2 times that of the first sub-electrode layer, and the metal atom concentration of the first sub-electrode layer is 1.1 to 1.7 times that of the confinement layer.

2. The resistive random access memory according to claim 1, characterized in that: During high-temperature annealing, the confinement layer restricts the migration of metal atoms from the second sub-electrode layer to the first sub-electrode layer. By controlling the temperature window and / or adjusting the thickness of the confinement layer, the number of metal atoms migrating from the second sub-electrode layer to the first sub-electrode layer can be controlled.

3. The resistive random access memory according to claim 1, characterized in that: The metal atom concentration of the first sub-electrode layer ranges from 110% to 170%, the metal atom concentration of the confinement layer ranges from 101% to 145%, and the metal atom concentration of the second sub-electrode layer ranges from 125% to 200%.

4. The resistive random access memory according to claim 1, characterized in that: The thickness of the second sub-electrode layer is greater than the thickness of the confinement layer.

5. The resistive random access memory according to claim 1, characterized in that: The thickness of the limiting layer is greater than or equal to the thickness of the first sub-electrode layer.

6. The resistive random access memory according to claim 1, characterized in that: The thickness of the first sub-electrode layer ranges from 1 to 10 atomic layers, the thickness of the confinement layer ranges from 1 to 20 atomic layers, and the thickness of the second sub-electrode layer ranges from 100 atomic layers or more.

7. The resistive random access memory according to claim 1, characterized in that: The materials of the first sub-electrode layer, the confinement layer, and the second sub-electrode layer include one or more of metal nitrides, metal silicides, and metal germanides.

8. The resistive random access memory according to claim 1 or 7, characterized in that: The metals of the first sub-electrode layer, the confinement layer, and the second sub-electrode layer include one or more of copper, aluminum, and silver.

9. The resistive random access memory according to claim 1, characterized in that: The first sub-electrode layer, the confinement layer, and the second sub-electrode layer are made of metals doped with impurity metals, including one or more of copper, aluminum, and silver, and the impurity metals include one or more of titanium and tantalum.

10. The resistive random access memory according to claim 1, characterized in that: The resistive switching memory layer includes at least a reversible high-resistivity state and a low-resistivity state.

11. A method for fabricating a resistive random access memory as described in any one of claims 1 to 10, characterized in that, The preparation method includes the following steps: A first electrode, a resistive switching memory layer, and a second electrode are formed in sequence, wherein the second electrode is formed on the resistive switching memory layer, including: A first sub-electrode layer is formed on the resistive switching memory layer; A confinement layer is formed on the first sub-electrode layer; A second sub-electrode layer is formed on the confinement layer; The confinement layer is used to restrict the migration of metal atoms from the second sub-electrode layer to the first sub-electrode layer. The metal atom concentration of the second sub-electrode layer is greater than that of the first sub-electrode layer, and the metal atom concentration of the first sub-electrode layer is greater than that of the confinement layer. The metal atom concentration refers to the ratio of the number of metal atoms to the number of non-metal atoms in the corresponding layer.

12. The method for fabricating a resistive random access memory according to claim 11, characterized in that: A top electrode is formed on the resistive switching memory layer, comprising: a) The first sub-electrode layer is formed on the resistive switching memory layer by a metal compound sputtering process or an impurity metal doping sputtering process; b) Based on step a), increase the compound ratio or the doping concentration of the impurity metal, and form the confinement layer on the first sub-electrode layer by metal compound sputtering process or impurity metal doping sputtering process; c) The second sub-electrode layer is formed on the confinement layer by a metal compound sputtering process or an impurity metal doping sputtering process.

13. The method for fabricating a resistive random access memory according to claim 12, characterized in that: Increasing the compound ratio or the doping concentration of the impurity metal based on step a) includes: For metal compound sputtering processes, the sputtering speed of the metal target is reduced by decreasing the sputtering power and / or the reactive gas is increased, thereby improving the chemical reaction ratio between metal atoms and reactive gas. In the impurity metal doping sputtering process, the concentration of impurity metal atoms is increased by increasing the sputtering rate of the impurity metal target.

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