Switching clock phase shifting for multi-port buck-boost converter

Abstract

Described herein are multi-port USB power delivery C-type (USB-C / PD) power converters for switching clock phase shifting. The multi-port USB-C / PD power converter includes a first PD port, a second PD port, and a power controller coupled to the first PD port and the second PD port. The power controller includes a first phase-controlled clock generator to generate a first phase-shifted clock signal by shifting a clock signal relative to a reference clock signal by a first phase, and a second phase-controlled clock generator to generate a second phase-shifted clock signal by shifting the clock signal relative to the reference clock signal by a second phase. The first PD port and the second PD port output power in response to a first control signal based on the first phase-shifted clock signal and a second control signal based on the second phase-shifted clock signal, respectively.

Description

[0001] priority

[0002] This application is an international application of U.S. Non-Provisional Application No. 17 / 410,888, filed on August 24, 2021, which claims the benefit of U.S. Provisional Application No. 63 / 073,884, filed on September 2, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to integrated circuits (ICs) that control the delivery of power from a Universal Serial Bus (USB) to an electronic device. Background Technology

[0004] Various electronic devices (e.g., smartphones, tablets, laptops, chargers, adapters, power banks, etc.) are configured to transmit power via a USB connector according to the USB Power Delivery protocol as defined in various versions and revisions of the USB Power Delivery (USB-PD) specification. For example, in some applications, an electronic device may be configured as a power consumer to receive power via a USB connector (e.g., for battery charging), while in other applications, it may be configured as a power provider to supply power to another device connected to it via a USB connector. In various applications, electronics manufacturers may also use power converters (e.g., buck-boost converters) that need to meet various USB-PD specification requirements, such as requirements for electromagnetic interference (EMI). Attached Figure Description

[0005] Figure 1 This is a schematic diagram of a buck-boost converter according to one embodiment.

[0006] Figure 2 This is a schematic diagram of a two-port power converter with a power controller according to one embodiment, the power controller being used to generate two phase-shifted clock signals for switching between the first port (p0) and the second port (p1) of the two-port power converter.

[0007] Figure 3 It is a timing diagram of a reference clock signal, a first phase-shift clock signal, a second phase-shift clock signal, a first control signal, and a second control signal according to one embodiment.

[0008] Figure 4 This is a schematic diagram of a dual-port buck-only power converter according to one embodiment.

[0009] Figure 5 This is a schematic diagram of a dual-port boost-only power converter according to one embodiment.

[0010] Figure 6 This is a flowchart of a method for providing phase-shifted switching control for a multi-port power converter according to one embodiment.

[0011] Figure 7 This is a block diagram of an on-die IC controller for a USB-PD subsystem having a phased clock generator in at least one embodiment. Detailed Implementation

[0012] The following description sets forth numerous specific details, such as examples of particular systems, components, methods, etc., to provide a good understanding of the various implementations of switching clock phase shifts for multiport power converters (e.g., buck-boost converters) described herein. However, it will be apparent to those skilled in the art that at least some implementations can be practiced without the specific details described herein. In other instances, well-known components, elements, or methods are presented in a simple block diagram format rather than in detail to avoid unnecessarily obscuring the subject matter described herein. Therefore, the specific details set forth below are merely exemplary. Specific implementations may differ from the exemplary details described and are still considered to be within the spirit and scope of this embodiment.

[0013] In this specification, the references to "implementation," "one implementation," "example implementation," "some implementations," and "various implementations" refer to specific features, structures, steps, operations, or characteristics described in connection with an implementation, which are included in at least one implementation. Furthermore, the phrases "implementation," "one implementation," "example implementation," "some implementations," and "various implementations" appearing in various places in this specification do not necessarily refer to the same implementation.

[0014] This specification includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate exemplary embodiments. These embodiments, also referred to herein as “examples,” are described in sufficient detail to enable those skilled in the art to practice embodiments of the claimed subject matter described herein. Embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.

[0015] This document describes various implementations of reference clock controllers and phase-controlled clock controllers in USB-C type controllers that can be configured to operate in various electronic devices. Examples of such electronic devices include, but are not limited to, personal computers (e.g., laptop computers, notebook computers, etc.), mobile computing devices (e.g., tablets, tablet computers, e-readers, etc.), mobile communication devices (e.g., smartphones, mobile phones, personal digital assistants, messaging devices, handheld PCs, etc.), connection and charging devices (e.g., cables, hubs, docking stations, adapters, chargers, etc.), audio / video / data recording and / or playback devices (e.g., cameras, recorders, handheld scanners, monitors, etc.), and other similar electronic devices that can communicate, charge batteries, and / or deliver power using a USB interface.

[0016] For example, as used herein, a "USB-enabled" device or system refers to a device or system that includes, is configured with, or is otherwise associated with a USB connector interface. A USB-enabled electronic device may conform to at least one release of the Universal Serial Bus (USB) specification. Examples of such USB specifications include, but are not limited to, USB specification revision 2.0, USB 3.0, USB 3.1, USB 3.2, and / or their various supplements, versions, and errata. The USB specification typically defines the characteristics of the differential serial bus (e.g., attributes, protocol specifications, transaction types, bus management, programming interfaces, etc.) required for designing and building standard communication systems and peripherals. For example, a USB-enabled peripheral device is attached to a USB-enabled host device via a host device's USB port to form a USB-enabled system. A USB 2.0 port includes a 5V power supply line (denoted as VBUS), differential pairs of data lines (denoted as D+ or DP and D– or DN), and a ground line (denoted as GND) for power return. The USB 3.0 port also provides VBUS, D+, D–, and GND lines for backward compatibility with USB 2.0. Additionally, the USB 3.0 port provides differential pairs for the transmitter data lines (denoted as SSTX+ and SSTX–), differential pairs for the receiver data lines (denoted as SSRX+ and SSRX–), a power line for power supply (denoted as DPWR), and a ground line for power return (denoted as DGND) to support the faster differential bus (USB SuperSpeed ​​Bus). The USB 3.1 port provides the same wiring as the USB 3.0 port for backward compatibility with both USB 2.0 and USB 3.0 communication, but extends the performance of the SuperSpeed ​​Bus through a series of features known as Enhanced SuperSpeed.

[0017] The various releases and / or versions of the USB Type-C specification define the latest technology for USB connectors referred to as USB Type-C (also referred to herein as "USB-C"). The USB Type-C specification defines Type-C receptacles, Type-C plugs, and Type-C cables that can support USB communication and power delivery over newer USB power delivery protocols defined in various revisions / releases of the USB-PD specification. Examples of USB Type-C functionality and requirements may include, but are not limited to, data and other communications according to USB 2.0 and USB 3.0 / 3.1, electromechanical limitations and performance requirements for Type-C cables, electromechanical limitations and performance requirements for Type-C receptacles, electromechanical limitations and performance requirements for Type-C plugs, requirements for Type-C to legacy cable assemblies and adapters, requirements for Type-C-based device detection and interface configuration, and optimized power delivery requirements for Type-C connectors. According to the USB Type-C specification, among other things, Type-C ports provide VBUS lines, D+ lines, D– lines, GND lines, SSTX+ lines, SSTX– lines, SSRX+ lines, and SSRX– lines. Additionally, Type-C ports provide sideband use (SBU) lines for signaling of sideband functions and configuration channels (or communication channels, CC) lines for discovering, configuring, and managing connections on Type-C cables. Type-C ports can be associated with Type-C plugs and / or Type-C receptacles. For ease of use, Type-C plugs and receptacles are designed as reversible pairs that operate regardless of plug-to-receptacle orientation. Therefore, a standard USB Type-C connector configured as a standard Type-C plug or receptacle provides pins for four VBUS lines, four ground return (GND) lines, two D+ lines (DP1 and DP2), two D– lines (DN1 and DN2), two SSTX+ lines (SSTXP1 and SSTXP2), two SSTX– lines (SSRXN1 and SSTXN2), two SSRX+ lines (SSRXP1 and SSRXP2), two SSRX– lines (SSRXN1 and SSRXN2), two CC lines (CC1 and CC2), and two SBU lines (SBU1 and SBU2).

[0018] Some USB-enabled electronic devices may conform to specific revisions and / or versions of the USB-PD specification. The USB-PD specification defines a standard protocol designed to maximize the functionality of USB-enabled devices by providing more flexible power delivery and data communication over a single USB-C cable via a USB-C port. The USB-PD specification also describes the architecture, protocols, power supply behavior, parameters, and wiring necessary for managing power delivery over USB-C cables up to 100W. According to the USB-PD specification, devices with USB-C ports (e.g., USB-enabled devices) can negotiate current and / or higher or lower voltages than allowed in older USB specifications (e.g., USB 2.0, USB 3.1, USB Battery Charging Specification versions 1.1 / 1.2, etc.) over USB-C cables. For example, the USB-PD specification defines the requirements for a power delivery contract (PD contract) that can be negotiated between a pair of USB-enabled devices. A PD contract can specify both the power level and the direction of power delivery that can be adapted to both devices, and can be dynamically renegotiated (e.g., without unplugging the devices) based on requests from either device and / or in response to various events and conditions (e.g., power role swapping, data role swapping, hard reset, power failure, etc.). As used herein, a “USB-PD subsystem” refers to one or more logic blocks and other analog / digital hardware circuitry that can be controlled by firmware in an IC controller and configured and operated to perform functions and meet the requirements specified in at least one release of the USB-PD specification. An IC controller can be implemented in a USB Type-C device. An IC controller can be implemented in a USB device.

[0019] Power delivery according to the USB-PD specification can be embodied in several different types of USB Type-C applications. Examples of such Type-C applications include, but are not limited to: Downlink Port (DFP) applications, in which an IC controller with a USB-PD subsystem is configured to provide a downlink USB port (e.g., in a USB-enabled host device); Uplink Port (UFP) applications, in which an IC controller with a USB-PD subsystem is configured to provide an uplink USB port (e.g., in a USB-enabled peripheral device or adapter); Dual Role Port (DRP) USB applications, in which an IC controller with a USB-PD subsystem is configured to support both DFP and UFP applications on the same USB port (e.g., a USB Type-C port configured to operate as either a power provider or a power consumer, or dynamically alternate between said two roles by using USB-PD power role switching); and Active Cable applications, in which an IC controller with a USB-PD subsystem is disposed in an Electronically Marked Cable Assembly (EMCA) Type-C cable and configured to operate the Electronically Marked Cable Assembly (EMCA) Type-C cable.

[0020] Some two-port power converters (or, typically, multi-port power converters) can deliver power from each port (e.g., up to 100 watts (W)). For example, in the case of a two-port buck-boost converter, the inductor current at each port can charge and discharge during the switching cycle to deliver output power through the respective port. One or more power controllers (e.g., power delivery controllers) can be used to drive high-side and low-side switches (e.g., field-effect transistors (FETs) with approximate gate capacitances up to 3 nanofarads) during the switching cycle to provide output power. The power controllers can drive the switches quickly (e.g., with rise / fall times of approximately 10 to 20 nanoseconds) to minimize switching losses. Because various high-side and low-side switches can be switched, this can cause high peak currents on the supply and ground terminals. If the two buck-boost converters of a two-port power converter switch at the same switching frequency and with a higher output load, twice the peak current can exist in a single switching cycle, which can lead to a higher dynamic voltage drop and potentially EMI problems.

[0021] The aspects of this disclosure address the aforementioned drawbacks by providing an architecture and method for controlling a two-port (or multi-port) power converter using a single power controller at the same switching frequency but with a phase shift. Including a phase shift between switching at each port reduces peak current in each switching cycle and further minimizes EMI issues. Because the two-port power converter is controlled by a single integrated circuit power controller, the power converter's footprint can be reduced due to the elimination of the need for an additional external clock pin to introduce a phase shift (compared to having two power controllers).

[0022] The details of the multiport power converter are described below. This document also describes various implementations of an IC controller that includes one or more clocks to generate a master clock and various phase-shifted slave clocks. In one example implementation, the multiport power converter includes a first power-delivery (PD) port, a second PD port, and a power controller coupled to the first PD port and the second PD port. The power controller includes: a reference clock generator for generating a reference clock signal having a first frequency; a high-frequency clock generator for generating a clock signal having a second frequency greater than the first frequency; a first phase-controlled clock generator for generating a first phase-shifted clock signal by shifting the clock signal by a first phase relative to the reference clock signal; and a second phase-controlled clock generator for generating a second phase-shifted clock signal by shifting the clock signal by a second phase relative to the reference clock signal. The first PD port outputs power in response to a first control signal based on the first phase-shifted clock signal. The second PD port outputs power in response to a second control signal based on the second phase-shifted clock signal.

[0023] Figure 1 This is a schematic diagram of a buck-boost converter 100 according to one embodiment. The buck-boost converter 100 includes an inductor 102, a first switch 104, a second switch 106, a third switch 108, and a fourth switch 110. Switches 104 and 110 are also referred to as high-side (HS) switches, and switches 106 and 108 are referred to as low-side (LS) switches. The first switch 104 is coupled to an input voltage (Vin) 130, and the fourth switch 110 is coupled to an output voltage (Vout) 140. The switches can be controlled to operate the buck-boost converter 100 in one of four modes, including buck mode, buck-boost (BB) buck mode, BB boost mode, and boost mode.

[0024] Figure 2This is a schematic diagram of a dual-port power converter 200 with a power controller 250 according to one embodiment, the power controller 250 being used to generate two phase-shifted clock signals for switching between a first port (p0) and a second port (p1) of the dual-port power converter 200. In some embodiments, the dual-port power converter 200 may be a USB-C type power delivery (USB-C / PD) power converter. The power converter 200 may include a first buck-boost converter 200a and a second buck-boost converter 200b corresponding to the first output port (p0) and the second output port (p1), respectively. As described below, the first output port and the second output port may output power based on the clock signals. The first output port may output a first output voltage (Vout_p0) 235, and the second output port may output a second output voltage (Vout_p1) 240. The first output port p0 (also referred to as the first power delivery (PD) port) and the second output port p1 (also referred to as the second PD port) may share an input voltage source (Vin) 230. The power converter 200 may also include a power controller 250 (also referred to as a PD controller) coupled to the first buck-boost converter 200a and the second buck-boost converter 200b. In some embodiments, the power controller 250 may be an integrated circuit (IC) USB-PD / C power controller.

[0025] The first buck-boost converter 200a includes an inductor 202, a first switch (HS1) 204, a second switch (LS1) 206, a third switch (LS2) 208, and a fourth switch (HS2) 210. The first switch 204 is coupled to an input voltage 230, and the fourth switch 210 is coupled to a first output voltage 235.

[0026] The second buck-boost converter 200b includes an inductor 212, a first switch (HS1) 214, a second switch (LS1) 216, a third switch (LS2) 218, and a fourth switch (HS2) 220. The first switch 214 is coupled to an input voltage 230, and the fourth switch 220 is coupled to a second output voltage 240.

[0027] The power controller 250 provides various controls (e.g., by sending one or more control signals, clock signals, voltages, etc.) to the first buck-boost converter 200a and the second buck-boost converter 200b. The power controller includes a low-frequency clock generator 252 (e.g., a reference clock generator) and a high-frequency clock generator 254. The power controller includes a first boost-side gate driver 260, a first buck-boost controller 262, a first buck-side gate driver 264, and a first phase-controlled clock generator 266 corresponding to the first port p0. The power controller 250 also includes a second boost-side gate driver 270, a second buck-boost controller 272, a second buck-side gate driver 274, and a second phase-controlled clock generator 276 corresponding to the second port p1. The power controller 250 may include one or more terminals coupled to the first port and one or more other terminals coupled to the second port.

[0028] Low-frequency clock generator 252 can generate a low-frequency (e.g., 50 kHz or 100 kHz) reference clock signal to be used as a reference clock signal (Ref_clk) 201. High-frequency clock generator 254 can generate a high-frequency (e.g., 24 MHz, 48 MHz, etc.) clock signal 203. Low-frequency clock generator 252 can be generated from high-frequency clock 203 using a clock division method. Each phased-array clock generator 266 and phased-array clock generator 276 receives the reference clock signal 201 from low-frequency clock generator 252 and the high-frequency clock signal 203 from high-frequency clock generator 254. Phased-array clock generator 266 can generate a first phase-shifted clock signal (Sync_clk_P0) 205 by introducing a first phase shift (e.g., time delay) using the high-frequency clock signal 203, based on the switching frequency of the first port (p0) (e.g., 200 kHz, 400 kHz, etc.). The phase-controlled clock generator 276 can introduce a second phase shift (e.g., a time delay) using a high-frequency clock signal 203 to generate a second phase-shifted clock signal (Sync_clk_P1) 215 based on the switching frequency of the second port (p1) (e.g., 200 kHz, 400 kHz, etc.). In some embodiments, the second phase shift can be different from the first phase shift, such that the switching of the LS switch and HS switch for the first port (p0) and the second port (p1) is out of phase with respect to each other, even if the switching frequencies of the first port (p0) and the second port (p1) are the same.

[0029] Regarding the first buck-boost converter 200a, a first buck-boost controller 262 receives a first phase-shifted clock signal 205 from a first phase-controlled clock generator 266. The first buck-boost controller 262 can generate a first control signal 207 to control a first boost-side gate driver 260, and can generate a second control signal 209 to control a first buck-side gate driver 264. The first boost-side gate driver 260 receives the first control signal 207, and the first buck-side gate driver 264 receives the second control signal 209. The first control signal 207 and the second control signal 209 can be based on the first phase-shifted clock signal 205. In some embodiments, the first control signal 207 and the second control signal 209 can be the same or similar. The first boost-side gate driver 260 can generate other control signals to control a third switch (LS2) 208 and a fourth switch (HS2) 210. The first buck-side gate driver 264 can generate other control signals to control a first switch (HS1) 204 and a second switch (LS1) 206.

[0030] Regarding the second buck-boost converter 200b, the second buck-boost controller 272 receives a second phase-shifted clock signal 215 from the second phase-controlled clock generator 276. The second buck-boost controller 272 can generate a first control signal 217 to control the second boost-side gate driver 270, and can generate a second control signal 219 to control the second buck-side gate driver 274. The second boost-side gate driver 270 receives the first control signal 217, and the second buck-side gate driver 274 receives the second control signal 219. The first control signal 217 and the second control signal 219 can be based on the second phase-shifted clock signal 215. In some embodiments, the first control signal 217 and the second control signal 219 can be the same or similar. The second boost-side gate driver 270 can generate other control signals to control the third switch (LS2) 218 ​​and the fourth switch (HS2) 220. The second buck-side gate driver 274 can generate other control signals to control the first switch (HS1) 214 and the second switch (LS1) 216.

[0031] In some implementations, the power converter may be a multi-port AC-DC power converter rather than a multi-port buck-boost power converter. In this case, a single power controller can generate a phase-shifted clock signal to control the switching of each port of the AC-DC power converter. Control signals can be generated to control two switches for each port (instead of four switches as in the case of a buck-boost power converter) to output power through the corresponding port.

[0032] Figure 3This is an example timing diagram of a reference clock signal 201, a first phase-shifted clock signal 205, a second phase-shifted clock signal 215, a first control signal 301, and a second control signal 311 according to one embodiment. The first control signal 301 may be based on a first control signal 207 and a second control signal 209 of a first buck-boost converter 200a. The first control signal 301 can control the switching of at least a first switch (HS1) 204 and a third switch (LS2) 208 to provide a first output voltage (Vout_p0) 235 of the first buck-boost converter 200a. The second control signal 311 may be based on a first control signal 217 and a second control signal 219 of a second buck-boost converter 200b. The second control signal 311 can control the switching of at least a first switch (HS1) 214 and a third switch (LS2) 218 ​​to provide a second output voltage (Vout_p1) 240 of the second buck-boost converter 200b.

[0033] The reference clock signal (Ref_clk) 201 can be a programmable clock signal that can be modified (e.g., via registers of the power controller 250) based on system and / or consumer requirements. The first phase-shifted clock signal 205 to be used for the first port (p0) and the second phase-shifted clock signal 215 to be used for the second port (p1) can be programmed (e.g., via registers of the power controller 250) to obtain the switching frequencies required by the system and / or the user for the respective ports. The first phase-shifted clock signal 205 and the second phase-shifted clock signal 215 can be phase-shifted relative to the rising edge of the reference clock signal 201 (e.g., via registers of the power controller 250). In some embodiments, the first phase-shifted clock signal 205 or the second phase-shifted clock signal 215 can be phase-shifted between 0 degrees and 180 degrees. In other embodiments, the first phase-shifted clock signal 205 or the second phase-shifted clock signal 215 can be phase-shifted between 0 degrees and 360 degrees. In some implementations, the first phase-shifted clock signal 205 can be shifted between 0 degrees and 180 degrees by a first phase, while the second phase-shifted clock signal 215 can be shifted between 0 degrees and 180 degrees by a second phase.

[0034] In some embodiments, when the power controller 250 of the power converter 200 is enabled, a low-frequency clock generator 252 can generate a reference clock signal 201, and a high-frequency clock generator 254 can generate a high-frequency clock signal 203, which are initially aligned (e.g., their rising edges are aligned in time). The high-frequency clock signal 203 can be received by both phase-controlled clock generators 266 and 276. Phase-controlled clock generators 266 and 276 can each apply different phase shifts (e.g., a first phase shift and a second phase shift, respectively) to generate a first phase-shifted clock signal 205 and a second phase-shifted clock signal 215. In some embodiments, the rising edges of the first phase-shifted clock signal 205 and the second phase-shifted clock signal 215 can occur at different points in time. This results in the first control signal 301 and the second control signal 311 being phase-shifted relative to each other. Subsequently, switches 204 and 208 (and ultimately switches 206 and 210, since the gate signal of switch 206 is generated based on the gate signal of switch 204, and similarly, the gate signal of switch 210 is generated based on the gate signal of switch 208) can be switched by waveforms that have a phase shift compared to switches 214 and 218 (and ultimately switches 216 and 220, since the gate signal of switch 216 is generated based on the gate signal of switch 214, and similarly, the gate signal of switch 220 is generated based on the gate signal of switch 218). In some embodiments, the phase shift between the first control signal 301 and the second control signal 311 makes one out of phase with respect to the other, and switches 204 and 208 switch (on / off) out of phase with switches 214 and 218. In other words, the first port provides a first output voltage 235 and the second port provides a second output voltage 240, such that the power supplied by the first port has a phase-shifted distribution compared to the power supplied by the second port. In some embodiments, when the first control signal 301 and the second control signal 311 are 180 degrees out of phase (e.g., they do not overlap), the first duration and the second duration do not overlap (e.g., they do not overlap), resulting in a non-overlapping power distribution between the two ports. In other words, the power supplied by the first port and the power supplied by the second port have a non-overlapping or non-coincident distribution. In some embodiments, the first control signal 301 and the second control signal 311 are sufficiently out of phase, such that the power supplied by the first port and the power supplied by the second port have a non-overlapping or non-coincident distribution. In other embodiments, the first control signal 301 and the second control signal 311 are partially out of phase, and the first duration and the second duration may at least partially overlap, such that the power supplied by the first port and the power supplied by the second port have a partially overlapping distribution.

[0035] The phase shift applied by phase-controlled clock generators 266 and 276 can be digitally controlled by the firmware of power controller 250 based on application and / or consumer requirements. Controlling the phase shift between the first control signal 301 and the second control signal 311 (and thus controlling i) the switching of switches 204 and 208 and ii) the switching of switches 214 and 218 can reduce the peak current of the chip and ground, as well as the EMI of the power converter 200. Because the power converter 200 includes only a single power controller 250, and both phase-shifted clock signals 205 and 215 are generated based on low-frequency clock generator 252 and high-frequency clock generator 254 and phase-shifted using phase-controlled clock generators 266 and 276, no additional components or clock source are required in power controller 250 to support the phase shift between the first and second ports.

[0036] Despite Figure 2 In this paper, the power converter 200 is described as having two ports providing two output voltages (Vout_p0 and Vout_p1), but the method described above can be applied to multi-port power converters (e.g., having three, four, five, or more ports). In this case, each port can be switched with any phase shift or a predefined phase shift (e.g., using a corresponding phase-controlled clock generator). In some embodiments, each port can be switched with different phases, such that the power provided by each port depends on the programmed phase shift having a non-overlapping, partially overlapping, or fully overlapping distribution. In other embodiments, each port can be switched such that only one port provides power at any given time. In other embodiments, each port can be switched such that a first subset of the ports provides power for a first duration, a second subset of the ports provides power for a second duration, a third subset of the ports provides power for a third duration, and so on, wherein each duration may or may not overlap with another duration. For example, in some implementations, a first subset of ports may provide power for a first duration; when the first subset of ports stops providing power, a second subset of ports may provide power for a second duration; when the second subset of ports stops providing power, a third subset of ports may provide power for a third duration, and so on. In some implementations, there may be time intervals between each subset of ports providing power (e.g., there may be periods when no port provides power).

[0037] Figure 4 This is a schematic diagram of a dual-port buck-only power converter 400 according to one embodiment. Except that the power converter 400 operates in buck-only mode, the power converter 400 can be similar to... Figure 2The power converter 200. For example, in some embodiments, the power converter 400 may be a USB-PD C type (USB-PD / C) power converter. The power converter 400 includes a power controller 450, which may be similar to, except that the power controller 450 may not include the boost-side gate driver 260 and the boost-side gate driver 270. Figure 2 The power controller 250.

[0038] The power converter 400 may include a first output port (p0) for outputting a first output voltage (Vout_p0) 435 and a second output port (p1) for outputting a second output voltage (Vout_p1) 440. The first and second output ports may share an input voltage (Vin) 430. The power converter 400 may also include a power controller 450. The power converter may include a first inductor 402 and a second inductor 412, respectively coupled to the first and second output ports. The power converter 400 may include a first switch (HS1) 404, a second switch (LS1) 406, a third switch (HS1) 414, and a fourth switch (LS1) 416. The first switch 404 and the third switch 414 are coupled to the input voltage 430.

[0039] The power controller 450 provides various controls (e.g., by sending one or more control signals, clock signals, voltages, etc.) to control the power output through the first port and the second port. The power controller 450 may include a low-frequency clock generator and a high-frequency clock generator. The power controller 450 may include a first buck-boost controller or buck controller corresponding to the first port p0, a first buck-side gate driver, and a first phase-controlled clock generator. The power controller 450 may also include a second buck-boost controller or buck controller corresponding to the second port p1, a second buck-side gate driver, and a second phase-controlled clock generator.

[0040] As per the above reference Figure 2 As described, the low-frequency clock generator can generate a low-frequency (e.g., 50 kHz, 100 kHz, etc.) clock signal to be used as a reference clock signal (Ref_clk). The high-frequency clock generator can generate a high-frequency (e.g., 24 MHz, 48 MHz, etc.) clock signal. Each of the first and second phased-array clock generators can receive the reference clock signal from the low-frequency clock generator and the high-frequency clock signal from the high-frequency clock generator. Each phased-array clock generator can introduce a separate phase delay to the corresponding high-frequency clock signal, such that the switching of the LS switch and HS switch for the first port (p0) and the second port (p1) is out of phase with respect to each other.

[0041] Figure 5This is a schematic diagram of a dual-port boost-only mode power converter 500 according to one embodiment. Except that the power converter 500 operates in boost-only mode, the power converter 500 can be similar to... Figure 2 The power converter 200. For example, in some embodiments, the power converter 500 may be a USB-PD C type (USB-PD / C) power converter. The power converter 500 includes a power controller 550, except that the power controller 550 may not include the buck-side gate driver 264 and the buck-side gate driver 274, which may be similar to Figure 2 The power controller 250.

[0042] The power converter 500 may include a first output port (p0) for outputting a first output voltage (Vout_p0) 535 and a second output port (p1) for outputting a second output voltage (Vout_p1) 540. The first and second output ports may share an input voltage (Vin) 530. The power converter 500 may also include a power controller 550. The power converter 500 may include a first inductor 502 and a second inductor 512, respectively coupled to the first and second output ports. The power converter 500 may include a first switch (LS2) 508, a second switch (HS2) 510, a third switch (LS2) 518, and a fourth switch (HS2) 520.

[0043] The power controller 550 provides various controls (e.g., by sending one or more control signals, clock signals, voltages, etc.) to control the power output through the first port and the second port. The power controller 550 may include a low-frequency clock generator and a high-frequency clock generator. The power controller 550 may include a first buck-boost controller or boost controller corresponding to the first port p0, a first boost-side gate driver, and a first phase-controlled clock generator. The power controller 550 may also include a second buck-boost controller or boost controller corresponding to the second port p1, a second boost-side gate driver, and a second phase-controlled clock generator.

[0044] As shown above (refer to the reference) Figure 2As described, the low-frequency clock generator can generate a low-frequency (e.g., 50 kHz, 100 kHz, etc.) clock signal to be used as a reference clock signal (Ref_clk). The high-frequency clock generator can generate a high-frequency (e.g., 24 MHz, 48 MHz, etc.) clock signal. Each of the first and second phased-array clock generators can receive the reference clock signal from the low-frequency clock generator and the high-frequency clock signal from the high-frequency clock generator. Each phased-array clock generator can introduce a separate phase delay to the corresponding high-frequency clock signal, such that the switching of the LS switch and HS switch for the first port (p0) and the second port (p1) is out of phase with respect to each other.

[0045] Despite Figure 2 Power converter 200 Figure 4 400 power converter and Figure 5 The power converter 500 is shown as having two ports (e.g., as a two-port power converter), but the method of using phase-shifted clock signals to control the output power at each port can be applied to multi-port power converters (e.g., power converters with three, four, five or more ports).

[0046] Figure 6 This is a flowchart of a method 600 for providing phase shift switching control of a multi-port power converter according to one embodiment. Method 600 can be executed by processing logic including hardware, firmware, or any combination thereof. Method 600 can be performed by… Figure 2 The power converter 200 performs this operation. In some embodiments, method 600 can be performed by... Figure 2 The power controller 250 performs the operation. In some embodiments, method 600 can be performed by... Figure 4 The power converter 400 performs this. In some embodiments, method 600 can be performed by... Figure 4 The power controller 450 performs this operation. In some embodiments, method 600 can be performed by... Figure 5 The power converter 500 performs this operation. In some embodiments, method 600 can be performed by... Figure 5 The power controller 550 is executed.

[0047] Return to reference Figure 6Method 600 begins with the processing logic generating a reference clock signal having a first frequency (block 602). The processing logic generates a clock signal having a second frequency (block 604). The second frequency is greater than the first frequency. The processing logic generates a first phase-shifted clock signal by shifting the clock signal by a first phase relative to the reference clock signal (block 606). The processing logic generates a second phase-shifted clock signal by shifting the clock signal by a second phase relative to the reference clock signal (block 608). The processing logic outputs power in response to a first control signal (block 610). The first control is based on the first phase-shifted clock signal. The processing logic outputs power in response to a second control signal (block 612). The second control signal is based on the second phase-shifted clock signal; and method 600 ends.

[0048] The processing logic generates a first control signal and a second control signal via a first buck-boost controller and a second buck-boost controller, respectively. In other embodiments, the processing logic receives the first control signal and controls the first high-side HS switch and the first LS switch based on the first control signal. The processing logic receives the first control signal and controls the second HS switch and the second LS switch based on the first control signal. The processing logic receives the second control signal and controls the third HS switch and the third LS switch based on the second control signal. The processing logic receives the second control signal and controls the fourth HS switch and the fourth LS switch based on the second control signal.

[0049] In some implementations, the first HS switch and the first LS switch are coupled to an input voltage source. The second HS switch and the second LS switch are coupled to a first PD port. The third HS switch and the third LS switch are coupled to an input voltage source. The fourth HS switch and the fourth LS switch are coupled to a second PD port.

[0050] In other implementations, the processing logic generates a third phase-shifted clock signal by shifting the clock signal by a third phase relative to a reference clock signal. The processing logic outputs power in response to a third control signal. The third control signal is based on the third phase-shifted clock signal.

[0051] In some embodiments, the first phase is between 0 degrees and 180 degrees, and the second phase is between 0 degrees and 180 degrees. In some embodiments, the second frequency is greater than the first frequency.

[0052] In some implementations, the power converter is a direct-to-direct-current (DC-DC) converter, such as a buck-boost converter, a boost converter, or a buck converter. In other implementations, the power converter is an AC-DC power converter, etc.

[0053] Figure 7This is a block diagram of an on-chip IC controller 2100 with a phase-controlled clock generator in at least one embodiment of a USB-PD subsystem. The IC controller 2100 is an example semiconductor device configured according to the reference clock generator and phase-controlled clock generator described herein. Figure 7 In the illustrated embodiment, IC controller 2100 is a single-chip IC controller fabricated on a semiconductor die. In another example, IC controller 2100 may be a single-chip IC fabricated as a system-on-a-chip (SoC). In other embodiments, IC controller 2100 may be a multi-chip module packaged in a single semiconductor package. Among other components, IC controller 2100 includes a central processing unit (CPU) subsystem 2102, system interconnects 2112, peripheral interconnects 2114, system resources 2116, input / output (I / O) subsystem 2118, USB-PD subsystem 2120, and various terminals (e.g., pins) configured to receive and transmit signals.

[0054] CPU subsystem 2102 includes one or more CPUs 2104, flash memory 2106, SRAM (Static Random Access Memory) 2108, and ROM (Read-Only Memory) 2110 coupled to system interconnect 2112. CPU 2104 is a suitable processor that can operate in an IC or SoC device. Flash memory 2106 is a non-volatile memory (e.g., NAND flash, NOR flash, etc.) configured to store data, programs, and / or other firmware instructions. Flash memory 2106 is tightly coupled within CPU subsystem 2102 to improve access time. SRAM 2108 is a volatile memory configured to store data and firmware instructions accessed via CPU 2104. ROM 2110 is a read-only memory (or other suitable storage medium) configured to store boot routines, configuration parameters, and other firmware parameters and settings. System interconnect 2112 is a system bus (e.g., a single-level or multi-level high-performance bus, or AHB) configured as an interface for coupling the various components of CPU subsystem 2102 to each other and as a data and control interface between the various components of CPU subsystem and peripheral interconnect 2114.

[0055] Peripheral interconnect 2114 is a peripheral bus (e.g., a single-level or multi-level AHB) that provides the primary data and control interface between CPU subsystem 2102 and peripheral devices and other resources of CPU subsystem 2102, such as system resource 2116, I / O subsystem 2118, and USB-PD subsystem 2120. Peripheral interconnect 2114 may include various controller circuitry (e.g., direct memory access or DMA controllers) that can be programmed to transfer data between peripheral blocks without burdening CPU subsystem 2102. In various embodiments, each component of the CPU subsystem and the peripheral interconnect may vary depending on the selection or type of CPU, system bus, and / or peripheral bus.

[0056] System resource 2116 includes various electronic circuits that support the operation of IC controller 2100 in its various states and modes. For example, system resource 2116 may include a power subsystem with the analog and / or digital circuitry required for each controller state / mode (e.g., sleep control circuitry, wake-up interrupt controller (WIC), power-on reset (POR), voltage and / or current reference (REF) circuitry, etc.). In some embodiments, the power subsystem may also include circuitry that enables IC controller 2100 to draw power from and / or supply power to external sources at several different voltage and / or current levels and to support the controller's operation in several power states 2117 (e.g., active state, sleep state, and deep sleep state with clock off). Furthermore, in some embodiments, extensive clock gating may be utilized to optimize CPU subsystem 2102 for low-power operation, and the CPU subsystem may include various internal controller circuitry that enables the CPU to operate in various power states 2117. For example, the CPU may include a wake-up interrupt controller configured to wake the CPU from a sleep state, thereby enabling power to be turned off when the IC chip is in a sleep state. System resource 2116 may also include a clock subsystem having analog and / or digital circuitry for clock generation and clock management, such as clock control circuitry, watchdog timer (WDT) circuitry, internal low-speed oscillator (ILO) circuitry, and internal master oscillator (IMO) circuitry. System resource 2116 may also include analog and / or digital circuitry blocks that provide reset control and support external reset (XRES).

[0057] In various implementations, the I / O subsystem 2118 may include various different types of I / O blocks and subsystems. For example, in Figure 7In the illustrated embodiment, the I / O subsystem 2118 includes a GPIO (General Purpose Input / Output) block 2118a, a TCPWM (Timer / Counter / Pulse Width Modulation) block 2118b, and an SCB (Serial Communication Block) 2118c. The GPIO 2118a includes analog and / or digital circuitry configured to implement various functions such as pull-up / pull-down, input threshold selection, input and output buffer enable / disable, and multiplexed signals connected to various I / O pins. The TCPWM 2118b includes analog and / or digital circuitry configured to implement timers, counters, pulse width modulators, decoders, and various other analog / mixed-signal elements configured to operate on input / output signals. The SCB 2118c includes analog and / or digital circuitry configured to implement various serial communication interfaces such as I2C, SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter), CAN (Controller Area Network) interface, CXPI (Clock Extended Peripheral Interface), etc.

[0058] The USB-PD subsystem 2120 provides an interface to a USB Type-C port and is configured to support USB communication and other USB functions such as power delivery and battery charging. The USB-PD subsystem 2120 includes electrostatic discharge (ESD) protection circuitry required on the Type-C port. The USB-PD subsystem 2120 also includes a Type-C transceiver and physical layer logic (PHY) configured as integrated baseband PHY circuitry to perform various digital encoding / decoding functions (e.g., Biphase Marker Code (BMC) encoding / decoding, Cyclic Redundancy Check (CRC), etc.) and analog signal processing functions involved in physical layer transmission. The USB-PD subsystem 2120 also provides termination resistors (RP and RD) and their switches as required by the USB-PD specification to perform connection detection, plug orientation detection, and power delivery roles on Type-C cables. The IC controller 2100 (and / or its USB-PD subsystem 2120) can also be configured to respond to communications defined in the USB-PD specification, such as SOP (Start of Packet), SOP', and SOP' messages. The USB-PD subsystem 2120 may also include a reference clock controller and / or a phase clock controller 2101 to generate a reference clock signal and a phase-shifted clock signal as described herein.

[0059] In other circuitry, the USB-PD subsystem 2120 may also include: one or more analog-to-digital converters (ADCs) for converting various analog signals into digital signals; a VCONN FET; an error amplifier (ERROR AMP) for controlling the power supply voltage applied to the VBUS line according to the PD contract; a high-voltage regulator (HV REG) for converting the power supply voltage to the precise voltage (e.g., 3V-5V) required by the IC controller 2100; a current sensing amplifier (CSA) and overvoltage protection (OVP) circuitry for providing overcurrent (OCP) protection, overvoltage (OV) protection, and undervoltage (UV) protection with configurable threshold and response time on the VBUS line; a pulse width modulator (PWM); one or more gate drivers (GATE DRVs) for controlling the power switches that turn the power supply on and off on the VBUS line; a low-side gate driver (LSDR) and a high-side gate driver (HSDR) for controlling the switching of the buck-boost converter; and a communication channel PHY (CC BB) for supporting communication on the Type C communication channel (CC) line. PHY logic; a charging protocol detection block (CHG DET) for detecting different types of PD chargers; and at least two on-chip discharge (VBUS DISCH) circuits that can discharge the VBUS line voltage to any voltage level in a programmable voltage range.

[0060] The various implementations of switching clock phase shifts for multiport power converters described herein can include a variety of operations. These operations can be performed and / or controlled by hardware components, digital hardware and / or firmware, and / or combinations thereof. As used herein, the term "coupled to" can mean a direct connection or an indirect connection via one or more intermediate components. Any signal provided on various on-chip buses can be time-multiplexed with other signals and can be provided on one or more common on-chip buses. Additionally, interconnections between circuit components or blocks can be shown as buses or single signal lines. Each bus in a bus can alternatively be one or more single signal lines, and each single signal line can alternatively be a bus.

[0061] Some implementations can be carried out using firmware instructions stored on a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory). These instructions can be used to program and / or configure one or more devices, including a processor (e.g., CPU) or its equivalent (e.g., processing core, processing engine, microcontroller, etc.), such that when executed by the processor or its equivalent, the instructions cause the device to perform the described operations for switching clock phase shifts of the multi-port buck-boost converter described herein. Non-transitory computer-readable storage media can include, but are not limited to, electromagnetic storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or another now-known or later-developed medium suitable for storing information.

[0062] Although the operations of the circuits and blocks shown and described herein are in a specific order, in some embodiments, the order of operations of each circuit / block may be changed, such that certain operations can be performed in reverse order, or that certain operations can be performed at least partially simultaneously and / or in parallel with other operations. In other embodiments, instructions or sub-operations of different operations may be performed in an intermittent and / or alternating manner.

[0063] In the foregoing description, the invention has been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes can be made to the invention without departing from the broader spirit and scope of the invention as set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A multi-port Universal Serial Bus Type-C Power Delivery USB-C / PD Power Converter, comprising: First USB-C / PD port; Second USB-C / PD port; as well as A power controller, coupled to the first USB-C / PD port and the second USB-C / PD port, the power controller comprising: A first phase-controlled clock generator is configured to generate a first phase-shifted clock signal by shifting a clock signal by a first phase relative to a reference clock signal, wherein the reference clock signal includes a first frequency, and the clock signal includes a second frequency greater than the first frequency; and A second phase-controlled clock generator is used to generate a second phase-shifted clock signal by shifting the clock signal by a second phase relative to the reference clock signal, wherein: The first USB-C / PD port outputs power in response to a first control signal, the first control signal being based on the first phase-shifted clock signal; and The second USB-C / PD port outputs power in response to a second control signal, which is based on the second phase-shifted clock signal.

2. The multi-port USB-C / PD power converter according to claim 1, further comprising: A reference clock generator is used to generate the reference clock signal; as well as A clock generator is used to generate the clock signal.

3. The multi-port USB-C / PD power converter according to claim 1, further comprising: A first buck-boost converter is coupled to the first USB-C / PD port and to an input voltage source; as well as A second buck-boost converter is coupled to the second USB-C / PD port and to the input voltage source, wherein the power controller further includes: A first buck-boost controller is configured to receive the first phase-shift clock signal and generate the first control signal; and The second buck-boost controller is used to receive the second phase-shift clock signal and generate the second control signal.

4. The multi-port USB-C / PD power converter according to claim 1, further comprising: A first high-side HS switch and a first low-side LS switch are coupled to the input voltage source; A second HS switch and a second LS switch are coupled to the first USB-C / PD port; The third HS switch and the third LS switch are coupled to the input voltage source; as well as The fourth HS switch and the fourth LS switch are coupled to the second USB-C / PD port.

5. The multi-port USB-C / PD power converter according to claim 4, wherein, The power controller also includes: A first buck-boost controller is configured to receive the first phase-shift clock signal and generate the first control signal; A first buck-side gate driver is configured to receive the first control signal and control the first HS switch and the first LS switch. A first boost-side gate driver is configured to receive the first control signal and control the second HS switch and the second LS switch; The second buck-boost controller is used to receive the second phase-shift clock signal and generate the second control signal; A second buck-side gate driver is configured to receive the second control signal and control the third HS switch and the third LS switch; and The second boost-side gate driver is used to receive the second control signal and control the fourth HS switch and the fourth LS switch.

6. The multi-port USB-C / PD power converter according to claim 1, further comprising: Coupled to a third USB-C / PD port of the power controller, wherein the power controller further includes a third phase-controlled clock generator for generating a third phase-shifted clock signal by shifting the clock signal by a third phase relative to the reference clock signal, wherein: The third USB-C / PD port outputs power in response to a third control signal, which is based on the third phase-shift clock signal.

7. The multi-port USB-C / PD power converter according to claim 1, wherein, The first phase is between 0 degrees and 180 degrees, and the second phase is between 0 degrees and 180 degrees.

8. The multi-port USB-C / PD power converter according to claim 1, wherein, The first control signal and the second control signal do not overlap.

9. The multi-port USB-C / PD power converter according to claim 1, wherein, The multi-port USB-C / PD power converter is a buck-boost converter.

10. The multi-port USB-C / PD power converter according to claim 1, wherein, The multi-port USB-C / PD power converter is one of a buck converter, a boost converter, or an AC-DC converter.

11. A method for a Universal Serial Bus Type-C Power Delivery USB-C / PD controller, the method comprising: A first phase-shifted clock signal is generated by a first phase-controlled clock generator in the USB-C / PD controller by shifting a clock signal by a first phase relative to a reference clock signal, wherein the reference clock signal includes a first frequency and the clock signal includes a second frequency greater than the first frequency; The second phase-shifted clock signal is generated by the second phase-controlled clock generator in the USB-C / PD controller by shifting the clock signal by a second phase relative to the reference clock signal; In response to a first control signal, power is output through the first USB-C / PD port, wherein the first control signal is based on the first phase-shifted clock signal; and Power is output through the second USB-C / PD port in response to a second control signal, the second control signal being based on the second phase-shift clock signal.

12. The method of claim 11, further comprising: The reference clock signal is generated by the reference clock generator; as well as The clock signal is generated by a clock generator.

13. The method of claim 11, further comprising: The first phase-shift clock signal is received by the first buck-boost controller; The first control signal is generated by the first buck-boost controller; The second phase-shift clock signal is received by the second buck-boost controller; and The second control signal is generated by the second buck-boost controller.

14. The method of claim 13, further comprising: The first control signal is received by the first buck-side gate driver, and the first high-side HS switch and the first low-side LS switch are controlled based on the first control signal. The first control signal is received by the first boost-side gate driver, and the second HS switch and the second LS switch are controlled based on the first control signal. The second control signal is received by the second buck-side gate driver, and the third HS switch and the third LS switch are controlled based on the second control signal; as well as The second control signal is received by the second boost-side gate driver, and the fourth HS switch and the fourth LS switch are controlled based on the second control signal.

15. The method according to claim 14, wherein: The first HS switch and the first LS switch are coupled to the input voltage source; The second HS switch and the second LS switch are coupled to the first USB-C / PD port; The third HS switch and the third LS switch are coupled to the input voltage source; as well as The fourth HS switch and the fourth LS switch are coupled to the second USB-C / PD port.

16. The method of claim 11, further comprising: The third phase-shifted clock signal is generated by the third phase-controlled clock generator in the USB-C / PD controller by shifting the clock signal by a third phase relative to the reference clock signal; as well as Power is output through a third USB-C / PD port in response to a third control signal, the third control signal being based on the third phase-shift clock signal.

17. The method according to claim 11, wherein, The first phase is between 0 degrees and 180 degrees, and the second phase is between 0 degrees and 180 degrees.

18. An integrated circuit IC Universal Serial Bus Type-C Power Delivery USB-C / PD controller, comprising: The first terminal to be coupled to the first USB-C / PD port; The second terminal is to be coupled to the second USB-C / PD port; A reference clock generator is used to generate a reference clock signal with a first frequency; A clock generator for generating a clock signal having a second frequency, wherein the second frequency is greater than the first frequency; A first phase-controlled clock generator is used to generate a first phase-shifted clock signal by shifting the clock signal by a first phase relative to the reference clock signal; as well as A second phase-controlled clock generator is used to generate a second phase-shifted clock signal by shifting the clock signal by a second phase relative to the reference clock signal.

19. The IC USB-C / PD controller according to claim 18, wherein: The first USB-C / PD port outputs power in response to a first control signal, the first control signal being based on the first phase-shifted clock signal; as well as The second USB-C / PD port outputs power in response to a second control signal, which is based on the second phase-shifted clock signal.

20. The IC USB-C / PD controller according to claim 18, further comprising: A first buck-boost controller is configured to receive the first phase-shift clock signal and generate a first control signal; A first buck-side gate driver is configured to receive the first control signal and control the first high-side HS switch and the first low-side LS switch, wherein the first HS switch and the first LS switch are coupled to the input voltage source. A first boost-side gate driver is configured to receive the first control signal and control the second HS switch and the second LS switch, wherein the second HS switch and the second LS switch are coupled to the first USB-C / PD port. The second buck-boost controller is used to receive the second phase-shift clock signal and generate the second control signal; A second buck-side gate driver is configured to receive the second control signal and control the third HS switch and the third LS switch, wherein the third HS switch and the third LS switch are coupled to the input voltage source; as well as A second boost-side gate driver is configured to receive the second control signal and control the fourth HS switch and the fourth LS switch, which are coupled to the second USB-C / PD port.

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