Error signaling window for phase-difference protocol

Abstract

Systems, methods, and apparatuses for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase difference resolution decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received on the serial bus, each symbol representing a signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in the signaling state of two lines of the serial bus, the indicator of the error signaling window corresponding to a forbidden symbol combination or a delay in control signaling, and to signal an error during the error signaling window via the bus interface when the error is detected in the timing of the indicator of the error signaling window or in the sequence of symbols.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to pending non-provisional application serial number 17 / 027,541, filed with the U.S. Patent and Trademark Office on September 21, 2020, the contents of which are fully set forth herein and incorporated herein in their entirety and for all applicable purposes. Technical Field

[0003] This disclosure generally relates to a serial bus interface between processing circuitry and peripheral devices, and more specifically to detecting and reporting errors in a sequence of symbols transmitted via a serial bus or in data decoded from a sequence of symbols. Background Technology

[0004] Mobile communication devices may include various components, including circuit boards, integrated circuit (IC) devices, and / or system-on-a-chip (SoC) devices. These components may include processing devices, user interface components, storage devices, and other peripheral components that communicate via a shared data communication bus, which may include a multi-point serial bus or a parallel bus. Commonly known serial interfaces in the industry include internal integrated circuits (I2C or I2C). 2 C) Serial interfaces and their derivatives and alternatives.

[0005] The Mobile Industrial Processor Interface (MIPI) Alliance defines standards for Improved Integrated Circuit (I3C) serial interfaces, Radio Frequency Front-End (RFFE) interfaces, System Power Management Interfaces (SPMIs), and other interfaces. These interfaces can be used to connect processors, sensors, and other peripheral devices. In some interfaces, multiple bus masters are coupled to a serial bus, allowing two or more devices to act as bus masters for different types of messages transmitted on the serial bus. The SPMI protocol defines the hardware interface that can be implemented between the baseband or application processor and peripheral components. In some cases, the SPMI protocol is implemented to support power management operations within the device.

[0006] The standard I3C protocol is typically used to control half-duplex operation on a serial bus. The need for higher throughput can be met by using higher clock rates or other encoding schemes. In many conventional systems, error reporting on a half-duplex serial bus can lead to data rate conflicts with certain encoding schemes that transmit data in coded blocks or signaling sequences. Summary of the Invention

[0007] Certain aspects of this disclosure relate to systems, apparatuses, methods, and techniques for providing predefined patterns within a data stream, which can be explicitly identified by a receiving device, and for improving the integrity of high-speed communication interfaces, including interfaces involving phase differential coding.

[0008] In various aspects of this disclosure, a method for receiving data at a device coupled to a serial bus includes receiving a sequence of symbols, each symbol representing a signaling state of the serial bus; decoding data based on transitions between symbol pairs in the symbol sequence; detecting an indicator of an error signaling window in the signaling state of two lines of the serial bus, the indicator of the error signaling window corresponding to a prohibited symbol combination or a delay in control signaling; and signaling an error during the error signaling window period when an error is detected in the timing of the indicator of the error signaling window or in the symbol sequence.

[0009] In various aspects of this disclosure, an apparatus includes: a bus interface configured to couple the apparatus to a serial bus; a phase differential decoder configured to decode data based on transitions between symbol pairs in a symbol sequence received from the serial bus, each symbol representing a signaling state of the serial bus; and a processor configured to: detect an indicator of an error signaling window in the signaling state of two lines of the serial bus, the indicator of the error signaling window corresponding to a prohibited symbol combination or a delay in control signaling; and signal an error via the bus interface during the error signaling window period when an error is detected in the timing of the indicator of the error signaling window or in the symbol sequence.

[0010] In various aspects of this disclosure, a computer-readable medium stores code, instructions, and / or data, including code that, when executed by a processor, causes the processor to: receive a sequence of symbols, each symbol representing a signaling state of a serial bus; decode data based on transitions between symbol pairs in the symbol sequence; detect indicators of an error signaling window in the signaling state of two lines of the serial bus, the indicators of the error signaling window corresponding to a prohibited symbol combination or a delay in control signaling; and signal an error during an error signaling window when an error is detected in the timing of the indicator of the error signaling window or in the symbol sequence.

[0011] In various aspects of this disclosure, an apparatus includes: means for receiving a sequence of symbols, each symbol representing a signaling state of a serial bus; means for decoding data based on transitions between symbol pairs in the symbol sequence; means for detecting an indicator of an error signaling window in the signaling state of two lines of the serial bus, the indicator of the error signaling window corresponding to a prohibited symbol combination or a delay in control signaling; and means for signaling an error during an error signaling window when an error is detected in the timing of the indicator of the error signaling window or in the symbol sequence.

[0012] In various aspects of this disclosure, a method for transmitting data from a device coupled to a serial bus includes encoding data with transitions between symbol pairs in a symbol sequence, each symbol defining a signaling state of the serial bus; transmitting the symbol sequence via the serial bus; transmitting an indicator of an error signaling window in the signaling state of two lines of the serial bus, the indicator of the error signaling window corresponding to a prohibited symbol combination or a delay in control signaling; receiving, within the error signaling window, a signaling indicating an error in the symbol sequence or an error in the timing of the indicator of the error signaling window; and terminating data transmission when an error signaling indicating an error is received in the error signaling window.

[0013] In various aspects of this disclosure, an apparatus includes: a bus interface configured to couple the apparatus to a serial bus; a phase differential encoder configured to encode data with transitions between symbol pairs in a symbol sequence, each symbol defining a signaling state of the serial bus; and a processor configured to: transmit an indicator of an error signaling window in the signaling state of the two lines of the serial bus, the indicator of the error signaling window corresponding to a prohibited symbol combination or a delay in control signaling; receive, within the error signaling window, a signaling indicating an error in the symbol sequence or an error in the timing of the indicator of the error signaling window; and terminate data transmission when an error signaling indication is received in the error signaling window.

[0014] In various aspects of this disclosure, a computer-readable medium stores code, instructions, and / or data, including code that, when executed by a processor, causes the processor to: encode data as transitions between symbol pairs in a symbol sequence, each symbol defining a signaling state of a serial bus; transmit the symbol sequence via the serial bus; transmit indicators of error signaling windows in the signaling states of the two lines of the serial bus, the indicators of the error signaling windows corresponding to prohibited symbol combinations or delays in control signaling; receive, within the error signaling window, signaling indicating an error in the symbol sequence or an error in the timing of the indicator of the error signaling window; and terminate data transmission when an error signaling indication is received in the error signaling window.

[0015] In various aspects of this disclosure, an apparatus for managing transactions executed on a serial bus includes: components for encoding data with transitions between symbol pairs in a symbol sequence, each symbol defining a signaling state of the serial bus; components for transmitting the symbol sequence via the serial bus; components for transmitting indicators of error signaling windows in the signaling states of the two lines of the serial bus, the indicators of the error signaling windows corresponding to prohibited symbol combinations or delays in control signaling; components for receiving, within the error signaling window, signaling indicating an error in the symbol sequence or an error in the timing of the indicator of the error signaling window; and components for terminating data transmission when an error signaling indication is received within the error signaling window. Attached Figure Description

[0016] Figure 1 An apparatus is shown that employs a data link between IC devices, which operates selectively according to one of several available standards.

[0017] Figure 2 A communication interface is shown in which multiple devices are connected using a serial bus.

[0018] Figure 3 Some aspects of a device comprising multiple devices connected to a serial bus are shown.

[0019] Figure 4 The timing associated with the command word sent to the slave device according to the I2C protocol is shown.

[0020] Figure 5 An example of signaling on a serial bus is shown when the serial bus is operating in an operating mode defined by the I3C specification.

[0021] Figure 6 An example of frame transmission in I3C single data rate mode is shown.

[0022] Figure 7 An example of frame transmission in I3C high data rate mode is shown, where data is transmitted at double data rate (DDR).

[0023] Figure 8 Transmissions are shown via a multi-line serial bus configured according to certain aspects disclosed herein.

[0024] Figure 9 A first example of an encoding scheme for transcoding data, based on certain aspects disclosed herein, is shown.

[0025] Figure 10 A second example of an encoding scheme for transcoding data, based on certain aspects disclosed herein, is shown.

[0026] Figure 11 The signaling status of a high data rate protocol (such as the I3C protocol) during symbol transmission is shown according to certain aspects disclosed herein.

[0027] Figure 12 A first example of signaling adaptation for providing an error signaling window is shown, based on some aspects disclosed herein.

[0028] Figures 13-16 The use of the error signaling window, provided in accordance with certain aspects disclosed herein, is illustrated.

[0029] Figure 17 A second example of signaling adaptation for providing an error signaling window is shown, based on some aspects disclosed herein.

[0030] Figures 18-21 The use of the error signaling window, provided in accordance with certain aspects disclosed herein, is illustrated.

[0031] Figure 22 This is a block diagram illustrating a device employing processing circuitry that can be adapted to certain aspects disclosed herein.

[0032] Figure 23 This illustrates certain aspects of a method for receiving data at a device coupled to a serial bus, based on certain aspects disclosed herein.

[0033] Figure 24 A hardware implementation of an apparatus that operates as a receiving device according to certain aspects disclosed herein is shown.

[0034] Figure 25 This illustrates certain aspects of a method for transferring data from a device coupled to a serial bus, based on certain aspects disclosed herein.

[0035] Figure 26 A hardware implementation of an apparatus that operates as a transmission device according to certain aspects disclosed herein is shown. Detailed Implementation

[0036] The detailed description given below, in conjunction with the accompanying drawings, is intended to describe various configurations and not to represent the only configuration in which the concepts described herein can be practiced. The detailed description includes specific details used to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0037] Several aspects and features will now be introduced with reference to various apparatuses and methods. These apparatuses and methods will be described in detail below and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, “elements”). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system.

[0038] Overview

[0039] Devices, including application-specific integrated circuits (ASICs), system-on-a-chip (SoCs), and / or other IC devices, typically employ a shared communication interface. This interface may include a serial bus or other data communication links for connecting the processor to modems and other peripheral devices. Serial buses can operate according to specifications and protocols defined by standards bodies. In some embodiments disclosed herein, the serial bus operates according to protocols such as I2C and / or I3C, which define timing relationships between signals transmitted over the serial bus. Certain aspects disclosed herein relate to systems, apparatuses, methods, and techniques for providing a slave device with the opportunity to report parity errors before a transaction has been fully transmitted.

[0040] Some aspects of this disclosure relate to devices for transmitting and receiving phase differential coded signals via a serial bus. In one example, a receiving device may receive a sequence of symbols, each symbol representing a signaling state of the serial bus, decode data according to transitions between symbol pairs in the symbol sequence, detect indicators of error signaling windows in the signaling states of two lines of the serial bus, the indicators of the error signaling windows corresponding to prohibited symbol combinations or delays in control signaling, and signal errors during the error signaling window period when an error is detected in the timing of the error signaling window indicator or in the symbol sequence.

[0041] Example of a device with a serial data link

[0042] According to certain aspects of this disclosure, serial data links may be employed to interconnect electronic devices, which are subcomponents of devices such as: cellular phones, smartphones, Session Initiation Protocol (SIP) phones, laptops, notebook computers, netbooks, smartbooks, personal digital assistants (PDAs), satellite radios, Global Positioning System (GPS) devices, smart home devices, smart lighting, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, entertainment devices, vehicle components, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), electrical appliances, sensors, security devices, vending machines, smart meters, drones, multirotors, or any other similar functional devices.

[0043] Figure 1 An example of a device 100 employing a data communication bus is shown. Device 100 may include processing circuitry 102 having multiple circuits and / or devices 104, 106, and / or 108, which may be implemented, for example, in one or more ASICs or SoCs. In one example, device 100 may be a communication device, and processing circuitry 102 may include processing devices disposed in ASIC 104, one or more peripheral devices 106, and transceiver 108, enabling the device to communicate with a radio access network, a core access network, the Internet, and / or another network via antenna 124.

[0044] ASIC 104 may have one or more processors 112, one or more modems 110, on-board memory 114, bus interface circuitry 116, and / or other logic circuitry or functions. Processing circuitry 102 may be controlled by an operating system that provides an application programming interface (API) layer enabling one or more processors 112 to execute software modules residing in on-board memory 114 or in other processor-readable storage devices 122 disposed on processing circuitry 102. Software modules may include instructions and data stored in on-board memory 114 or processor-readable storage devices 122. ASIC 104 may access its on-board memory 114, processor-readable storage devices 122, and / or storage devices external to processing circuitry 102. On-board memory 114 and processor-readable storage devices 122 may include non-transitory media such as read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM (EEPROM), flash memory cards, or other types of memory devices that can be used in processing systems and computing platforms. Processing circuitry 102 may include, implement, or access a local database or other parameter storage device that can maintain operating parameters and other information for configuring and operating device 100 and / or processing circuitry 102. The local database may be implemented using registers, a database module, flash memory, magnetic media, EEPROM, floppy disk, or hard disk, etc. Processing circuitry 102 may also be operatively coupled to external devices, such as antenna 124, display 126, operator control, and other components. Operator control may include switches or buttons 128, 130 and / or an integrated or external keypad 132. The user interface module may be configured to operate display 126, external keypad 132, etc., via a dedicated communication link or via one or more serial data interconnects.

[0045] Processing circuitry 102 may provide one or more buses 118a, 118b, 120 that enable communication between certain devices 104, 106, and / or 108. In one example, ASIC 104 may include bus interface circuitry 116, which includes a combination of circuitry, counters, timers, control logic, and other configurable circuitry or modules. In some cases, bus interface circuitry 116 may be configured to operate according to a standard-defined communication specification or protocol. Processing circuitry 102 may include or control power management functions that configure and manage the operation of device 100.

[0046] Figure 2A communication link 200 is illustrated, in which multiple devices 204, 206, 208, 210, 212, 214, and 216 are connected using a serial bus 202. In one example, devices 204, 206, 208, 210, 212, 214, and 216 may be adapted or configured to communicate via the serial bus 202 according to the I3C protocol. In some cases, one or more of devices 204, 206, 208, 210, 212, 214, and 216 may alternatively or additionally use other protocols to communicate, such as including the I2C protocol.

[0047] Communication via serial bus 202 can be controlled by master device 204. In one operating mode, master device 204 can be configured to provide a clock signal that controls the timing of data signals. In another operating mode, two or more of devices 204, 206, 208, 210, 212, 214, and 216 can be configured to exchange data encoded with symbols defining the signaling states of clock and data signals, wherein timing information is embedded in the transmission of the symbols.

[0048] Figure 3 Multiple devices 302 and 3220-322 coupled to serial bus 320 are shown. N Certain aspects of device 300. Devices 302 and 3220-322 N It can be disposed in one or more semiconductor IC devices (such as application processors, SoCs, or ASICs). In various implementations, devices 302 and 3220-322... N It may include, support, or operate as: modems, signal processing devices, display drivers, cameras, user interfaces, sensors, sensor controllers, media players, transceivers, and / or other such components or devices. In some examples, from devices 3220-322 N One or more slave devices can be used to control, manage, or monitor sensor devices. Devices 302 and 3220-322 N Communication between them via serial bus 320 is controlled by bus master device 302. Some types of buses can support multiple bus masters 302.

[0049] In one embodiment, the bus master device 302 includes an interface controller 304, which manages access to the serial bus and provides interfaces for slave devices 3220-322. NConfigure a dynamic address and / or generate a clock signal 328 to be transmitted on clock line 318 of the serial bus 320. The bus master device 302 may include a configuration register 306 or other storage device 324, and / or control logic 312 configured to process protocols or advanced functions. Control logic 312 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. The bus master device 302 includes a transceiver 310 and line drivers / receivers 314a and 314b. The transceiver 310 may include a receiver, a transmitter, and common circuitry, wherein the common circuitry may include timing circuitry, logic circuitry, and / or storage devices. In one example, the transmitter encodes and transmits data based on timing in the clock signal 328 provided by clock generation circuitry 308. Additional timing clock signals 326 may be provided for use by control logic 312 and other functions, circuitry, or modules.

[0050] At least one device 3220-322 N It can be configured to operate as a slave device on a serial bus 320 and may include circuitry and modules that support and communicate with a display, image sensor, and / or one or more sensors for controlling and measuring environmental conditions. In one example, a slave device 3220 configured to operate as a slave device may provide control functions, modules, or circuitry 332, which includes circuitry and modules for supporting and communicating with a display, image sensor, and / or one or more sensors for controlling and measuring environmental conditions. Slave device 3220 may include a configuration register 334 or other storage device 336, control logic 342, transceiver 340, and line drivers / receivers 344a and 344b. Control logic 342 may include processing circuitry, such as a state machine, sequencer, signal processor, or general-purpose processor. Transceiver 310 may include a receiver, transmitter, and common circuitry, wherein the common circuitry may include timing, logic circuitry, and / or storage devices. In one example, the transmitter encodes and transmits data based on timing in a clock signal 348 provided by clock generation and / or recovery circuitry 346. Clock signal 348 can be derived from a signal received from clock line 318. Other timing clock signals 338 can be provided for use by control logic 342 and other functions, circuits, or modules.

[0051] The serial bus 320 can operate according to I2C, I3C, RFFE, SPMI, or other protocols. At least one device 302, 3220-322 N It can be configured to operate as both a master and slave device on the serial bus 320. Two or more devices 302, 3220-322N It can be configured to operate as a master device on the serial bus 320.

[0052] In one example, the serial bus 320 can operate according to the I3C protocol. Devices communicating using the I3C protocol can coexist on the same serial bus 320 with devices communicating using the I2C protocol. The I3C protocol can support different communication modes, including a Single Data Rate (SDR) mode compatible with the I2C protocol. High Data Rate (HDR) mode can provide data transfer rates between 6 megabits per second (Mbps) and 16 Mbps, and some HDR modes can provide even higher data transfer rates. The I2C protocol can conform to the de facto I2C standard to provide data rates between 100 kilobits per second (kbps) and 3.2 Mbps. In addition to data format and bus control aspects, the I2C and I3C protocols can also define the electrical and timing aspects of signals transmitted on the two-wire serial bus 320. In some aspects, the I2C and I3C protocols can define the DC characteristics affecting certain signal levels associated with the serial bus 320 and / or the AC characteristics affecting certain timing aspects of signals transmitted on the serial bus 320. In some examples, the two-wire serial bus 320 transmits data on data line 316 and clock signals on clock line 318. In some cases, the data may be encoded in signaling states or in the transition of signaling states between data line 316 and clock line 318.

[0053] In some implementations, pull-up / pull-down circuit 350 may be coupled to data line 316 and / or clock line 318 to maintain the signaling state of serial bus 320 when no device actively drives the associated line, including during line turnaround (when the first device stops driving the line and before the second device begins actively driving the line). Pull-up / pull-down circuit 350 can be implemented using various circuits. In the illustrated example, pull-up / pull-down circuit 350 includes resistor 354, which can be coupled to a voltage source via switch 352. In one example, the voltage source can provide a voltage corresponding to one of the two binary signaling states defined for serial bus 320. In some cases, switch 352 may be implemented as a suitably configured transistor. In some cases, pull-up / pull-down circuit 350 is directly coupled to a voltage source, and switch 352 couples pull-up / pull-down circuit 350 to data line 316 or clock line 318.

[0054] In some implementations, the keeper circuit 360 can be configured as a positive feedback circuit that drives data line 316 and / or clock line 318 through a high-impedance output and receives feedback from data line 316 and / or clock line 318 through a low-impedance input. The keeper circuit 360 can be configured to maintain the last asserted signaling state on the line. The output of the keeper circuit 360 can be easily controlled by the master device 302 or slave devices 3220-322. N The line driver in the process is overcome.

[0055] Data transmission via serial bus

[0056] The examples illustrate data transmission using the I2C and I3C protocols to control signaling, command, and payload transfers. However, some concepts disclosed herein apply to other bus configurations and protocols, including RFFE and SPMI configurations and protocols. In one example, data can be transmitted according to the I3C HDR protocol, where data is encoded in ternary notation (HDR-TSP), and HDR-TSP slots can be defined according to HDR-TSP words, where each slot can be represented as a set of six consecutively recovered clock pulses, which is the equivalent number of clock pulses used for an HDR-TSP word. In another example, data can be transmitted according to the I3C HDR Double Data Rate (HDR-DDR) protocol, where slots can be defined according to HDR-DDR words and / or represented as the number of clock pulses used to transmit HDR-DDR words.

[0057] Figure 4 An example of timing 400 associated with an address word sent to a slave device according to certain I2C and / or I3C protocols is shown. In this example, the master initiates a transaction with start condition 406, whereby SDA line 402 is driven from high to low while SCL line remains high. The master then transmits a clock signal on SCL line 404. The slave device's seven-bit address 410 is then transmitted on SDA line 402. Following the seven-bit address 410 is a write / read command bit 412, which indicates "write" when low and "read" when high. The slave device can respond with ACK by driving SDA line 402 low within the next clock interval 414. If the slave device does not respond, SDA line 402 is pulled high, and the master treats the lack of response as NACK. The master can terminate the transaction with stop condition 408 by driving SDA line 402 from low to high while SCL line 404 is high. This transaction can be used to determine whether a slave device coupled to the serial bus with the transmitted address is active.

[0058] Figure 5The diagram illustrates signaling 500 on the serial bus when it operates in Single Data Rate (SDR) mode as defined by the I3C specification. Data transmitted on the first line of the serial bus (which may be referred to as data line 502, SDA, or SDATA) can be captured using a clock signal transmitted on the second line of the serial bus (which may be referred to as clock line 504, SCL, or SCLOCK). During data transmission, when clock line 504 is at a high voltage level, the signaling state 512 of data line 502 is expected to remain constant for the duration of pulse 514. When clock line 504 is at a high voltage level, transitions on data line 502 indicate a start condition 506, a stop condition 508, or a repeated start condition 510.

[0059] On the I3C serial bus, a start condition 506 is defined to allow the current bus master to signal that data is about to be transmitted. Start condition 506 occurs when data line 502 transitions from high to low while clock line 504 is high. The bus master can use stop condition 508 to signal the completion and / or termination of a transmission. Stop condition 508 is indicated when data line 502 transitions from low to high while clock line 504 is high. Repeat start 510 can be transmitted by a bus master that wishes to initiate a second transmission upon completion of the first transmission. Repeat start 510 is transmitted instead of stop condition 508, and repeat start 510 has the significance of following start condition 506 immediately after stop condition 508. Repeat start 510 occurs when data line 502 transitions from high to low while clock line 504 is high.

[0060] The bus master device may transmit an initiator 522 before transmitting slave device addresses, commands and / or data. The initiator 522 may be a start condition 506 or a repeat start 510. Figure 5 The diagram illustrates a command code transfer 520 performed by the bus master. During the transfer, a predefined address header 524 and command code 526 may follow the initiator 522. For example, command code 526 may cause the serial bus to switch to the desired operating mode. In some cases, data 528 may be transferred. The command code transfer 520 may be followed by a terminator 530, which may be a stop condition 508 or a restart 510.

[0061] Some serial bus interfaces support signaling schemes that provide higher data rates. In one example, the I3C specification defines several HDR modes, including HDR-DDR mode, in which data is transmitted on both the rising and falling edges of the clock signal.

[0062] The I3C bus can switch between SDR mode and DDR mode. Figure 5 Examples include signaling 540 transmitted on data line 502 and clock line 504 to initiate certain mode changes. Signaling 540 is defined by the I3C protocol for initiating restarts, exits, and / or interrupts from I3C HDR communication modes. Signaling 540 includes HDR Exit 542, which can be used to interrupt or exit HDR. HDR Exit 542 begins with a falling edge 544 on clock line 504 and ends with a rising edge 546 on clock line 504. When clock line 504 is in a low signaling state, four pulses are transmitted on data line 502. When no pulses are provided on clock line 504, the I2C device ignores data line 502.

[0063] Figure 6 and Figure 7 Includes timing diagrams illustrating frames 600 and 700 transmitted on the serial bus when a bus master reads from a slave device. The serial bus has clock lines (SCL602, 702) and data lines (SDA604, 704). Clock signals 620 and 720 transmitted on SCL602 and 702 provide timing information usable when the serial bus operates in I3C Single Data Rate (SDR) mode and I3C HDR-DDR mode. The clock signals consist of pulses 622, 628, 722, and 728 defined by rising edges 624 and 724 and falling edges 626 and 726. The bus master transmits clock signals on SCL602 and 702 regardless of the direction of the data flow through the serial bus.

[0064] Figure 6 Frame 600 is shown being transmitted on a serial bus operating in I3C SDR mode. In each frame 600, a single byte of data 606 is transmitted. The data signal transmitted on SDA 604 is expected to be stable during the duration of the high state of pulse 628 in clock signal 620, and in one example, the state of SDA 604 is sampled on the falling edge of clock pulse 628. Each byte of data 606 is followed by bit 608, which can be used as a parity bit or a transition bit (T bit).

[0065] Figure 7Frame 700 is shown being transmitted when the serial bus is operating in HDR-DDR mode. In HDR-DDR mode, data is transmitted on both the rising edge 724 and the falling edge 726 of pulse 722 in clock signal 720. The receiver samples or captures one bit of data on SDA 704 at each edge of pulse 728 in clock signal 720. In HDR-DDR mode, a 2-byte data word 708 is transmitted in each frame 700. Data word 708 typically includes 16 payload bits, which are organized into two 8-bit bytes 714 and 716, and data word 708 is preceded by a two-bit preamble 706 and followed by two parity bits 712. The 20 bits in frame 700 can be transmitted on the edges of 10 clock pulses. Transmission integrity is protected by the transmission of parity bits 712.

[0066] The flexibility, bus management features, and energy efficiency of the MIPI I3C interface have elevated the I3C protocol to a preferred state for serial interfaces. A standard I3C interface can provide effective data throughput of up to 100 Mbps. The I3C interface is used in a wide variety of applications. Some applications have an increasing need for higher data transfer rates and reduced latency. Higher data throughput can certainly be achieved by increasing the bus clock rate. Increasing the bus clock rate may render slower switching drivers unusable in some conventional devices and may jeopardize timing shutdown conditions in newer receivers. In one example, the timing shutdown condition is met when the receiver is able to sample the data signal within a stable and valid time window. Some systems use multichannel configurations that maintain a base clock rate of 12.5 MHz to ensure that the timing shutdown condition is met at the receiver and to maintain compatibility with older, slower devices. These multichannel configurations achieve higher data throughput through the use of additional physical channels and multichannel (ML) protocols.

[0067] Additional physical channels can be set up in a serial bus to couple two or more devices and can be used as additional data channels to increase data throughput, provide error detection protection features, improve signal integrity, extend the physical range of the serial bus, and / or for other purposes. Additional channels can be configured to enable efficient encoding of data to be transmitted over the serial bus. The I3C standard supports several High Data Rate (HDR) protocols, including DDR mode and Phase Differential Signaling mode. Phase Differential Signaling mode encodes data in the form of symbols that control the signaling states of multiple lines on the serial bus. Phase Differential Signaling offers several advantages over clock-line based protocols. For example, Phase Differential Signaling can minimize the number of transitions on a serial bus channel, and using a common driver for data can improve signal integrity and support increased bus reachability. The standard I3C specification provides Ternary Symbol Traditional Mode (HDR-TSL) for use on a serial bus coupled with traditional I2C devices, and Pure Bus Mode Ternary Symbols (HDR-TSP) for use on a serial bus coupled only with I3C devices.

[0068] Figure 8 Three examples 800, 820, and 840 of transmission via a multi-wire serial bus are illustrated. The first example 800 relates to a serial bus with two primary lines (SCL 802 and SDA 804) and three secondary lines 806, 808, and 810. This serial bus can operate according to I3C HDR-TSP or HDR-TSL modes, in which data is encoded with 5-bit symbols and transmitted using phase differential signaling. The second example 820 relates to a serial bus with two primary lines (SCL 822 and SDA 824) and a secondary line 826. This serial bus can operate according to I3C HDR-TSP or HDR-TSL modes, in which data is encoded with 3-bit symbols and transmitted using phase differential signaling. The third example 840 relates to a serial bus with two primary lines (SCL 842 and SDA 844) and no secondary lines. The serial bus can operate in either I3C HDR-TSP or HDR-TSL mode, in which data is encoded with 2-bit symbols and transmitted using phase differential signaling.

[0069] Based on certain aspects disclosed herein, other combinations of lines and encoding can be provided. In HDR-DDR mode, a command for selecting HDR-TSP or HDR-TSL mode can be transmitted. In some cases, this command can carry additional parameters defining the operating mode of the serial bus. The operating mode can define the number of symbols transmitted in a frame, the number of lines used for transmitting symbols, the operating type or mode of the driver and / or receiver coupled to the serial bus, the encoding scheme or mapping, the digital base used to represent the number of transitions, and / or other characteristics or parameters. The number of symbols transmitted per frame or per symbol sequence can be selected to provide an expected coding rate representing the number of data bits per frame, an expected coding efficiency (which can be expressed as the ratio of the number of bits encoded per frame to the maximum number of bits that can be encoded per frame), and / or to obtain a satisfactory trade-off between coding rate and coding efficiency.

[0070] Figure 9 A first example of encoding scheme 900 is shown, which can be used by a ternary-to-symbol encoder to generate a sequence of symbols with an embedded clock for transmission on serial bus 320. Encoding scheme 900 can also be used by a symbol-to-ternary decoder to extract the number of ternary transitions from symbols received from serial bus 3230. In this encoding scheme 900, the two lines of serial bus 320 allow the definition of four basic symbols 930, 932, 934, 936 (S:{0,1,2,3}). Any two consecutive symbols in the symbol sequence have different states, and the symbol sequence 0,0, 1,1, 2,2, and 3,3 is an invalid combination of consecutive symbols. Therefore, only three valid symbol transitions are available at each symbol boundary, where the symbol boundary is determined by the transmission clock and represents the point where the first symbol (previous symbol Ps) 922 terminates and the second symbol (current symbol Cs) 924 begins.

[0071] According to certain aspects disclosed herein, for each Ps symbol 922, three available transitions are assigned a transition number digit (T) 926. The value of T 926 can be represented in ternary form. In one example, the value of the transition number digit 926 can be determined by assigning a symbol sorting circle 902 to the encoding scheme. The symbol sorting circle 902 assigns a rotation direction 906 between positions 904a-904d and positions 904a-906d on the symbol sorting circle 902 for the four possible symbols. In the example shown, the rotation direction 906 is clockwise. The transition number digit 926 can represent the interval between the valid current symbol 924 and the immediately preceding symbol 922. This interval can be defined as the number of steps along the rotation direction 906 on the symbol sorting circle 902 required to reach the current symbol Cs 924 from the previous symbol 922. This number of steps can be represented as a base-3 digit. It should be understood that a three-step difference between symbols can be represented as 0. base-3 . Figure 9 Table 920 summarizes the coding schemes that use this method.

[0072] At the transmitter, given the previously generated symbol 922 and the input ternary number (which serves as the transition number digit 926), table 920 can be used to look up the current symbol 924 to be transmitted. At the receiver, table 920 can be used as a lookup table to determine the transition number digit 926 representing the transition between the previously received symbol 922 and the currently received symbol 924.

[0073] Depending on certain aspects, the number of transitions 940 can be formed by multiple transition number digits 926, each digit 926 being used to determine the next symbol given the current symbol. In one example, the number of transitions 940 is a ternary number comprising 12 ternary digits 926. In general, there are r possible transitions for each T 926, and the number of transitions 940 with N digits (Ts) 926 has a total of r. N There are 940 states. In the example of 12 digit transitions, for each of the 926 digits in N = 12 digits, there are a total of r = 4 - 1 = 3 possible transitions, thus providing a total of 3 12 = 531,441 distinct states. Therefore, 940 12-bit transitions can encode a 19-bit binary number requiring 524,288 states. The remaining 7,153 states can be used to carry control codes, etc.

[0074] Multiple next-generation devices can coexist with one or more traditional I2C devices on the same serial bus 320. Therefore, high data rate protocols define signaling schemes that can be ignored, undetected, or otherwise disregarded by traditional I2C devices. I3C devices can transmit control information in signaling consistent with I2C mode signaling and can transmit data payloads encoded according to ternary encoding protocols for faster transmission speeds. Next-generation devices can use other encoding schemes to transmit data payloads, including traditional I2C mode.

[0075] Figure 10 A second example of an encoding scheme 1000 employing symbol-shifting encoding on a two-wire serial bus 320 is shown. In this example, a variant of ternary-based digital encoding is used according to the I3C HDR protocol. It is conceivable that certain concepts associated with symbol shifting can be extended to include an I3C serial bus 320 with three or more wires. When three wires are available for transmitting symbols, septenary-based digital encoding can be used; when four wires are available for transmitting symbols, petadecimal-based digital encoding can be used, and so on. A two-wire example is shown in Table 1020 (see also...). Figures 7 to 9 In the equation, the number of transitions 1024 generated by the encoder can be represented as the displacement value 1022 between the states 1008, 1010, 1012, and 1014 on and across the circle. The clockwise displacement 1004 can be represented as the ternary value T = 1, the counterclockwise displacement 1002 can be represented as the ternary value T = 0, and the displacement across the circle (i.e., 2 steps clockwise or counterclockwise) can be represented as the ternary value T = 2.

[0076] Other symbol encoding schemes can be implemented for two-line implementations and / or for implementations using more than two lines. In one example, for N lines (W1…WN), where N≥3, for three or more lines, the encoding can be characterized by a formula for the number of transitions, where for two consecutive states S and S-1:

[0077] {(W1 S XNOR W1 S-1 (W2) S XNOR W2 S-1 ), ……(WN S XNOR WN S-1 )}.

[0078] Figure 11Including timing diagram 1100, which illustrates the signaling state of serial bus 320 during the transmission of symbol sequences according to certain aspects disclosed herein. In the example shown, both clock line 318 and data line 316 are used for data encoding. The raw symbol value 1102 causes the lines of the driving circuitry to drive each of the clock line 318 and data line 316 to a voltage level determined by a single bit of the current raw symbol value 1102. In this example, a symbol bit set to "binary 1" causes the corresponding line of clock line 318 and data line 316 to become a more positive voltage level, while a symbol bit set to "binary 0" causes the corresponding line of clock line 316 and data line 318 to become a more negative voltage level. Figure 11 Table 1120 is provided, which shows four possible signaling states for symbol 1122 when each of clock line 318 and data line 316 can be at one of two voltage levels. Data elements with K bits can be encoded as a sequence of L symbols. The values ​​of K and L can be determined based on the encoding scheme, word size and configuration, and other application parameters (including latency, etc.). Timing diagram 1100 shows an extraction or snapshot of a symbol transmission sequence comprising seven time slots 1104, where symbol 1106 can be transmitted in each time slot 1104. The seven time slots shown can be part of a larger symbol sequence, such as a 12-symbol sequence encoded with a 16-bit word, or can include two or more symbol sequences (e.g., 2, 3… or 6 symbol examples).

[0079] Based on certain aspects disclosed herein, the transmitter can be configured or adapted to ensure that the same symbol is not transmitted in any two consecutive time slots in the time slot 1104 sequence. Therefore, at least one of the clock line 318 and data line 316 changes the signaling state at each boundary between consecutive symbols. The switching of any of the clock line 318 and data line 316 marks the beginning of a new symbol.

[0080] Depending on certain aspects, signaling on the mainline can be configured to avoid generating specific data patterns defined by I3CHDR for indicating reboots, exits, and / or in-band resets. In some cases, the mainline carries data in patterns defined by the standard I3C protocol, including data transmitted using SDR, HDR-DDR, HDR-TSP, and HDR-TSL protocols.

[0081] Error signaling window of phase differential protocol

[0082] Application-defined data throughput and latency requirements may necessitate increasing the base clock rate of the serial bus. Increasing the base clock rate is particularly challenging with respect to timing shutdown in communications based on protocols such as I3C SDR and I3C HDR-DDR, which use a dedicated clock line (SCL) driven by the bus master regardless of the data transmission direction. In a READ transaction, a timing window opens when the clock edge is introduced at the bus master, and the clock signal travels across the serial bus to the slave device, which uses this edge to time data transmissions in the relative direction across the serial bus. In the latter example, transmission and switching delays accumulate and have the greatest impact on the timing window at the receiver circuitry in the bus master.

[0083] Phase differential protocols (such as I3C HDR-TSP and I3C HDR-TSL) can overcome certain timing shutdown issues that can affect I3C SDR and I3CHDL-DDR because they use an embedded clock in each transmission. The clock is embedded by the transmitter and provides timing information in the form of sign transitions, which can be used by the receiver to control the timing of sign capture. That is, the clock information originates from the same end of the serial bus as the transmitted data, and a closely matched propagation path can be easily provided for all lines (including all lines in a multi-channel serial bus).

[0084] Certain aspects of this disclosure provide techniques for detecting errors that may occur when using phase differential protocols. These techniques can improve serial bus performance when using higher clock rates to control transmissions over a serial bus. While examples of the I3C HDR-TSP and I3C HDR-TSL protocols are used to describe certain techniques, apparatuses, and processes, the underlying concepts and the I3C HDR-TSP and I3C HDR-TSL protocols are applicable to other phase differential protocols.

[0085] In high data rate or noisy bus environments employing phase differential protocols, frame synchronization can be problematic. The I3C HDR-TSP and I3C HDR-TSL protocols define data packets encoded in 12-symbol frames. Data is encoded as transitions between symbols, and symbol loss due to noise or sampling circuit errors can affect decoding based on multiple subsequent symbol transitions. The I3C protocols provide parity checking, which can be used to trigger a request for early termination, signaled during one or more early termination signaling modes. When, for example, a timing error causes a receiver to lose or discard a symbol, the early termination signaling mode can lead to bus errors or confusion with normal data transmission symbols due to synchronization loss. In some cases, a receiver that detects a parity error may attempt to signal the transmitter using a protocol-defined mode, potentially causing serious and disruptive bus collisions when synchronization is lost. For example, the transmitter might be transmitting the next frame without receiving any early termination signaling. Unsynchronized receivers attempting to transmit error codes at points between protocol-defined frames can cause bus collisions with the transmitter.

[0086] Certain aspects of this disclosure provide signaling that allows a device to reliably identify an error signaling window. The term "error signaling window" can be used to characterize a signaling pattern that allows a receiving device in a transaction to indicate an error. An error signaling window indicator can be provided, which uses a predefined, unique pattern within the data stream that can be explicitly identified by the sending device in the transaction and serves as an indication of an error detected by the receiving device in the transaction. In one example, the error signaling window can be indicated using a data string containing symbols that are prohibited or do not appear in any other valid data transmission. In another example, the error signaling window can be indicated using an early termination pattern defined by the protocol and can be modified to change one or more timing parameters associated with the early termination pattern.

[0087] According to certain aspects of this disclosure, the mode, timing, and characteristics associated with an error signaling window used with one or more phase differential protocols can be defined by the protocol, configured using command transmission, or negotiated between the transmitter and receiver. During a data transmission transaction, all lines of the serial bus operating according to the phase differential protocol are actively driven. The receiver in the transaction can only signal an error or request action at a time agreed upon between the transmitter and receiver, or at a time pre-configured for both the transmitter and receiver, and provides a specific procedure defined for signaling. The definition of the timing and structure of the error signaling window is necessary to prevent collisions and ensure that synchronization can be re-established after an error occurs.

[0088] In one example, Common Command Codes (CCCs) can be used to configure certain aspects of the error signaling window used with the I3CHDR-TSP or I3C HDR-TSL protocols. In another example, applications on the transmitter and receiver can establish a contract for controlling the use and format of the error signaling window. The operation and configuration of the error signaling window can be defined during system design, initialization, or during bus instantiation of the affected devices. Multichannel serial bus implementations of phase differential protocols can provide error signaling windows using master channels (e.g., SCL and SDA), additional channels, or some combination of master and additional channels.

[0089] Error signaling windows can be used for data transfers to and from bus masters or between slave devices. The timing associated with the error signaling window can be modified by the application to implement robust error identification and ensure reliable serial operation when the timing closes near its specified limits. In examples of the I3C protocol, certain HDR-TSP and HDR-TSL specifications define flow-control procedures that can be adapted to allow the receiver to safely intervene when an error is detected. These procedures can be applied to other phase-differential protocols or symbol-based protocols. These procedures and adaptations are described with reference to certain two-wire serial buses, although these concepts and some implementations are applicable to serial buses with one or more additional lines.

[0090] Figure 12 A first adaptation of signaling 1200, defined by the I3C HDR-TSP and I3C HDR-TSL protocols according to certain aspects disclosed herein, is shown. HDR restart mode 1206 is recognizable in all I3C operating modes, including SDR, HDR-DDR, HDR-TSP, and HDR-TSL modes. HDR restart mode 1206 corresponds to the transmission of a symbol sequence 1208 comprising three or more consecutive symbols 1208 with a value of “2”. The symbol sequence causes SCL 1204 to be held in a low signaling state 1210 while SDA 1202 switches. An edge 1212 on SCL 1204 verifies the restart and can trigger the receiver to capture the current state of SDA 1202 and SCL 1204 to reset or configure the receiver circuitry before the next command word 1214 appears on the serial bus.

[0091] In one aspect of this disclosure, the HDR restart mode 1206 can be adapted to provide an error signaling window identifier 1226 in signaling 1220 transmitted via the serial bus. The error signaling window identifier 1226 is also identifiable in all I3C operating modes, including SDR, HDR-DDR, HDR-TSP, and HDR-TSL modes. The error signaling window identifier 1226 corresponds to the transmission of a symbol sequence including three or more consecutive symbols 1228 with a value of “2”. The symbol sequence causes SCL 1224 to be held in a high signaling state 1230, while SDA 1222 switches. An edge 1232 on SCL 1204 verifies the restart and can trigger the receiver to capture the current state of SDA 1222 and SCL 1224 to reset or configure the receiver circuitry before the next data word 1234 appears on the serial bus.

[0092] Figure 13 and Figure 14 Timing diagrams 1300 and 1400 illustrate first examples of the use of error signaling windows provided according to certain aspects disclosed herein. These first examples relate to master-to-slave transfers.

[0093] Timing diagrams 1300 and 1400 illustrate examples of serial buses operating according to the I3C HDR-TSP or I3C HDR-TSL protocol. Timing diagrams 1300 and 1400 show signaling on SDA 1302, 1402 and SCL 1304, 1404. Timing diagrams 1300 and 1400 also show slave contributions 1322, 1422 to signaling on SDA 1302, 1402, and bus master contributions 1332, 1432 to signaling on SDA 1302, 1402. Timing diagrams 1300 and 1400 further show slave contributions 1324, 1424 to signaling on SCL 1304, 1404, and bus master contributions 1334, 1434 to signaling on SCL 1304, 1404. The contribution to signaling on SDA 1302, 1402 or SCL 1304, 1404 is shown as a solid line, while a dashed line indicates that the corresponding device's driver is in a high-impedance state. In some cases, the bus master can put the output of one of its drivers coupled to the serial bus line into a high-impedance state while connecting a holder circuit or a passive pull-up or pull-down circuit to the driver output to maintain the expected or default signaling state on the serial bus line.

[0094] Figure 13Timing diagram 1300 illustrates the termination of a master-to-slave transfer by a slave device using an error signaling window provided according to certain aspects disclosed herein. At time 1306, after the bus master has completed the transmission of the last symbol (T0) used for encoding the data word, the bus master actively drives SDA 1302 and SCL 1304 high at time 1308. During each subsequent symbol transmission interval, the bus master maintains SCL 1304 high while toggling SDA 1302. The combination of SCL 1304 high and SDA 1302 toggled is interpreted as a symbol with a value of "2". A sequence of three or more symbols with a value of "2" is prohibited in data transmission according to the I3C phase differential protocol, and such a sequence is identified as an error signaling window in the bus master and slave devices configured according to certain aspects of this disclosure. The error signaling window signaling can be generated by logic circuitry in the bus master.

[0095] The slave device, acting as the transmitter, may include logic circuitry configured to detect error signaling windows independently of its own decoding logic. In some cases, the error signaling window may be configured to generate three or more symbols with a value of "2" at the receiver, allowing the receiver to identify the error signaling window when one or more symbols are lost or contain errors. The slave device can determine that the error signaling window was received unexpectedly. For example, lost or discarded symbols may cause the error signaling window to be detected prematurely. Early or late detection of the error signaling window by the slave device, or detection of parity errors, can be interpreted as an error condition. For example, other error conditions may occur in higher-level applications. Detection of any type of communication error may cause the slave device to terminate the transmission.

[0096] According to one aspect, by driving SCL 1304 to a low-signal state, the slave device can terminate transmission after detecting or receiving a third symbol 1312 with a value of "2". After the transition corresponding to the third symbol 1312 with a value of "2" is transmitted, the bus master can release SCL 1304 to a high-impedance state 1310 to allow the slave device to drive SCL 1304. When putting its line driver into a high-impedance state, the bus master can couple a retainer circuit or a passive pull-up circuit to SCL 1304. After driving SCL 1304 to a low-signal state, and after allowing the bus master to detect one or more edges of transition 1314 in SDA 1302, the slave device puts its line driver into a high-impedance mode.

[0097] After the bus master detects transition 1314 in SCL 1304, it actively drives SCL 1304 to a low-signal state 1318 via its line driver. The bus master can then terminate the transfer. In one example, the bus master keeps SCL 1304 in a low-signal state 1318 and continues to switch SDA 1302 to generate an HDR exit or restart mode, which includes an additional sequence of three or more value "2" symbols 1320.

[0098] Figure 14 Timing diagram 1400 illustrates the continuation of the master-to-slave transmission indicated by an error signaling window provided by the slave device using certain aspects disclosed herein. At time 1406, when the bus master has completed the transmission of the last symbol (T0) for encoding the data word, the bus master actively drives SDA 1402 and SCL 1404 high at time 1408. During each subsequent symbol transmission interval, the bus master maintains SCL 1404 high while toggling SDA 1402. The combination of SCL 1404 being high and SDA 1402 being toggled is interpreted as a symbol with a value of "2", and a sequence of three or more such symbols is prohibited in the I3C phase differential protocol for data transmission and is identified as an error signaling window in the bus master and slave devices configured according to certain aspects of this disclosure. The error signaling window signaling can be generated by logic circuitry in the bus master.

[0099] The slave device, acting as the sender, may include logic circuitry configured to detect error signaling windows independently of the decoding logic within the slave device. In some cases, the error signaling window may be configured to generate three or more symbols with a value of "2" at the receiver, allowing the receiver to identify the error signaling window when one or more symbols are missing or contain errors. The slave device can determine that the error signaling window has been received in a timely manner and that no other types of communication errors have been detected.

[0100] According to one aspect, when no error is detected, the slave device can suppress the driving of SDA1402 and SCL1404. After the transition corresponding to the third symbol 1412 with a value of "2" is transmitted, the bus master can release SCL1404 to a high-impedance state 1410 to allow the slave device to drive SCL1404 as needed. When putting its line driver into a high-impedance state, the bus master can couple a hold circuit or a passive pull-up circuit to SCL1404. The bus master actively drives its line driver to a low-signal state 1414 after a certain period of time, which is calculated to provide sufficient time for the slave device to request termination. In some examples, the bus master waits for 1 to 8 symbol intervals to allow the slave device to request termination. In some examples, the bus master stretches one or more symbol intervals to allow the slave device to request termination.

[0101] Figure 15 and Figure 16 Timing diagrams 1500 and 1600 illustrate second examples of the use of error signaling windows provided according to certain aspects disclosed herein. The second example pertains to transmission from device to master device.

[0102] Timing diagrams 1500 and 1600 illustrate examples of serial buses operating according to the I3C HDR-TSP or I3C HDR-TSL protocol. Timing diagrams 1500 and 1600 show signaling on SDA 1502, 1602 and SCL 1504, 1604. Timing diagrams 1500 and 1600 also show slave contributions 1522 and 1622 to signaling on SDA 1502, 1602, and bus master contributions 1532 and 1632 to signaling on SDA 1502, 1602. Timing diagrams 1500 and 1600 further show slave contributions 1524 and 1624 to signaling on SCL 1504, 1604, and bus master contributions 1534 and 1634 to signaling on SCL 1504, 1604. The contribution to signaling on SDA 1502, 1602 or SCL 1504, 1604 is shown as a solid line, while a dashed line indicates that the corresponding device's driver is in a high-impedance state. In some cases, the bus master can put the output of one of its drivers coupled to the serial bus line into a high-impedance state while connecting a holder circuit or a passive pull-up or pull-down circuit to the driver output to maintain the expected or default signaling state on the serial bus line.

[0103] Figure 15Timing diagram 1500 illustrates the termination of a slave-to-master transfer by the master device using an error signaling window provided according to certain aspects disclosed herein. At time 1506, when the slave device has completed the transmission of the last symbol (T0) used for encoding the data word, the slave device actively drives SDA 1502 and SCL 1504 high at state 1508. During each subsequent symbol transmission interval, the slave device maintains SCL 1504 high while toggling SDA 1502. The combination of SCL 1504 high and SDA 1502 toggled is interpreted as a symbol with a value of "2", and a sequence of three or more such symbols is prohibited in the I3C phase differential protocol for data transmission and is identified as an error signaling window in the bus master and slave devices configured according to certain aspects of this disclosure. The error signaling window signaling can be generated by logic circuitry in the slave device.

[0104] The bus master may include logic circuitry configured to detect error signaling windows independently of the decoding logic within the bus master. In some cases, the error signaling window may be configured to generate three or more symbols with a value of "2" at the receiver, allowing the receiver to identify the error signaling window when one or more symbols are missing or contain errors. The bus master can determine that an error signaling window has been received unexpectedly. For example, a lost or discarded symbol may cause the error signaling window to be detected prematurely. Premature or delayed detection of error signaling windows by the slave device, or detection of parity errors, can be interpreted as error conditions. For example, other error conditions may occur in higher-level applications. Detection of any type of communication error may cause the bus master to terminate transmission.

[0105] According to one aspect, by driving SCL 1504 to a low-signal state, the bus master can terminate the transmission after detecting or receiving a third symbol 1512 with a value of "2". After the transition corresponding to the third symbol 1512 with a value of "2" is transmitted, the slave device can release SCL 1504 to a high-impedance state 1510 to allow the bus master to drive SCL 1504. Before the slave device puts its line driver into a high-impedance state, the bus master can couple a hold circuit or a passive pull-up circuit to SCL 1504. The bus master actively drives SCL 1504 to a low-signal state 1518 on the next falling edge of SDA 1502. The bus master can then terminate the transmission. In one example, the bus master holds SCL 1504 in a low-signal state and continues to toggle SDA 1502 to generate an HDR exit or restart mode that includes an additional sequence of three or more symbols 1520 with a value of "2".

[0106] Figure 16 Timing diagram 1600 illustrates the continuation of a slave-to-master transfer indicated by an error signaling window provided by the bus master using certain aspects disclosed herein. At time 1606, after the bus master has completed the transmission of the last symbol (T0) for encoding the data word, the slave actively drives SDA 1602 and SCL 1604 to a high signaling state 1608. During each subsequent symbol transmission interval, the slave maintains SCL 1604 high while toggling SDA 1602. The combination of SCL 1604 being high and SDA 1602 being toggled is interpreted as a symbol with a value of "2", and a sequence of three or more such symbols is prohibited in the I3C phase differential protocol for data transmission and is identified as an error signaling window in the bus master and slave configured according to certain aspects of this disclosure. The error signaling window signaling can be generated by logic circuitry in the slave device.

[0107] The bus master device may include logic circuitry configured to detect error signaling windows independently of the decoding logic in the slave device. In some cases, the error signaling window may be configured to generate three or more symbols with a value of "2" at the receiver, so that the receiver can identify the error signaling window when one or more symbols are missing or contain errors. The bus master device can determine that the error signaling window has been received in a timely manner and that no other types of communication errors have been detected.

[0108] According to one aspect, when no error is detected, the bus master can suppress the driving of SDA 1602 and SCL 1604. If the bus master requires it, after the transition corresponding to the third symbol 1612 with a value of "2" is transmitted, the slave device can release SCL 1604 to a high-impedance state 1610 so that the bus master can drive SCL 1604 as needed. Before the slave device puts its line driver into a high-impedance state 1614, the bus master can couple a hold circuit or a passive pull-up circuit to SCL 1604. The slave device actively drives its line driver to a low-signal state 1618 after a certain period of time, which is calculated to provide sufficient time for the bus master to request termination. In some examples, the slave device waits for 1 to 8 symbol intervals to allow the slave device to request termination. In some examples, the slave device extends one or more symbol intervals to allow the slave device to request termination.

[0109] In the above example, the receiving device can terminate the transmission by activating the driver and changing the signaling state of SDA 1302, 1402, 1502, or 1602, and allow the transmission to continue by not taking any action to change the signaling state. In some implementations, the receiving device may need to affirmatively acknowledge receipt of one or more data words before the transmission continues. In these implementations, the receiving device allows the transmission to continue by activating the driver and changing the signaling state of SDA 1302, 1402, 1502, or 1602, and allows the transmission to terminate by not taking any action to change the signaling state.

[0110] Figure 17 A second adaptation of signaling 1700, defined by the I3C HDR-TSP and I3C HDR-TSL protocols according to certain aspects disclosed herein, is shown. HDR early termination mode 1706 can be transmitted after a predetermined number of symbols, frames, or data words 1708. In the example shown, the bus master uses early termination mode 1706 to terminate data transmission from the slave device. In this example, the slave device provides sufficient additional clock pulses 1712 to enable the bus master to signal the request for early termination. The slave device initially drives SDA 1702 to a high signaling state 1710 before releasing SDA 1702 by bringing its line driver output to a high impedance state 1714. The bus master may couple a hold circuit or a pull-up circuit to SDA 1702 before the slave device releases SDA 1702. The bus master can terminate the transmission by driving SDA 1702 to a low signaling state 1716 after the falling edge 1718 of the first clock pulse 1712 on SCL 1704. The slave device recognizes the change in the state of SDA 1702 after the falling edge of the second clock pulse 1712 in clock pulse 1712. The slave device releases SCL 1704 at time 1720, enabling the bus master to control the serial bus and provide HDR exit or HDR restart signaling.

[0111] In one aspect of this disclosure, early termination mode 1706 can be adapted to provide an error signaling window identifier. The error signaling window identifier can be provided as a part of delayed early termination mode 1706.

[0112] Timing diagrams 1800 and 1900 illustrate examples of serial buses operating according to the I3C HDR-TSP or I3C HDR-TSL protocol. Timing diagrams 1800 and 1900 show signaling on SDA 1802, 1902 and SCL 1804, 1904. Timing diagrams 1800 and 1900 also show slave contributions 1822 and 1922 to signaling on SDA 1802, 1902, and bus master contributions 1832 and 1932 to signaling on SDA 1802, 1902. Timing diagrams 1800 and 1900 further show slave contributions 1824 and 1924 to signaling on SCL 1804, 1904, and bus master contributions 1834 and 1934 to signaling on SCL 1804, 1904. Contributions to signaling on SDA 1802, 1902 or SCL 1804, 1904 are shown as solid lines, while dashed lines indicate that the corresponding device's driver is in a high-impedance state. In some cases, the bus master can put the output of one of the drivers coupled to the serial bus line into a high-impedance state while connecting a hold circuit or passive pull-up or pull-down circuit to the driver output to maintain the expected or default signaling state on the serial bus line.

[0113] Figure 18 Timing diagram 1800 illustrates the termination of a master-to-slave transfer by the slave device using an error signaling window provided according to certain aspects disclosed herein. The bus master actively drives SDA 1802 high and provides a clock pulse on SCL 1804 after a delay of 1806. Following the delay, an early termination mode 1808 is provided. Early termination mode 1808 corresponds to early termination mode 1706, except for the delay of 1806. Figure 18 In the example, the slave device signals a request to terminate the transmission by driving SDA 1802 low to state 1810 before releasing SDA 1802 at time 1812, so that the bus master can acquire control of the serial bus on the falling edge of the second pulse on SCL 1804. The bus master can then provide HDR restart or HDR exit signaling.

[0114] The duration of delay 1806 can be selected based on application requirements, bus clock rate, and expected error rate of bus transmission. Delay 1806 can include multiple bus clock cycles. In one example, when using a 100MHz bus clock, delay 1806 includes 8 bus clock cycles. Delay 1806 enables the receiving device to recognize early termination mode 1808, which includes an error signaling window capable of preventing synchronization errors from causing collisions.

[0115] Figure 19Timing diagram 1900 illustrates a transaction where the slave device allows master-to-slave transmission to continue after an error signaling window, provided according to certain aspects disclosed herein, is detected. The bus master actively drives SDA 1902 high and actively provides a clock pulse on SCL 1904 after a delay of 1906. Following the delay, early termination mode 1908 is provided. Early termination mode 1908 corresponds to early termination mode 1706, except for the delay of 1906. Figure 19 In the example, the slave device suppresses the drive of SDA 1902, allowing the bus master to retain control of the serial bus. The bus master can then begin the transmission of the next data word at time 1910.

[0116] The duration of delay 1906 can be selected based on application requirements, bus clock rate, and expected error rate of bus transmission. Delay 1906 can include multiple bus clock cycles. In one example, when using a 100MHz bus clock, delay 1906 includes 8 bus clock cycles. Delay 1906 enables the receiving device to recognize early termination mode 1908, which includes an error signaling window capable of preventing synchronization errors from causing collisions.

[0117] Timing diagrams 2000 and 2100 illustrate examples of serial buses operating according to the I3C HDR-TSP or I3C HDR-TSL protocol. Timing diagrams 2000 and 2100 show signaling on SDA 2002, 2102 and SCL 2004, 2104. Timing diagrams 2000 and 2100 also show slave device contributions 2022 and 2122 to signaling on SDA 2002, 2102, and bus master contributions 2032 and 2132 to signaling on SDA 2002, 2102. Timing diagrams 2000 and 2100 further show slave device contributions 2024 and 2124 to signaling on SCL 2004, 2104, and bus master contributions 2034 and 2134 to signaling on SCL 2004, 2104. The contribution to signaling on SDA 2002, 2102 or SCL 2004, 2104 is shown as a solid line, while a dashed line indicates that the driver of the corresponding device is in a high-impedance state. In some cases, the bus master can put the output of one of its drivers coupled to the serial bus line into a high-impedance state while connecting a holder circuit or a passive pull-up or pull-down circuit to the driver output to maintain the expected or default signaling state on the serial bus line.

[0118] Figure 20Timing diagram 2000 illustrates the termination of a slave-to-master transfer by the bus master device using an error signaling window provided according to certain aspects disclosed herein. The slave device actively drives SDA 2002 high and provides a clock pulse on SCL 2004 after a delay of 2006. Following the delay, early termination mode 2008 is provided. Early termination mode 2008 corresponds to early termination mode 1706, except for the delay 2006. Figure 20 In the example, the bus master signals a request to terminate the transmission by driving SDA 2002 low to state 2010 before releasing SDA 2002 at time 2012. The slave device releases SCL 2004 by entering a high-impedance state, allowing the bus master to acquire control of the serial bus at the falling edge of the second pulse on SCL 2004. The bus master can then provide HDR restart or HDR exit signaling.

[0119] The duration of delay 2006 can be selected based on application requirements, bus clock rate, and expected error rate of bus transmission. Delay 2006 can include multiple bus clock cycles. In one example, when using a 100MHz bus clock, delay 2006 includes 8 bus clock cycles. Delay 2006 enables the receiving device to recognize the early termination mode 2008, which includes an error signaling window capable of preventing synchronization errors from causing collisions.

[0120] Figure 21 Timing diagram 2100 illustrates a transaction where the bus master allows slave-to-master transmission to continue after an error signaling window, provided according to certain aspects disclosed herein, is detected. The slave device actively drives SDA 2102 high and provides a clock pulse on SCL 2104 after a delay 2106. Following the delay, an early termination mode 2108 is provided. Early termination mode 2108 corresponds to early termination mode 1706, except for delay 2106. Figure 21 In the example, the bus master suppresses the drive of SDA 2102, allowing the slave device to retain control of the serial bus. The slave device can then begin transmitting the next data word at time 2110.

[0121] The duration of delay 2106 can be selected based on application requirements, bus clock rate, and expected error rate of bus transmission. Delay 2106 can include multiple bus clock cycles. In one example, when using a 100MHz bus clock, delay 2106 includes 8 bus clock cycles. Delay 2106 enables the receiving device to recognize early termination mode 2108, which includes an error signaling window capable of preventing synchronization errors from causing collisions.

[0122] Examples of processing circuits and methods

[0123] Figure 22 This is a diagram illustrating an example of a hardware implementation of a device 2200 employing processing circuitry 2202, which may be configured to perform one or more functions disclosed herein. Elements, or any portion thereof, or any combination thereof disclosed herein, may be implemented using processing circuitry 2202 according to various aspects of this disclosure. Processing circuitry 2202 may include one or more processors 2204 controlled by some combination of hardware and software modules. Examples of processors 2204 include microprocessors, microcontrollers, digital signal processors (DSPs), SoCs, ASICs, field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, sequencers, gated logic, discrete hardware circuitry, and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors 2204 may include dedicated processors that perform specific functions and may be configured, enhanced, or controlled by one of the software modules 2216. One or more processors 2204 may be configured by a combination of software modules 2216 loaded during initialization, and may also be configured by loading or unloading one or more software modules 2216 during operation. In various examples, the processing circuit 2202 may be implemented using a state machine, sequencer, signal processor and / or general-purpose processor, or a combination of such devices and circuits.

[0124] In the illustrated example, processing circuitry 2202 can be implemented using a bus architecture (generally represented by bus 2210). Depending on the specific application and overall design constraints of processing circuitry 2202, bus 2210 may include any number of interconnect buses and bridges. Bus 2210 links various circuits together, including one or more processors 2204 and storage devices 2206. Storage devices 2206 may include memory devices and mass storage devices, and may be referred to herein as computer-readable media and / or processor-readable media. Bus 2210 may also link various other circuits, such as timing sources, timers, peripheral devices, voltage regulators, and power management circuitry. Bus interface 2208 may provide an interface between bus 2210 and one or more transceivers 2212. A transceiver 2212 may be provided for each networking technology supported by processing circuitry 2202. In some cases, multiple networking technologies may share some or all of the circuitry or processing modules in transceiver 2212. Each transceiver 2212 provides components for communicating with various other devices via a transmission medium. Depending on the nature of the device 2200, a user interface 2218 (e.g., keypad, display, speaker, microphone, joystick) may also be provided, and the user interface 2218 may be directly or communicatively coupled to the bus 2210 via the bus interface 2208.

[0125] Processor 2204 may be responsible for managing bus 2210 and general processing, which may include the execution of software stored on a computer-readable medium, including storage device 2206. In this regard, processing circuitry 2202 including processor 2204 may be used to implement any of the methods, functions, and techniques disclosed herein. Storage device 2206 may be used to store data manipulated by processor 2204 during software execution, and the software may be configured to implement any of the methods disclosed herein.

[0126] One or more processors 2204 in processing circuitry 2202 can execute software. Software should be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, algorithms, etc., whether referred to as software, firmware, middleware, microcode, hardware description languages, or others. Software may reside in storage device 2206 in a computer-readable form or on external computer-readable media. External computer-readable media and / or storage device 2206 may include non-transitory computer-readable media. For example, non-transitory computer-readable media include magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes), optical discs (e.g., optical compact discs (CDs) or digital versatile discs (DVDs)), smart cards, flash memory storage devices (e.g., "flash drives," cards, sticks, or key drives), RAM, ROM, programmable read-only memory (PROM), erasable PROM (EPROM) (including EEPROM), registers, removable disks, and any other suitable media for storing software and / or instructions that can be accessed and read by a computer. For example, computer-readable media and / or storage device 2206 may also include carrier waves, transmission lines, and any other suitable media for transmitting software and / or instructions that can be accessed and read by a computer. Computer-readable media and / or storage device 2206 may reside in processing circuitry 2202, in processor 2204, outside of processing circuitry 2202, or distributed across multiple entities including processing circuitry 2202. Computer-readable media and / or storage device 2206 may be implemented in a computer program product. As an example, a computer program product may include computer-readable media in packaging material. Those skilled in the art will recognize how best to implement the functions described throughout this disclosure, depending on the specific application and the overall design constraints imposed on the system.

[0127] Storage device 2206 can maintain and / or organize software within loadable code segments, modules, applications, programs, etc., which may be referred to herein as software module 2216. Each software module in software module 2216 may include instructions and data that, when installed or loaded onto processing circuitry 2202 and executed by one or more processors 2204, contribute to a runtime image 2214 that controls the operation of one or more processors 2204. When executed, certain instructions may cause processing circuitry 2202 to perform functions according to certain methods, algorithms, and procedures described herein.

[0128] Some software modules in software module 2216 may be loaded during the initialization of processing circuit 2202, and these software modules 2216 may configure processing circuit 2202 to perform the various functions disclosed herein. For example, some software modules 2216 may configure the internal devices and / or logic circuit 2222 of processor 2204, and may manage access to external devices such as transceiver 2212, bus interface 2208, user interface 2218, timers, math coprocessors, etc. Software module 2216 may include a control program and / or operating system that interacts with the interrupt handler and device drivers, and controls access to various resources provided by processing circuit 2202. These resources may include memory, processing time, access to transceiver 2212, user interface 2218, etc.

[0129] One or more processors 2204 of the processing circuitry 2202 can be multifunctional, wherein some software modules in software module 2216 are loaded and configured to perform different functions or different instances of the same function. For example, one or more processors 2204 can be additionally adapted to manage background tasks initiated in response to input from user interface 2218, transceiver 2212, and device driver. To support the execution of multiple functions, one or more processors 2204 can be configured to provide a multitasking environment, wherein each of the multiple functions is implemented as a set of tasks served by one or more processors 2204 as needed or desired. In one example, the multitasking environment can be implemented using a timesharing procedure 2220 that passes control of processors 2204 between different tasks, wherein each task returns control of one or more processors 2204 to the timesharing procedure 2220 upon completion of any unfinished operation and / or in response to input such as an interrupt. When a task has control over one or more processors 2204, the processing circuitry is effectively dedicated to the purpose of processing the functions associated with the control task. The time-sharing program 2220 may include an operating system, a main loop that transmits control on a loop-based basis, a function that allocates control over one or more processors 2204 according to the priority of the function, and / or an interrupt-driven main loop that responds to external events by providing control over one or more processors 2204 to the processing function.

[0130] Figure 23 This is flowchart 2300, illustrating a method that can be performed at a receiving device coupled to a serial bus. The serial bus can operate according to one or more I3C protocols. In block 2302, the receiving device can receive a sequence of symbols. Each symbol can represent a signaling state of the serial bus. For example, a 2-bit symbol can be used to represent the binary state of two lines of the serial bus, a 3-bit symbol can be used to represent the binary state of three lines of the serial bus, and so on. In block 2304, the receiving device can decode data based on transitions between symbol pairs in the symbol sequence. For example, the receiving device can use the number of transitions to represent the difference between successive signaling states, where data can be extracted from the number of transitions, which is generated from the symbol sequence.

[0131] In block 2306, the receiving device can detect an indicator of an error signaling window in the signaling status of the two lines of the serial bus. In some embodiments, the indicator of the error signaling window corresponds to a prohibited symbol combination. For example, a prohibited symbol combination can generate a signaling pattern that triggers a response to a device that does not otherwise participate in data transmission. In some embodiments, the error signaling window is indicated when a control signaling is delayed. In some embodiments, the indicator of the error signaling window precedes the error signaling window by one or more symbol intervals.

[0132] In box 2308, when an error is detected during the timing of the error signaling window's indicator or in the symbol sequence, the receiving device may signal the error during the error signaling window. In some examples, errors detected in the symbol sequence involve parity errors. An error can be detected when the error signaling window's indicator begins at an unexpected time or position in the symbol sequence, where the device is pre-configured with indications of the expected time of the error signaling window or the expected position in the symbol sequence. An error can be detected when the error signaling window's indicator begins before the complete symbol sequence is received. An error can be detected when the symbol sequence includes one or more symbols from a prohibited symbol combination.

[0133] In some implementations, a phase differential decoder is used to decode the data, and a detection circuit that operates independently of the phase differential decoder is used to detect errors in the timing of the indicator in the error signal window or in the symbol sequence.

[0134] In some examples, the receiving device is configured to operate as a slave device, and data transmission can be terminated after the device signals an error. In other examples, the receiving device operates as a bus master device and transmits a signaling mode configured to terminate data transmission after an error is signaled.

[0135] In one example, when the early termination mode is delayed, the receiving device can detect an indicator of the error signaling window. In another example, when the first of two lines is switched after each of three or more symbol intervals, while the second of the two lines of the serial bus remains in the first signaling state, the receiving device can detect an indicator of the error signaling window. When the first of two lines is switched after each of three or more symbol intervals, while the second of the two lines of the serial bus remains in the second signaling state, a synchronization mode of later or earlier transmission can be detected.

[0136] Figure 24This is a diagram illustrating an example hardware implementation of a device 2400 employing processing circuitry 2402. In one example, device 2400 is configured for data communication via a serial bus operating according to one or more I3C protocols. Processing circuitry 2402 typically has a controller or processor 2416, which may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuitry 2402 may be implemented using a bus architecture (generally represented by bus 2420). Depending on the specific application and overall design constraints of processing circuitry 2402, bus 2420 may include any number of interconnect buses and bridges. Bus 2420 links various circuits together, including one or more processors and / or hardware modules represented by controller or processor 2416, modules or circuits 2404, 2406, and 2408, and processor-readable storage medium 2418. Device 2400 may be coupled to a multi-line communication link using physical layer circuitry 2414. The physical layer circuit 2414 can operate the multi-wire serial bus 2412 to support communication compliant with the I3C protocol. The bus 2420 can also link various other circuits, such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will therefore not be described further.

[0137] Processor 2416 is responsible for general processing, including the execution of software, code, and / or instructions stored on processor-readable storage medium 2418. Processor-readable storage medium 2418 may include non-transitory storage. When executed by processor 2416, the software causes processing circuitry 2402 to perform the various functions described above for any particular device. Processor-readable storage medium 2418 may be used to store data manipulated by processor 2416 during software execution. Processing circuitry 2402 also includes at least one of modules 2404, 2406, and 2408. Modules 2404, 2406, and 2408 may be software modules running in processor 2416, residing in / stored in processor-readable storage medium 2418, one or more hardware modules coupled to processor 2416, or some combination thereof. Modules 2404, 2406, and 2408 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0138] In one configuration, device 2400 is a data communication device including physical layer circuitry 2414, which may include one or more line driver circuits coupled to a multi-line serial bus 2412. Device 2400 includes a module and / or circuitry 2406 configured to decode data based on a symbol sequence received from the multi-line serial bus 2412, and a module and / or circuitry 2408 configured to detect errors in the received symbol sequence or data decoded from the symbol sequence. Device 2400 includes a module and / or circuitry 2404 configured to detect an error signaling window for data transmission via the multi-line serial bus 2412 and to signal errors within the error signaling window.

[0139] In one example, device 2400 includes a bus interface configured to couple the device to a multi-wire serial bus 2412; a phase differential decoder configured to decode data based on transitions between symbol pairs in a symbol sequence received from the serial bus, each symbol representing a signaling state of the serial bus; and a processor 2416. Processor 2416 may be configured to detect indicators of error signaling windows in the signaling states of two lines of the serial bus, the indicators corresponding to prohibited symbol combinations or delays in control signaling; and to signal errors via the bus interface during the error signaling window period when an error is detected in the timing of the error signaling window indicator or in the symbol sequence.

[0140] In one example, errors detected in the symbol sequence include parity errors. In another example, processor 2416 is also configured to detect an error when the indicator of the error signaling window begins at an unexpected time or an unexpected position in the symbol sequence, wherein the device is pre-configured with an indication of the expected time of the error signaling window or the expected position in the symbol sequence. In another example, processor 2416 is also configured to detect an error when the indicator of the error signaling window begins before the complete symbol sequence is received. Processor 2416 may also be configured to detect an error when the symbol sequence includes one or more symbols from a prohibited symbol combination. In some implementations, the indicator of the error signaling window precedes the error signaling window by one or more symbol intervals.

[0141] In some embodiments, the apparatus 2400 includes a detection circuit configured to detect errors in the timing of an error signaling window indicator or in a symbol sequence, independent of the phase differential decoder. The detection circuit can also be configured to detect an error signaling window indicator when a first of two lines is switched after each of three or more symbol intervals, while a second of two lines of the serial bus remains in a first signaling state. A later or earlier transmission synchronization pattern can be detected when the first of two lines is switched after each of three or more symbol intervals, while the second of two lines of the serial bus remains in a second signaling state.

[0142] The detection circuit can also be configured to detect an indicator of an error signaling window when the early termination mode is delayed.

[0143] In some cases, the device is configured to operate as a slave device, and data transmission is terminated after an error is signaled. In other cases, the processor is also configured to operate the device as a bus master and transmit a signaling mode configured to terminate data transmission after an error is signaled.

[0144] The processor-readable storage medium 2418 may include instructions that cause the processing circuitry 2402 to perform the following operations: receive a sequence of symbols, each symbol representing a signaling state of a serial bus; decode data according to transitions between symbol pairs in the symbol sequence; detect indicators of error signaling windows in the signaling states of two lines of the serial bus, the indicators of the error signaling windows corresponding to prohibited symbol combinations or delays in control signaling; and signal an error during an error signaling window when an error is detected in the timing of the indicator of the error signaling window or in the symbol sequence.

[0145] In some examples, errors detected in the symbol sequence include parity errors. Errors can be detected when the indicator of the error signaling window begins at an unexpected time or an unexpected position in the symbol sequence, where the device is pre-configured with indications of the expected time of the error signaling window or the expected position in the symbol sequence. Errors can be detected when the indicator of the error signaling window begins before the complete symbol sequence is received. Errors can be detected when the symbol sequence includes one or more symbols from a prohibited symbol combination. In some implementations, a phase differential decoder is used to decode the data, and detection circuitry operating independently of the phase differential decoder is used to detect errors in the timing of the indicator of the error signaling window or in the symbol sequence.

[0146] In some examples, the processor-readable storage medium 2418 may include instructions that cause the processing circuitry 2402 to operate the device 2400 as a slave device, and data transmission may be terminated after the processing circuitry 2402 signals an error. In other examples, the device 2400 is operated as a bus master device and transmits a signaling mode configured to terminate data transmission after an error is signaled. In some implementations, the indicator of the error signaling window precedes the error signaling window by one or more symbol intervals.

[0147] In one example, the processor-readable storage medium 2418 may include instructions to cause the processing circuitry 2402 to: detect an indicator of an error signaling window when a first of two lines is switched after each of three or more symbol intervals, while a second of the two lines of the serial bus remains in a first signaling state; and detect a synchronization mode of later or earlier transmission when the first of two lines is switched after each of three or more symbol intervals, while a second of the two lines of the serial bus remains in a second signaling state. In another example, the processor-readable storage medium 2418 may include instructions to cause the processing circuitry 2402 to detect an indicator of an error signaling window when an early termination mode is delayed.

[0148] Figure 25 This is flowchart 2500, illustrating a method that can be performed at a transmission device coupled to a serial bus. The serial bus can operate according to one or more I3C protocols. In block 2502, the transmission device can encode data as transitions between symbol pairs in a symbol sequence. Each symbol can define the signaling state of the serial bus. For example, a 2-bit symbol can define the binary state of two lines of the serial bus in a symbol transmission interval, a 3-bit symbol can define the binary state of three lines of the serial bus in a symbol transmission interval, and so on. In block 2504, the transmission device can transmit symbol sequences via the serial bus.

[0149] In box 2506, the transmitting device can transmit an indicator of an error signaling window in the signaling state of the two lines of the serial bus. The indicator of the error signaling window may correspond to a forbidden symbol combination or a delay in control signaling. In one example, a forbidden symbol combination may generate a signaling pattern that triggers a response to a device not otherwise participating in data transmission. In some examples, the transmitting device may transmit the indicator of the error signaling window at a pre-configured position or pre-configured time in the symbol sequence. In box 2508, the transmitting device may receive a receive signaling indicating an error in the symbol sequence or an error in the timing of the indicator of the error signaling window within the error signaling window. In box 2510, when an error signaling indication is received within the error signaling window, the transmitting device may terminate data transmission.

[0150] In some examples, the transmission device may use a phase differential encoder to encode the data, and circuitry that operates independently of the phase differential encoder may be used to generate an indicator for the error signal window.

[0151] In some implementations, the transmission device can generate an indicator for the error signaling window using a delayed early termination mode. The transmission device can operate as either a bus master or a slave. In some implementations, the transmission device can generate an indicator for the error signaling window by switching the first of two lines after each of three or more symbol intervals, while the second of the two lines of the serial bus remains in the first signaling state. A synchronization mode of later or earlier transmission can be detected when the first of the two lines is switched after each of three or more symbol intervals, while the second of the two lines of the serial bus remains in the second signaling state.

[0152] Figure 26 This is a diagram illustrating an example hardware implementation of a device 2600 employing processing circuitry 2602. In one example, device 2600 is configured for data communication via a serial bus operating according to one or more I3C protocols. Processing circuitry 2602 typically has a controller or processor 2616, which may include one or more microprocessors, microcontrollers, digital signal processors, sequencers, and / or state machines. Processing circuitry 2602 may be implemented using a bus architecture (generally represented by bus 2620). Depending on the specific application and overall design constraints of processing circuitry 2602, bus 2620 may include any number of interconnect buses and bridges. Bus 2620 links various circuits together, including one or more processors and / or hardware modules represented by controller or processor 2616, modules or circuits 2604, 2606, and 2608, and processor-readable storage medium 2618. Device 2600 may be coupled to a multi-line communication link using physical layer circuitry 2614. Physical layer circuitry 2614 can operate multi-wire serial bus 2612 to support communication compliant with the I3C protocol. Bus 2620 can also link various other circuits, such as timing sources, peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will therefore not be described further.

[0153] Processor 2616 is responsible for general processing, including the execution of software, code, and / or instructions stored on processor-readable storage medium 2618. Processor-readable storage medium 2618 may include non-transitory storage. When executed by processor 2616, the software causes processing circuitry 2602 to perform the various functions described above for any particular device. Processor-readable storage medium 2618 may be used to store data manipulated by processor 2616 during software execution. Processing circuitry 2602 also includes at least one of modules 2604, 2606, and 2608. Modules 2604, 2606, and 2608 may be software modules running in processor 2616, residing in / stored in processor-readable storage medium 2618, one or more hardware modules coupled to processor 2616, or some combination thereof. Modules 2604, 2606, and 2608 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.

[0154] In one configuration, device 2600 includes physical layer circuitry 2614, which may include one or more line driver circuits coupled to a multi-wire serial bus 2612. Device 2600 includes modules and / or circuitry 2606 configured to encode data in a symbol sequence to be transmitted via the multi-wire serial bus 2612, and modules and / or circuitry 2608 configured to process errors in the symbol sequence or data decoded from a symbol sequence reported by a receiving device. Device 2600 includes modules and / or circuitry 2604 configured to provide an error signaling window for data transmission via the multi-wire serial bus 2612 and to monitor the error signaling window.

[0155] In one example, device 2600 includes a bus interface configured to couple the device to a multi-wire serial bus 2612; a phase differential encoder configured to decode data based on transitions between symbol pairs in a symbol sequence received from the serial bus, each symbol representing a signaling state of the serial bus; and a processor 2616. Processor 2616 may be configured to transmit indicators of error signaling windows in the signaling states of the two lines of the serial bus. The indicators of the error signaling windows may correspond to prohibited symbol combinations or delays in control signaling. Processor 2616 may also be configured to receive signaling indicating errors in the symbol sequence or in the timing of the indicators of the error signaling windows within the error signaling windows. Processor 2616 may also be configured to terminate data transmission when an error signaling indication is received in the error signaling windows.

[0156] In some embodiments, apparatus 2600 includes signaling circuitry configured to generate an indicator of an error signaling window independently of a phase differential encoder. The signaling circuitry may be configured to generate the indicator of the error signaling window via a delayed early termination mode. The signaling circuitry may be configured to generate the indicator of the error signaling window by switching a first line of two lines after each of three or more symbol intervals while maintaining a second line of two lines of the serial bus in a first signaling state. A later or earlier transmission synchronization mode can be detected when the first line of two lines is switched after each of three or more symbol intervals while the second line of two lines of the serial bus remains in a second signaling state. In some examples, the signaling circuitry may be configured to transmit the indicator of the error signaling window at a pre-configured position or pre-configured time in the symbol sequence.

[0157] The processor-readable storage medium 2618 may include instructions to cause the processing circuitry 2602 to: encode data with transitions between symbol pairs in a symbol sequence, each symbol defining a signaling state of the serial bus; transmit the symbol sequence via the serial bus; transmit an indicator of an error signaling window in the signaling state of the two lines of the serial bus, the indicator of the error signaling window corresponding to a prohibited symbol combination or a delay in control signaling; and receive a signaling in the error signaling window indicating an error in the timing of the indicator of the error signaling window or an error in the symbol sequence. In some examples, the processor-readable storage medium 2618 may include instructions to cause the processing circuitry 2602 to terminate data transmission when an error signaling indicating an error is received in the error signaling window.

[0158] In some examples, the transmission device may use a phase differential encoder to encode the data, and circuitry that operates independently of the phase differential encoding may be used to generate an indicator for the error signaling window.

[0159] In some examples, the processor-readable storage medium 2618 may include instructions that cause the processing circuitry 2602 to generate an indicator of an error signaling window by switching a first line of two lines after each of three or more symbol intervals, while maintaining a second line of two lines of the serial bus in a first signaling state. A synchronization mode of later or earlier transmission can be detected when the first line of two lines is switched after each of three or more symbol intervals, while the second line of two lines of the serial bus remains in a second signaling state. In some examples, the processor-readable storage medium 2618 may include instructions that cause the processing circuitry 2602 to generate an indicator of an error signaling window in a delayed early termination mode. The transmission device may operate as a bus master or slave device.

[0160] It is understood that the specific order or hierarchy of steps in the disclosed process is an illustration of an exemplary method. It is understood that the specific order or hierarchy of steps in the process may be rearranged based on design preferences. Furthermore, some steps may be combined or omitted. The appended method requires that the elements of each step be presented in a sample order, but is not limited to the specific order or hierarchy presented.

[0161] The above description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but should be accorded the full scope consistent with the language of the claims, wherein, unless specifically stated otherwise, reference to a singular element does not mean “one and only one,” but rather “one or more.” Unless otherwise specifically stated, the term “some” means one or more. All structural and functional equivalents of elements known or to be known later by those skilled in the art throughout the various aspects described in this disclosure are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended as a donation to the public, whether or not such disclosure is expressly listed in the claims. Unless an element is explicitly stated using the phrase “means for,” it should not be interpreted as a means plus a function.

Claims

1. A method for receiving data at a device coupled to a serial bus, comprising: Receive a sequence of symbols, each symbol representing the signaling state of the serial bus; Decode the data based on the transitions between symbol pairs in the symbol sequence; When a first line of two lines of the serial bus is switched after each of three or more symbol intervals, while the second line of the two lines of the serial bus remains in a first signaling state, an indicator of an error signaling window in the signaling state of the two lines of the serial bus is detected, wherein the indicator of the error signaling window includes a prohibited symbol combination or a delay in control signaling. A synchronization mode is detected when the first line of the two lines of the serial bus is switched after each of three or more symbol intervals, while the second line of the two lines of the serial bus remains in the second signaling state. as well as When an error is detected during the timing of the indicator or the symbol sequence in the error signaling window, the error is signaled during the error signaling window.

2. The method of claim 1, wherein the error detected in the symbol sequence includes a parity error.

3. The method according to claim 1, further comprising: An error is detected when the indicator of the error signaling window begins at an unexpected time or at an unexpected position in the symbol sequence, wherein the device is pre-configured with an indication of the expected time of the error signaling window or the expected position in the symbol sequence.

4. The method according to claim 1, further comprising: The error is detected when the indicator in the error signaling window begins before the complete symbol sequence is received.

5. The method of claim 1, wherein the indicator of the error signaling window precedes the error signaling window by one or more symbol intervals.

6. The method according to claim 1, further comprising: The data is decoded using a phase difference decoder; as well as The error is detected using a detection circuit that operates independently of the phase differential decoder, either during the timing of the indicator in the error signaling window or in the symbol sequence.

7. The method of claim 1, wherein the device is configured to operate as a slave device, and wherein the transmission of data is terminated after signaling the error.

8. The method according to claim 1, further comprising: The device is operated as a bus master. as well as A transmission signaling mode is configured to terminate the transmission of data after signaling the error.

9. The method according to claim 1, further comprising: An HDR error signaling window indicator is detected when the high data rate HDR early termination mode is delayed.

10. A data communication device, comprising: A bus interface is configured to couple the data communication device to a serial bus; A phase differential decoder is configured to decode data based on transitions between symbol pairs in a sequence of symbols received from the serial bus, each symbol representing a signaling state of the serial bus; as well as The processor is configured as follows: When a first line of two lines of the serial bus is switched after each of three or more symbol intervals, while the second line of the two lines of the serial bus remains in a first signaling state, an indicator of an error signaling window in the signaling state of the two lines of the serial bus is detected, wherein the indicator of the error signaling window includes a prohibited symbol combination or a delay in control signaling. A synchronization mode is detected when the first line of the two lines of the serial bus is switched after each of three or more symbol intervals, while the second line of the two lines of the serial bus remains in the second signaling state. as well as When an error is detected during the timing of the indicator or the symbol sequence in the error signaling window, the error is signaled via the bus interface during the error signaling window.

11. The data communication apparatus of claim 10, wherein the error detected in the symbol sequence includes a parity check error.

12. The data communication apparatus according to claim 10, wherein the processor is further configured to: An error is detected when the indicator of the error signaling window begins at an unexpected time or at an unexpected position in the symbol sequence, wherein the data communication device is pre-configured with an indication of the expected time of the error signaling window or the expected position in the symbol sequence.

13. The data communication apparatus according to claim 10, wherein the processor is further configured to: The error is detected when the indicator in the error signaling window begins before the complete symbol sequence is received.

14. The data communication apparatus of claim 10, wherein the indicator of the error signaling window precedes the error signaling window by one or more symbol intervals.

15. The data communication apparatus according to claim 10, further comprising: The detection circuit is configured to detect the error independently of the phase differential decoder in the timing of the indicator or in the symbol sequence of the error signaling window.

16. The data communication apparatus according to claim 15, wherein the detection circuit is further configured to: An HDR error signaling window indicator is detected when the high data rate HDR early termination mode is delayed.

17. The data communication apparatus of claim 10, wherein the data communication apparatus is configured to operate as a slave device, and wherein the transmission of data is terminated after signaling the error.

18. The data communication apparatus of claim 10, wherein the processor is further configured to: The data communication device is operated as a bus master device; and A transmission signaling mode is configured to terminate the transmission of data after signaling the error.

19. A method for transferring data from a device coupled to a serial bus, comprising: The data is encoded by transitions between symbol pairs in a symbol sequence, each symbol defining the signaling state of the serial bus; The symbol sequence is transmitted via the serial bus; An indicator of an error signaling window in the signaling state of the two lines of the serial bus is transmitted by switching the first line of the two lines of the serial bus after each of three or more symbol intervals, while maintaining the second line of the two lines of the serial bus in a first signaling state, wherein when the synchronous mode is transmitted through the serial bus, the first line of the two lines of the serial bus is switched after each of three or more symbol intervals, while the second line of the two lines of the serial bus is maintained in a second signaling state, and wherein the indicator of the error signaling window includes a prohibited symbol combination or a delay in control signaling; Receive signaling in the error signaling window indicating an error in the timing of the indicator or an error in the symbol sequence of the error signaling window; as well as When a signal indicating the error is received in the error signaling window, the transmission of the data is terminated.

20. The method of claim 19, further comprising: The data is encoded using a phase differential encoder; as well as The indicator for the error signaling window is generated using circuitry that operates independently of the phase differential encoder.

21. The method of claim 19, further comprising: The indicator of the error signaling window is transmitted at a pre-configured time or at a pre-configured position in the symbol sequence.

22. The method of claim 19, further comprising: HDR error signaling window indicator is generated by delaying the high data rate HDR early termination mode.

23. A data communication device, comprising: A bus interface is configured to couple the data communication device to a serial bus; A phase differential encoder is configured to encode data in pairs of transitions between symbol pairs in a symbol sequence, each symbol defining the signaling state of the serial bus; as well as The processor is configured as follows: An indicator of an error signaling window in the signaling state of the two lines of the serial bus is transmitted by switching the first line of the two lines of the serial bus after each of three or more symbol intervals, while maintaining the second line of the two lines of the serial bus in a first signaling state, wherein when the synchronous mode is transmitted through the serial bus, the first line of the two lines of the serial bus is switched after each of three or more symbol intervals, while the second line of the two lines of the serial bus is maintained in a second signaling state, and wherein the indicator of the error signaling window includes a prohibited symbol combination or a delay in control signaling; Receive signaling in the error signaling window indicating an error in the timing of the indicator or an error in the symbol sequence of the error signaling window; as well as When a signal indicating the error is received in the error signaling window, the transmission of the data is terminated.

24. The data communication apparatus according to claim 23, further comprising: The signaling circuitry is configured to generate the indicator for the error signaling window independently of the phase differential encoder.

25. The data communication apparatus of claim 24, wherein the signaling circuit is further configured to: HDR error signaling window indicator is generated by delaying the high data rate HDR early termination mode.

26. The data communication apparatus of claim 24, wherein the signaling circuit is further configured to: The bus interface transmits the indicator of the error signaling window at a pre-configured time or at a pre-configured position in the symbol sequence.

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