A storage device and its manufacturing method, an electronic device

Abstract

This application discloses a memory device and its manufacturing method, as well as an electronic device. The memory device includes a substrate, a memory layer on the substrate, an isolation trench penetrating the memory layer, an insulating material filled in the isolation trench, and a conductor plug penetrating the insulating material longitudinally. The memory layer may include alternating layers of ferroelectric layers and multiple conductive layers. On the sidewall of the isolation trench, the ferroelectric layer has a protruding portion protruding from the conductive layer. The conductor plug contacts the protruding portion of the ferroelectric layer but is isolated from the conductive layer by the insulating material. In this way, the ferroelectric layer, the conductive layer in contact with the ferroelectric layer, and the conductor plug in contact with the ferroelectric layer can constitute a memory cell. The non-contacting conductive layer and conductor plug can serve as two electrodes. That is to say, in this application embodiment, the stacking of ferroelectric layers and conductive layers realizes the three-dimensionalization of the ferroelectric memory, improves the storage density of the device, reduces the etching difficulty, improves the etching accuracy and reliability, and improves the device performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a storage device and its manufacturing method, and an electronic device. Background Technology

[0002] In the era of big data, massive amounts of data are generated, transmitted, and processed every day. The huge data flow carries a lot of information needed for social development, bringing convenience to social development, but also placing higher demands on the processing capabilities of each link of the data, especially the performance requirements of its carrier - storage, which have reached unprecedented levels, such as extremely high storage density, extremely large transmission bandwidth, and extremely fast erase and write speeds.

[0003] Currently, different memory types exist to meet different needs, such as NAND type, especially 3D NAND FLASH, which provides storage capacity that increases exponentially in three dimensions; high bandwidth memory (HBM) solutions provide high transmission bandwidth; and dynamic random access memory (DRAM) and static random access memory (SRAM) provide extremely fast erase and write speeds. However, these devices all have their limitations in addition to their advantages.

[0004] In addition, memory made using the principle that the polarization direction of ferroelectric materials changes under the influence of an electric field is called ferroelectric random access memory (FRAM), or simply "ferroelectric memory." It has advantages such as high read / write speeds, low power consumption, and small area. The memory cells in ferroelectric memory can include ferroelectric field-effect transistors (FeFETs) based on a metal-ferroelectric-insulator-semiconductor (MFIS) structure, and ferroelectric diodes (Fe-diodes) based on a metal-ferroelectric-metal (MFM) structure. MFM structure memory cells have better durability than MFIS structure memory cells, and are therefore widely used in one-transistor-one-capacitor (1T-1C) architecture FRAMs.

[0005] However, ferroelectric memories are mostly two-dimensional structures. How to extend ferroelectric memories from two-dimensional to three-dimensional, thereby increasing the storage capacity of the memory device and further improving its performance, is an important research area in this field. Summary of the Invention

[0006] In view of this, embodiments of this application provide a storage device and its manufacturing method, as well as an electronic device, which extend ferroelectric memory to three dimensions, further improve the performance of the storage device, simplify the device manufacturing process, and reduce manufacturing costs.

[0007] A first aspect of this application provides a storage device, including a substrate, a storage layer on the substrate, an isolation trench penetrating the storage layer, an insulating material filled in the isolation trench, and a conductor plug penetrating the insulating material longitudinally. The storage layer includes alternating layers of ferroelectric layers and multiple conductive layers. On the sidewall of the isolation trench, the ferroelectric layer has a protruding portion protruding from the conductive layer. The conductor plug contacts the protruding portion of the ferroelectric layer but is isolated from the conductive layer by the insulating material. Thus, the ferroelectric layer, the conductive layer in contact with the ferroelectric layer, and the conductor plug in contact with the ferroelectric layer can constitute a storage cell, and the non-contacting conductive layer and conductor plug can serve as two separate storage cells. In other words, in this embodiment of the application, the ferroelectric memory is three-dimensionally formed by stacking ferroelectric and conductor layers, thereby increasing the storage density of the device. The isolation trench is relatively large and easier to etch than a deep hole. When the deep hole containing the conductor plug is formed, the etching target is the insulating material, thus avoiding the difficult-to-etch ferroelectric and conductor layers. Therefore, its etching precision is higher and the etching reliability is improved. At the same time, by setting the deep hole within the isolation trench, the device area is saved while ensuring the device function, thereby improving the device integration. Combined with the high speed and high bandwidth characteristics of the ferroelectric memory itself, the three-dimensional ferroelectric memory has superior performance.

[0008] In some possible implementations, the storage device further includes an insulating layer;

[0009] The insulating layer is disposed on the side surface of the ferroelectric layer facing the conductor layer, and the insulating layer protrudes from the conductor layer on the sidewall of the isolation trench.

[0010] In this embodiment, an insulating layer can be provided on one side surface of the ferroelectric layer to isolate different storage devices, thereby improving the control accuracy of the storage cell.

[0011] In some possible implementations, the insulating material or the insulating layer comprises at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, and aluminum oxide.

[0012] In this embodiment, the materials of the insulating material and the insulating layer can be defined to ensure good insulation.

[0013] In some possible implementations, the ferroelectric layer comprises at least one of the following materials: lithium niobate, blackened lithium niobate, doped lithium niobate, lithium tantalate, blackened lithium tantalate, doped lithium tantalate, bismuth ferrite, barium titanate, barium strontium titanate, and strontium titanate.

[0014] In this embodiment, the material of the ferroelectric layer can be defined to ensure good storage performance.

[0015] In some possible implementations, the material of the conductor layer or the conductor plug includes at least one of the following materials: titanium nitride, tungsten, nickel, platinum, titanium, tungsten nitride, ruthenium, ruthenium oxide, iridium, iridium oxide, tantalum nitride, cobalt, aluminum, copper, polycrystalline silicon, and metal silicides.

[0016] In this embodiment, the materials of the conductor layer and the conductor plug can be defined to ensure good conductivity.

[0017] A second aspect of this application provides a method for manufacturing a storage device, comprising:

[0018] Provide substrate;

[0019] A storage layer and an isolation trench are formed on the substrate; the storage layer comprises alternating layers of ferroelectric layers and multiple conductor layers, wherein the ferroelectric layers have protrusions protruding from the conductor layers on the sidewalls of the isolation trench;

[0020] The isolation trench is filled with insulating material;

[0021] The insulating material is etched to obtain a through hole that penetrates the insulating material longitudinally; the sidewall of the through hole includes the sidewall of the ferroelectric layer and the sidewall of the insulating material;

[0022] A conductor plug is formed by filling the through hole; the conductor plug contacts the protruding portion of the ferroelectric layer and is separated from the conductor layer by the insulating material.

[0023] In some possible implementations, a storage layer is formed on the substrate, and an isolation trench extends through the storage layer, including:

[0024] Multiple ferroelectric layers and multiple conductor layers are alternately formed on the substrate;

[0025] The ferroelectric layer and the conductor layer are etched to obtain a first longitudinal trench;

[0026] The conductor layer is partially etched laterally using the first trench so that the ferroelectric layer has a protruding portion protruding from the conductor layer on the sidewall of the first trench, thereby obtaining an isolation trench that penetrates the storage layer.

[0027] In some possible implementations, a storage layer is formed on the substrate, and an isolation trench extends through the storage layer, including:

[0028] Multiple ferroelectric layers and multiple sacrificial layers are alternately formed on the substrate;

[0029] The ferroelectric layer and the sacrificial layer are etched to obtain a longitudinal second trench;

[0030] The sacrificial layer is partially etched laterally using the second trench to obtain the first depression;

[0031] Conductive material is formed in the second trench and the first recess;

[0032] The ferroelectric layer and sacrificial layer between the second trench are etched to obtain the longitudinal third trench;

[0033] The third trench is used to perform lateral etching on the sacrificial layer to remove the sacrificial layer and obtain the second depression;

[0034] Conductive material is formed in the third trench and the second recess to form a conductor layer between the ferroelectric layers;

[0035] The conductor material in the second trench and the third trench is removed, and the conductor layer is partially etched laterally using the second trench and the third trench, so that the ferroelectric layer has a protruding portion protruding from the conductor layer on the sidewall of the second trench and the third trench, thereby obtaining an isolation trench that penetrates the storage layer.

[0036] In this embodiment, a ferroelectric layer and a sacrificial layer can be provided. After etching to form trenches, the sacrificial layer is replaced with a conductor layer, which can avoid the stress generated during conductor layer deposition, improve film quality, and improve device performance.

[0037] In some possible implementations, the storage layer further includes an insulating layer disposed on the ferroelectric layer's surface facing the conductor layer, which protrudes from the conductor layer on the sidewall of the isolation trench after the conductor layer has been partially etched laterally.

[0038] In some possible implementations, the insulating material or the insulating layer comprises at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, and aluminum oxide.

[0039] In some possible implementations, the ferroelectric layer comprises at least one of the following materials: lithium niobate, blackened lithium niobate, doped lithium niobate, lithium tantalate, blackened lithium tantalate, doped lithium tantalate, bismuth ferrite, barium titanate, barium strontium titanate, and strontium titanate.

[0040] In some possible implementations, the material of the conductor layer or the conductor plug includes at least one of the following materials: titanium nitride, tungsten, nickel, platinum, titanium, tungsten nitride, ruthenium, ruthenium oxide, iridium, iridium oxide, tantalum nitride, cobalt, aluminum, copper, polycrystalline silicon, and metal silicides.

[0041] A third aspect of this application provides an electronic device, including a circuit board and a storage device connected to the circuit board as described in the first aspect of this application.

[0042] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:

[0043] This application provides a storage device and its manufacturing method, as well as an electronic device. The storage device includes a substrate, a storage layer on the substrate, an isolation trench penetrating the storage layer, an insulating material filled in the isolation trench, and a conductor plug penetrating the insulating material longitudinally. The storage layer includes alternating layers of ferroelectric layers and multiple conductive layers. On the sidewall of the isolation trench, the ferroelectric layer has a protruding portion protruding from the conductive layer. The conductor plug contacts the protruding portion of the ferroelectric layer but is isolated from the conductive layer by the insulating material. Thus, the ferroelectric layer, the conductive layer in contact with the ferroelectric layer, and the conductor plug in contact with the ferroelectric layer can constitute a storage cell, while the non-contacting conductive layers and conductor plug can function as... With two electrodes, the ferroelectric memory in this embodiment is three-dimensionally constructed by stacking ferroelectric and conductor layers, thereby increasing the storage density of the device. The isolation trench is relatively large and easier to etch than a deep hole. The deep hole where the conductor plug is located is formed by etching an insulating material, thus avoiding the difficult-to-etch ferroelectric and conductor layers. Therefore, the etching precision is higher and the etching reliability is improved. At the same time, setting the deep hole within the isolation trench saves device area while ensuring device functionality and improving device integration. Combined with the high speed and high bandwidth characteristics of the ferroelectric memory itself, the three-dimensional ferroelectric memory has superior performance. Attached Figure Description

[0044] To clearly understand the specific embodiments of this application, the accompanying drawings used in describing the specific embodiments of this application will be briefly described below. Obviously, these drawings are only some embodiments of this application.

[0045] Figure 1 A three-dimensional structural schematic diagram of a storage device provided in an embodiment of this application;

[0046] Figure 2 for Figure 1A two-dimensional structural diagram of the storage device in the image;

[0047] Figure 3 A schematic diagram of an MFM structure provided in an embodiment of this application;

[0048] Figure 4 A flowchart illustrating a method for manufacturing a storage device according to an embodiment of this application;

[0049] Figures 5-16 This is a schematic diagram of the structure of the storage device in the manufacturing process according to an embodiment of this application. Detailed Implementation

[0050] This application provides a storage device and its manufacturing method, as well as an electronic device, which extends ferroelectric memory to three dimensions, increasing the storage capacity of the storage device while simplifying the device manufacturing process and reducing manufacturing costs.

[0051] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0052] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0053] In practice, memory devices can be fabricated by utilizing the principle that the polarization direction of ferroelectric materials changes under the influence of an electric field. Specifically, when the polarization direction of a ferroelectric material reverses, potential domain wall regions exist between the reversed and unreversed regions. When the polarization directions are opposite, the domain walls open, resulting in a conductive state (low-resistance state); when the polarization directions are the same, the domain walls close, resulting in an insulating state (high-resistance state). These high and low resistance states are used to represent the stored "0" and "1" states, respectively. For example, high resistance corresponds to "0" and low resistance corresponds to "1," or vice versa, thus forming a novel type of ferroelectric memory. This type of memory is called a ferroelectric memory, which has advantages such as fast read / write speeds, low power consumption, and small area.

[0054] However, ferroelectric memories are mostly two-dimensional structures. Expanding ferroelectric memories from two-dimensional to three-dimensional to increase storage capacity and further improve performance is an important research area in this field. In fact, increasing storage capacity, combined with the nanosecond duration of domain wall opening and closing and the parallel read / write characteristics inherent in the structure of ferroelectric memories, could potentially achieve high capacity, high speed, and high bandwidth simultaneously within a single memory architecture, while also reducing manufacturing costs. This would make ferroelectric memories a general-purpose memory, thus making ferroelectric memory research extremely valuable.

[0055] Currently, three-dimensional ferroelectric memories can be constructed by stacking multiple ferroelectric thin films layer by layer. Specifically, a single-layer ferroelectric thin film can be first deposited on a silicon substrate, and metal electrodes and leads can be placed at specific structural locations using microfabrication techniques to form a memory array based on a single-layer ferroelectric thin film. For example, a single-layer ferroelectric thin film memory array can be based on an MFM structure. Then, a second ferroelectric thin film is deposited on top, using the same processing method as the first layer, with the same metal electrodes and leads. This process allows for the deposition of ferroelectric thin films layer by layer, with metal electrodes and leads placed on each layer. Finally, the leads of each layer are interconnected using a specific method to form a three-dimensional structure. However, this method requires layer-by-layer processing and stacking, increasing the complexity and cost of the process and hindering the increase of storage capacity. Furthermore, during interlayer stacking, the memory cells and metal leads need to be aligned with nanometer-level precision, which poses a significant challenge to advanced processes. Especially when ferroelectric materials cannot be stacked using thin-film deposition, the alignment precision is far higher than the nanometer level, making the fabrication of multilayer structures extremely difficult.

[0056] Using existing 3D NAND flash memory models, multiple thin films, including sacrificial layers and ferroelectric material layers, can be stacked first. Through-holes are then etched into the sacrificial and ferroelectric materials, forming metal electrodes as bit lines (BLs). Spacer trenches are then etched into the sacrificial and ferroelectric material layers. These trenches are then used to process the sacrificial layer using special techniques, preventing complete consumption. The etching stop point is controlled by time, and the etched areas are filled with metal electrodes to form word lines (WLs), thus achieving a three-dimensional structure. In this three-dimensional structure, a ferroelectric material layer is formed between two metal electrodes, constituting an MFM structure. However, this method involves a one-time etching of the multilayer films, requiring high-steepness, high-aspect-ratio deep-hole etching. The etching performance of ferroelectric materials is not ideal, leading to poor device reliability. Furthermore, the isolation between the deep-hole electrodes and deep trenches results in low storage density, hindering the achievement of large-capacity storage.

[0057] Based on the above technical problems, embodiments of this application provide a storage device and its manufacturing method, as well as an electronic device. The storage device includes a substrate, a storage layer on the substrate, an isolation trench penetrating the storage layer, an insulating material filled in the isolation trench, and a conductor plug penetrating the insulating material longitudinally. The storage layer includes alternating layers of ferroelectric layers and multiple conductive layers. On the sidewall of the isolation trench, the ferroelectric layer has a protruding portion protruding from the conductive layer. The conductor plug contacts the protruding portion of the ferroelectric layer but is isolated from the conductive layer by the insulating material. In this way, the ferroelectric layer, the conductive layer in contact with the ferroelectric layer, and the conductor plug in contact with the ferroelectric layer can constitute a storage cell. The non-contacting conductive layers and conductor plugs... The body plug can serve as two electrodes. In other words, in this embodiment, the ferroelectric memory is three-dimensionally formed by stacking the ferroelectric layer and the conductor layer, thereby increasing the storage density of the device. The isolation trench is relatively large and easier to etch than a deep hole. When the deep hole containing the conductor plug is formed, the etching target is the insulating material, thus avoiding the difficult-to-etch ferroelectric layer and the conductor layer. Therefore, its etching precision is higher and the etching reliability is improved. At the same time, by setting the deep hole within the isolation trench, the device area is saved while ensuring the device function, thereby improving the device integration. Combined with the high speed and high bandwidth characteristics of the ferroelectric memory itself, the three-dimensional ferroelectric memory has superior performance.

[0058] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0059] refer to Figure 1 The image shown is a three-dimensional structural schematic diagram of a storage device provided in an embodiment of this application. (Refer to...) Figure 2 As shown, Figure 1A two-dimensional structural diagram of the storage device in the diagram, where 2A is... Figure 1 Top view of the storage device in the middle. Figure 2 B is Figure 1 A cross-sectional view of the storage device along the AA direction. The storage device includes a substrate 100, a storage layer on the substrate 100, an isolation trench penetrating the storage layer, an insulating material 113 in the isolation trench, and a conductor plug 114 penetrating the insulating material 113.

[0060] In this embodiment, the substrate 100 can be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Specifically, the substrate 100 can be a silicon wafer or a die with logic circuitry.

[0061] The storage layer comprises alternating layers of ferroelectric layers 112 and conductor layers 111. These layers are stacked vertically and extend horizontally. The number of ferroelectric layers 112 and conductor layers 111 can be determined based on actual storage requirements and fabrication processes. A greater number of ferroelectric layers 112 and conductor layers 111 results in a larger storage capacity. This embodiment uses three ferroelectric layers 112 and three conductor layers 111 as an example, with the conductor layer 111 as the bottom layer and the ferroelectric layer 112 as the top layer. However, in other embodiments, by changing the stacking order, the conductor layer 111 can also be located on the top layer.

[0062] The ferroelectric layer 112 is made of a material with ferroelectric properties, such as at least one of the following: lithium niobate (LiNbO3), blackened lithium niobate, doped lithium niobate, lead zirconium titanate (PbZrTiO3), lithium tantalate (LiTaO3), blackened lithium tantalate, doped lithium tantalate, bismuth ferrite (BiFeO3), barium titanate (BaTiO3), barium strontium titanate (SrBa2Ta2O9), strontium titanate (SrTiO), hafnium zirconate (HfZrO3), lanthanum hafnium zirconate (La-HfZrO3), etc. The dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), iron (Fe), thulium (Tm), erbium (Er), etc. The material of the conductor layer 111 is a material with electrical conductivity, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), iridium oxide (IrOx), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), metal silicides, etc.

[0063] The memory layer also includes isolation trenches that penetrate the memory layer. These trenches divide the memory layer laterally into multiple sections. Multiple isolation trenches can be arranged in parallel. The isolation trenches can penetrate at least to the bottom ferroelectric layer 112; for example, they can penetrate only to the bottom ferroelectric layer 112, or they can completely penetrate the memory layer to the substrate. The isolation trenches can divide the memory layer into multiple sections, each of which can form an independent memory cell. The isolation trenches can isolate different memory cells, facilitating the integration of memory devices.

[0064] The ferroelectric layer 112 on the sidewall of the isolation trench has a protruding portion that protrudes from the conductor layer 111, and the conductor layer 111 is recessed relative to the ferroelectric layer 112. The isolation trench is filled with insulating material 113, and the recess of the conductor layer 111 relative to the ferroelectric layer 112 is also filled with insulating material 113. Since the isolation trench penetrates the storage layer, its sidewalls include the sidewalls of the ferroelectric layer 112 and the sidewalls of the conductor layer 111. The insulating material 113 effectively fills the spaces between laterally adjacent ferroelectric layers 112 (which are the same ferroelectric layer 112 separated by the isolation trench) and between laterally adjacent conductor layers 111 (which are the same conductor layer 111 separated by the isolation trench), thereby isolating the same ferroelectric layer 112 and the same conductor layer 111. The lateral dimension of the insulating material 113 between laterally adjacent conductor layers 111 is larger than the lateral dimension of the insulating material 113 between laterally adjacent ferroelectric layers 112. The insulating material 113 includes at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, and aluminum oxide.

[0065] The isolation trench also includes a conductor plug 114 that extends longitudinally through the insulating material 113. The conductor plug 114 extends in the stacking direction of the storage layer and is arranged along the direction of the isolation trench, perpendicular to the arrangement direction of the isolation trench. The conductor plug 114 contacts the sidewall of the protruding portion of the ferroelectric layer 112 in the isolation trench. The conductor plug 114 and the conductor layer 111 can be separated by the insulating material 113. The insulating material 113 that separates the conductor plug 114 and the conductor layer 111 can be formed in the recess of the conductor layer 111 relative to the ferroelectric layer 112.

[0066] Specifically, the conductor plug 114 can contact at least one side of the ferroelectric layer 112, see reference. Figure 1As shown, the conductor plug 114 may contact only the ferroelectric layer 112 on its left, only the conductor layer 111 on its right, or both the ferroelectric layers 112 on its left and right simultaneously. That is, the lateral dimension of the conductor plug 114 may be less than or equal to the lateral distance between adjacent ferroelectric layers 112, and less than the lateral distance between adjacent conductor layers 111. In an ideal device, the conductor plug 114 contacts each ferroelectric layer 112 in the isolation trench but does not contact any conductor layer 111, ensuring the structural and functional integrity of each memory cell.

[0067] The shape of the transverse cross-section of the conductor plug 114 can be determined according to the actual situation, and it can be circular, elliptical, or polygonal, where the polygonal shape can be rectangular, triangular, etc. The material of the conductor plug 114 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), iridium oxide (IrOx), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), metal silicides, etc.

[0068] Based on the above discussion, the ferroelectric layer 112 extends laterally, with its sidewalls connected to a longitudinally extending conductor plug 114. A laterally extending conductor layer 111 is formed above and below it. The laterally extending conductor layer 111 and the longitudinally extending conductor plug 114 are isolated by an insulating material 113, which can serve as two electrodes. The insulating material 113 prevents short circuits. The ferroelectric layer 112, along with the conductor layer 111 and conductor plug 114 connected to it, constitute an MFM structure, which can function as a memory cell. Applying voltage to the conductor layer 111 and conductor plug 114 controls data writing and reading within the memory cell. The conductor layer 111 can serve as a word line, and the conductor plug 114 can serve as a bit line.

[0069] For details, please refer to Figure 3 As shown, Figure 3 This is a schematic diagram of an MFM structure provided in an embodiment of this application, wherein the initial spontaneous polarization direction of the ferroelectric layer 112 is to the right. When writing data to the memory cell, the voltage of the conductor layer 111 (grounded) can be made less than the voltage of the conductor plug 114 (Vdd), and the voltage difference between the two is greater than the coercive voltage of the ferroelectric layer 112. The coercive voltage of the ferroelectric layer 112 refers to the critical voltage that causes the polarization direction of the ferroelectric layer 112 to reverse. (Refer to...) Figure 3As shown in Figure A, the applied electric field direction is opposite to the initial spontaneous polarization direction of the ferroelectric layer 112, and the electric field is relatively large. The polarization direction of the ferroelectric layer 112 between the conductor layer 111 and the conductor plug 114 is reversed, forming a working module with a leftward polarization direction. The polarization direction at other locations of the ferroelectric layer 112 is not reversed, forming a reference module with a rightward polarization direction. At this time, there will be a potential domain wall region between the reversed and unreversed regions, roughly located at the position shown by the dashed line. When the polarization directions between the two are opposite, the domain wall opens, connecting the conductor layer 111 and the conductor plug 114, and has conductive properties. The conductor layer 111 and the conductor plug 114 are in a conductive state, i.e., a low-resistance state, which can be equivalent to writing "1". Alternatively, the voltage of the conductor layer 111 (Vdd) can be made greater than the voltage of the conductor plug 114 (grounded), and the reference... Figure 3 As shown in B, the direction of the electric field is the same as the initial spontaneous polarization direction of the ferroelectric layer 112. The ferroelectric layer 112 between the conductor layer 111 and the conductor plug 114 will not reverse. This is equivalent to the polarization direction of the working module and the reference module being the same. The domain walls are closed, which is an insulating state, i.e., a high-resistivity state, which is equivalent to writing "0".

[0070] When reading the data stored in the memory cell, the voltage applied across the memory cell is in the same direction as the initial spontaneous polarization of the ferroelectric layer 112, and its value can be less than the coercive voltage of the ferroelectric layer 112 and greater than the threshold voltage (Vth). At this time, the current value of the ferroelectric diode is read and the conduction direction or whether the ferroelectric diode is conducting is determined. For example, if it is conducting, the data stored in the memory cell is determined to be "1", and if it is not conducting, the data stored in the memory cell is determined to be "0".

[0071] The storage device in this embodiment may further include an insulating layer (not shown). The insulating layer can be used to isolate different storage cells, improving the control accuracy of the storage cells. The insulating layer can be disposed on the surface of the ferroelectric layer 112 facing the conductor layer 111. For example, the insulating layer can be disposed between the ferroelectric layer 112 and the conductor layer 111 above it, so that the ferroelectric layer 112 and the conductor layer 111 below it belong to the same storage cell. Alternatively, the insulating layer can be disposed between the ferroelectric layer 112 and the conductor layer 111 below it, so that the ferroelectric layer 112 and the conductor layer 111 above it belong to the same storage cell. The insulating layer cannot be disposed on multiple surfaces of the same ferroelectric layer simultaneously; for example, it cannot be disposed on both the upper and lower surfaces of the ferroelectric layer simultaneously, otherwise it will affect the contact between the ferroelectric layer 112 and the conductor layer 111 in the same storage cell, making the storage cell incomplete.

[0072] The insulating layer may protrude from the conductor layer 111 on the sidewall of the isolation trench; specifically, the insulating layer may be flush with the ferroelectric layer 112. Therefore, the material of the insulating layer is such that it is not removed during the etching of the conductor layer 111; for example, the wet etching selectivity ratio between the material of the conductor layer 111 and the material of the insulating layer is greater than 100:1. The material of the insulating layer may be at least one of the following: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, or aluminum oxide.

[0073] This application provides a storage device including a substrate, a storage layer on the substrate, an isolation trench penetrating the storage layer, an insulating material filled in the isolation trench, and a conductor plug penetrating the insulating material longitudinally. The storage layer includes alternating layers of ferroelectric layers and multiple conductive layers. On the sidewalls of the isolation trench, the ferroelectric layer has a protruding portion protruding from the conductive layer. The conductor plug contacts the protruding portion of the ferroelectric layer but is isolated from the conductive layer by the insulating material. Thus, the ferroelectric layer, the conductive layer in contact with the ferroelectric layer, and the conductor plug in contact with the ferroelectric layer can constitute a storage cell. The non-contacting conductive layer and conductor plug can serve as two electrodes. In other words, this embodiment achieves three-dimensional ferroelectric memory by stacking ferroelectric and conductor layers, increasing the device's storage density. The isolation trench is relatively large, making etching easier compared to deep holes. Since the deep holes containing the conductor plug are formed by etching insulating material, the difficult-to-etch ferroelectric and conductor layers are avoided, resulting in higher etching precision and improved reliability. Furthermore, placing the deep holes within the isolation trench saves device area while maintaining functionality, increasing device integration. Combined with the high speed and high bandwidth characteristics of the ferroelectric memory itself, the three-dimensional ferroelectric memory exhibits superior performance. In addition, the periodicity of the interlayer structure reduces the burden on the control end.

[0074] Based on the storage device provided in the embodiments of this application, the embodiments of this application also provide a method for manufacturing the storage device, referring to... Figure 4 The diagram shown is a flowchart of a method for manufacturing a storage device according to an embodiment of this application. Specifically, the method may include:

[0075] S101, providing substrate 100, reference Figure 5 and Figure 6 As shown.

[0076] In this embodiment, the substrate 100 can be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Specifically, the substrate 100 can be a silicon wafer or a die with logic circuitry.

[0077] S102, a memory layer and an isolation trench 202 penetrating the memory layer are formed on the substrate 100, with reference to... Figures 5-13 As shown.

[0078] The storage layer comprises alternating layers of ferroelectric layers 112 and conductor layers 111. These layers are stacked vertically and extend horizontally. The number of ferroelectric layers 112 and conductor layers 111 can be determined based on actual storage requirements and fabrication processes. A greater number of ferroelectric layers 112 and conductor layers 111 results in a larger storage capacity. The ferroelectric layer 112 is made of a material with ferroelectric properties, such as at least one of the following: lithium niobate (LiNbO3), blackened lithium niobate, doped lithium niobate, lead zirconium titanate (PbZrTiO3), lithium tantalate (LiTaO3), blackened lithium tantalate, doped lithium tantalate, bismuth ferrite (BiFeO3), barium titanate (BaTiO3), barium strontium titanate (SrBa2Ta2O9), strontium titanate (SrTiO), hafnium zirconate (HfZrO3), lanthanum hafnium zirconate (La-HfZrO3), etc. The dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), iron (Fe), thulium (Tm), erbium (Er), etc. The conductor layer 111 is made of a material with electrical conductivity, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), iridium oxide (IrOx), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), metal silicides, etc.

[0079] The memory layer also includes isolation trenches 202 that penetrate the memory layer. These isolation trenches 202 divide the memory layer laterally into multiple sections. Multiple isolation trenches 202 can be arranged in parallel. The isolation trenches 202 can penetrate at least to the bottommost ferroelectric layer 112; for example, they can penetrate only to the bottommost ferroelectric layer 112, or they can completely penetrate the memory layer to the substrate. The isolation trenches 202 can divide the memory layer into multiple sections, each of which can form an independent memory cell. The isolation trenches 202 can isolate different memory cells, facilitating the integration of memory devices. On the sidewalls of the isolation trenches 202, the ferroelectric layer 112 has protruding portions that protrude from the conductor layer 111, and the conductor layer 111 is recessed relative to the ferroelectric layer 112. Since the isolation trench 202 penetrates the storage layer, the sidewalls of the isolation trench 202 include the sidewalls of the ferroelectric layer 112 and the sidewalls of the conductor layer 111. Therefore, the lateral dimension of the isolation trench 202 between adjacent conductor layers 111 is greater than the lateral dimension between adjacent ferroelectric layers 112.

[0080] The storage layer may also include an insulating layer, which can be disposed on the surface of the ferroelectric layer 112 facing the conductor layer 111. For example, an insulating layer can be disposed between the ferroelectric layer 112 and the conductor layer 111 above it to isolate the ferroelectric layer 112 from the conductor layer 111 above it, or an insulating layer can be disposed between the ferroelectric layer 112 and the conductor layer 111 below it to isolate the ferroelectric layer 112 from the conductor layer 111 below it. The insulating layer cannot be disposed on multiple surfaces of the same ferroelectric layer 112 simultaneously; for example, it cannot be disposed on both the upper and lower surfaces of the ferroelectric layer, otherwise it will affect the contact between the ferroelectric layer 112 and the conductor layer 111 in the same storage cell, resulting in incomplete storage cell functionality. The material of the insulating layer is such that it is not removed when the conductor layer 111 is etched; for example, the wet etching selectivity ratio between the material of the conductor layer 111 and the material of the insulating layer is greater than 100:1. The insulating layer can be made of at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, or aluminum oxide.

[0081] In this embodiment of the application, the method of forming the storage layer and isolation trench 202 can specifically be as follows: alternatingly forming multiple ferroelectric layers 112 and multiple conductor layers 111 on the substrate 100, as shown in the reference. Figure 5 As shown, the first longitudinal trench 201 is obtained by etching the ferroelectric layer 112 and the conductor layer 111, with reference to... Figure 13 As shown, the conductor layer 111 is partially etched laterally using a first trench, so that the ferroelectric layer 112 has a protruding portion protruding from the conductor layer 111 on the sidewall of the first trench. The conductor layer 111 is recessed relative to the ferroelectric layer 112 on the sidewall of the first trench, thereby obtaining an isolation trench 202 that penetrates the storage layer. (Refer to...) Figure 14 As shown.

[0082] Specifically, alternating layers of ferroelectric layers 112 and conductor layers 111 can be formed using periodic thin-film formation processes. Ferroelectric layers 112 can be formed using bonding or thin-film growth processes, and conductor layers 111 can be formed using thin-film growth processes. Ferroelectric layers 112 and conductor layers 111 can also be formed using other processes. When the storage layer includes an insulating layer, insulating layers, ferroelectric layers 112, and conductor layers 111 can be formed alternately, or ferroelectric layers 112, insulating layers, and conductor layers 111 can be formed. Then, deep trench etching is performed on the ferroelectric layers 112 and conductor layers 111 to obtain a vertical first trench 201. Deep trench etching is less difficult than deep hole etching, and the etching depth can be at least through the bottommost ferroelectric layer 112. The etching method can be anisotropic dry etching, resulting in smooth sidewalls and a high steepness of the first trench 201. When an insulating layer is formed, it needs to be etched simultaneously when forming the first trench 201. Then, the conductor layer 111 can be etched laterally in the first trench 201. Lateral etching can remove part of the conductor layer 111, so that the ferroelectric layer 112 on the sidewall of the first trench has a protruding part that protrudes from the conductor layer 111. The conductor layer 111 is recessed relative to the ferroelectric layer 112 on the sidewall of the first trench. The lateral etching method can be wet chemical etching. For conductor layers 111 of different layers in the isolation trench 202, the lateral etching depth should be kept as consistent as possible. During lateral etching, the insulating layer can be etched without damaging it or with minimal damage.

[0083] In this embodiment, the method of forming the storage layer and isolation trench 202 can specifically be as follows: alternatingly forming a ferroelectric layer 112 and a sacrificial layer 110 on the substrate 100, as shown in the reference. Figure 6 As shown, the ferroelectric layer 112 and the sacrificial layer 110 are etched and filled, thereby replacing the sacrificial layer 110 with the conductor layer 111, as shown in the reference. Figure 12 As shown, an isolation trench 202 is then formed penetrating the conductor layer 111 and the ferroelectric layer 112, as referenced. Figure 14 As shown.

[0084] Specifically, alternating layers of ferroelectric layers 112 and sacrificial layers 110 can be formed using periodic thin-film formation processes. Ferroelectric layers 112 can be formed using bonding or thin-film growth processes, and sacrificial layers 110 can also be formed using bonding or thin-film growth processes. Ferroelectric layers 112 and sacrificial layers 110 can also be formed using other processes. The sacrificial layer 110 is located at the position of the subsequent conductor layer 111, occupying space for the conductor layer 111. The sacrificial layer 110 is simpler to form and less difficult to etch than the conductor layer 111, facilitating device fabrication and subsequent etching. When the storage layer includes an insulating layer, insulating layers 112 and sacrificial layers 110 can be formed alternately, or ferroelectric layers 112, insulating layers, and sacrificial layers 110 can be formed. Insulating layers cannot be simultaneously disposed on multiple surfaces of the same ferroelectric layer 112; for example, they cannot be simultaneously disposed on the upper and lower surfaces of the ferroelectric layer. The material properties of the sacrificial layer 110 are such that it can be removed without causing damage to the ferroelectric layer 112 and the insulating layer during the removal process. For example, the wet etching ratio of the sacrificial layer 110 and the ferroelectric layer 112 is greater than 100:1. The material of the sacrificial layer 110 may include at least one of the following materials: silicon dioxide, silicon nitride, polysilicon, aluminum oxide, titanium oxide, hafnium oxide, etc.

[0085] Then, the ferroelectric layer 112 and the sacrificial layer 110 can be etched to obtain the longitudinal second trench 204. The etching difficulty of deep trenches is less than that of deep hole etching. The etching depth can be at least through the bottom ferroelectric layer 112. The etching method can be anisotropic dry etching, so that the sidewalls of the second trench 204 are smooth and have a high steepness. The distance between the second trenches 204 can be twice the distance between the first trenches 201. In this way, the space for a potential third trench 205 (shown by dashed lines, the third trench has not yet been formed at this time) is reserved between the second trenches 204. When an insulating layer is formed, the insulating layer needs to be etched together when the second trench 204 is formed.

[0086] Then, the sacrificial layer 110 can be partially etched laterally using the second trench 204 to obtain the first depression. The second trench 204 after lateral etching is designated as trench 206. (Refer to...) Figure 8 As shown, conductive material 115 is formed in the second trench 204 and the first recess, reference Figure 9As shown. Lateral etching of the sacrificial layer 110 can be performed using wet chemical etching. The etching of the sacrificial layer 110 is partial, allowing the remaining sacrificial layer 110 to support the ferroelectric layer 112. During lateral etching, the insulating layer may be undamaged or only minimally damaged. The lateral etching depth of the sacrificial layer 110 can vary at different depths in the second trench 204; for example, the lower parts of the same sacrificial layer 110 may be etched more deeply. Conductor material 115 is formed in the second trench 204 and the first recess using thin film growth methods, such as deposition processes. Afterwards, a planarization process can be used to remove the conductor material outside the second trench. The conductor material 115 fills the second trench 204 and the first recess, helping to alleviate the stress between the conductor material 115 and the ferroelectric layer 112, resulting in higher film quality compared to forming the conductor material directly on the ferroelectric layer 112. At this point, within the original horizontal plane where the sacrificial layer 110 was located, part of it is the sacrificial layer 110, and part is replaced by the conductor material 115.

[0087] Then, the ferroelectric layer 112 and sacrificial layer 110 between the second trench 204 can be etched to obtain the vertical third trench 206. The third trench is formed at the location of the potential third trench 205, with reference to... Figure 10 As shown. The etching of the third trench 206 is deep trench etching, which is less difficult than deep hole etching. The etching depth can be at least through the bottom ferroelectric layer 112. The etching method can be anisotropic dry etching, resulting in smooth sidewalls and high steepness of the third trench 206. The depth of the third trench 206 can be the same as the depth of the second trench 204. When an insulating layer is formed, the insulating layer needs to be etched together when forming the third trench 206. The distance between the third trenches 206 can be twice the distance between the first trenches 201, so that the second trench 204 and the third trench 206 can form the first trench 201.

[0088] Then, the sacrificial layer 110 can be laterally etched using the third trench 206 to remove the sacrificial layer 110 and obtain the second depression. The third trench after lateral etching can be represented as trench 207. (Refer to...) Figure 11 As shown, conductive material is formed in the third trench 206 and the second recess. The conductive materials formed in the second trench 204, the first recess, the third trench 206, and the second recess are interconnected to form a conductive layer 111 between the ferroelectric layers 112. (Refer to...) Figure 12As shown. Lateral etching of the sacrificial layer 110 can be performed using wet chemical etching. The etching of the sacrificial layer 110 is complete, allowing the conductive material to support the ferroelectric layer 112. During lateral etching, the insulating layer may be undamaged or only minimally damaged. The lateral etching depth of the sacrificial layer 110 can vary at different depths in the third trench 206. Conductive material is formed in the third trench 206 and the second recess using thin film growth methods, such as deposition processes. Subsequently, a planarization process can be used to remove the conductive material outside the third trench 206. The conductive material fills the third trench 206 and the second recess, helping to alleviate stress between the conductive material and the ferroelectric layer 112, resulting in higher film quality compared to directly forming the conductive material on the ferroelectric layer 112. At this point, the horizontal plane where the original sacrificial layer 110 was located has been completely replaced by conductive material.

[0089] Then, deep trench etching can be performed at the locations of the second trench 204 and the third trench 206 to remove the conductor material in the second trench 204 and the third trench 206. The combination of the second trench 204 and the third trench 206 is consistent with the number, size, and arrangement of the first trench 201, and their combination constitutes the first trench 201. (Refer to...) Figure 13 As shown, the depth of the deep trench etching can be the same as the depth of the second trench 204 and the third trench 206, or at least penetrate the bottom ferroelectric layer 112. Subsequently, the conductor layer 111 can be laterally etched in the second trench 204 and the third trench 206. Lateral etching can remove a portion of the conductor layer 111, causing the ferroelectric layer 112 on the sidewalls of the second trench 204 and the third trench 206 to have protruding portions protruding from the conductor layer 111. The conductor layer 111 is recessed relative to the ferroelectric layer 112 on the sidewalls of the second trench 204 and the third trench 206, thereby obtaining an isolation trench 202 penetrating the memory layer. (Refer to...) Figure 14 As shown, the lateral etching method can be wet chemical etching. For the conductor layers 111 of different layers in the second trench 204 and the third trench 206, the lateral etching depth should be kept as consistent as possible. During lateral etching, the insulating layer can be undisturbed or only slightly damaged.

[0090] S103, fill the isolation trench 202 with insulating material 113, and etch the insulating material 113 to obtain a through hole 203 penetrating the insulating material 113, reference. Figure 15 and Figure 16 As shown.

[0091] Insulating material 113 can be filled into the isolation trench 202, see reference. Figure 15As shown, the insulating material 113 can be filled using deposition or other thin film growth processes, and then the insulating material 113 outside the isolation trench 202 can be removed using a planarization process. The sidewalls of the isolation trench 202 include the sidewalls of the ferroelectric layer 112 and the sidewalls of the conductor layer 111. The insulating material 113 is actually filled between laterally adjacent ferroelectric layers 112 and between laterally adjacent conductor layers 111, thereby isolating the ferroelectric layers 112 and conductor layers 111 of the same layer. The lateral dimension of the insulating material 113 between laterally adjacent conductor layers 111 is larger than the lateral dimension of the insulating material 113 between laterally adjacent ferroelectric layers 112. The insulating material 113 includes at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, and aluminum oxide.

[0092] After filling the isolation trench 202 with insulating material 113, the insulating material 113 can be etched to obtain a through-hole (Via) 203 that longitudinally penetrates the insulating material 113, as shown in the reference. Figure 16 As shown, the etching target of via 203 is the insulating material 113. Compared with etching the ferroelectric layer 112 in the prior art, this reduces the etching difficulty, improves the etching accuracy, simplifies the process, and improves device reliability. The sidewalls of via 203 penetrating the insulating material 113 are the ferroelectric layer 112 and the insulating material 113. That is, via 203 exposes the sidewalls of the ferroelectric layer 112 but not the sidewalls of the conductor layer 111. Via 203 can expose at least one sidewall of the ferroelectric layer 112, see reference. Figure 1 As shown, via 203 may expose only the sidewall of the ferroelectric layer 112 on its left side, only the sidewall of the ferroelectric layer 112 on its right side, or both the sidewalls of the ferroelectric layer 112 on its left and right sides simultaneously. In an ideal device, via 203 exposes the sidewall of each ferroelectric layer 112 without exposing the sidewall of any conductor layer 111, thus ensuring the structural and functional integrity of each memory cell.

[0093] The shape of the transverse cross-section of the through-hole 203 can be determined according to the actual situation. It can be circular, elliptical, or polygonal, where the polygonal shape can be rectangular, triangular, etc. The etching depth of the through-hole 203 can be the same as or different from the depth of the isolation trench 202. The through-hole 203 must penetrate at least the bottom ferroelectric layer 112.

[0094] S104, a conductor plug 114 is formed by filling the through hole 203, reference. Figure 2 As shown in B.

[0095] The via 203 is filled with a conductor plug 114. The filling method can be a thin film growth process, such as a deposition process. The material of the conductor plug 114 is a material with conductive properties, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), iridium oxide (IrOx), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polycrystalline silicon (Si), metal silicides, etc.

[0096] The conductor plug 114 extends in the stacking direction of the storage layers. The conductor plug 114 can contact the sidewall of the ferroelectric layer 112 in the isolation trench 202. The conductor plug 114 and the conductor layer 111 can be separated by an insulating material 113. The insulating material 113 separating the conductor plug 114 and the conductor layer 111 can be formed in the recess of the conductor layer 111 relative to the ferroelectric layer 112. That is, the lateral dimension of the conductor plug 114 can be less than or equal to the lateral distance between adjacent ferroelectric layers 112, and less than the lateral distance between adjacent conductor layers 111. The shape of the lateral cross-section of the conductor plug 114 can be circular, elliptical, or polygonal, where the polygonal shape can be rectangular, triangular, etc.

[0097] Based on the above discussion, the ferroelectric layer 112 extends laterally, with its sidewalls connected to a longitudinally extending conductor plug 114. A laterally extending conductor layer 111 is formed above and below it. The laterally extending conductor layer 111 and the longitudinally extending conductor plug 114 are isolated by an insulating material 113, which can serve as two electrodes. The insulating material 113 prevents short circuits. The ferroelectric layer 112, along with the conductor layer 111 and conductor plug 114 connected to it, constitute an MFM structure, which can function as a memory cell. Applying voltage to the conductor layer 111 and conductor plug 114 controls data writing and reading within the memory cell. The conductor layer 111 can serve as a word line, and the conductor plug 114 can serve as a bit line.

[0098] This application provides a method for manufacturing a memory device, including providing a substrate, forming a memory layer on the substrate, and an isolation trench penetrating the memory layer, filling the isolation trench with an insulating material, etching the insulating material to obtain through-holes penetrating the insulating material, and filling the through-holes with conductor plugs. The memory layer includes alternating layers of multiple ferroelectric layers and multiple conductive layers. On the sidewalls of the isolation trench, the ferroelectric layer has protruding portions protruding from the conductive layers. The conductor plugs contact the protruding portions of the ferroelectric layer but are isolated from the conductive layers by the insulating material. In this way, the ferroelectric layer, the conductive layers in contact with the ferroelectric layer, and the conductor plugs in contact with the ferroelectric layer can constitute a memory cell, while the non-contacting conductive layers... The conductor plug can serve as two electrodes. In other words, in this embodiment, the ferroelectric memory is three-dimensionally formed by stacking the ferroelectric layer and the conductor layer, thereby increasing the storage density of the device. The isolation trench is relatively large and easier to etch than a deep hole. When the deep hole containing the conductor plug is formed, the etching target is an insulating material, thus avoiding the difficult-to-etch ferroelectric layer and the conductor layer. Therefore, its etching precision is higher and the etching reliability is improved. At the same time, setting the deep hole within the isolation trench saves device area and improves device integration while ensuring device functionality. Combined with the high speed and high bandwidth characteristics of the ferroelectric memory itself, the three-dimensional ferroelectric memory has superior performance.

[0099] Based on this, this application also provides an electronic device, which includes a circuit board and a storage device connected to the circuit board. The storage device can be any of the storage devices described above. The circuit board can be a printed circuit board (PCB), or a flexible printed circuit board (FPC), etc. This embodiment does not limit the type of circuit board. Optionally, the electronic device can be different types of user equipment or terminal equipment such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices; the electronic device can also be network equipment such as base stations.

[0100] Optionally, the electronic device further includes a packaging substrate, which is fixed to a printed circuit board (PCB) by solder balls, and the storage device is fixed to the packaging substrate by solder balls.

[0101] In another aspect of this application, a non-transitory computer-readable storage medium for use with a computer having software for creating integrated circuits is also provided. The computer-readable storage medium stores one or more computer-readable data structures having photomask data for manufacturing the integrated circuit provided in any of the above-provided figures.

[0102] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the structural embodiments, so they are described more simply; relevant parts can be referred to the descriptions of the structural embodiments.

[0103] The above describes the specific implementation of this application. It should be understood that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A storage device, characterized in that, include: Substrate; Storage layer located on the substrate; The storage layer comprises alternating layers of ferroelectric layers and multiple layers of conductor layers; Isolation trenches penetrating the storage layer; The ferroelectric layer on the sidewall of the isolation trench has a protruding portion that protrudes from the conductor layer, and the isolation trench is filled with insulating material; A conductor plug extends longitudinally through the insulating material; the conductor plug contacts the protruding portion of the ferroelectric layer and is separated from the conductor layer by the insulating material.

2. The storage device according to claim 1, characterized in that, It also includes an insulating layer; The insulating layer is disposed on the side surface of the ferroelectric layer facing the conductor layer, and the insulating layer protrudes from the conductor layer on the sidewall of the isolation trench.

3. The storage device according to claim 2, characterized in that, The insulating material or the insulating layer comprises at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, and aluminum oxide.

4. The storage device according to any one of claims 1-3, characterized in that, The ferroelectric layer includes at least one of the following materials: lithium niobate, blackened lithium niobate, doped lithium niobate, lithium tantalate, blackened lithium tantalate, doped lithium tantalate, bismuth ferrite, barium titanate, barium strontium titanate, and strontium titanate.

5. The storage device according to any one of claims 1-3, characterized in that, The material of the conductor layer or the conductor plug includes at least one of the following materials: titanium nitride, tungsten, nickel, platinum, titanium, tungsten nitride, ruthenium, ruthenium oxide, iridium, iridium oxide, tantalum nitride, cobalt, aluminum, copper, polycrystalline silicon, and metal silicides.

6. A method for manufacturing a storage device, characterized in that, include: Provide substrate; A storage layer and an isolation trench extending through the storage layer are formed on the substrate; The storage layer comprises alternating layers of ferroelectric layers and multiple conductor layers, wherein the ferroelectric layers have protruding portions protruding from the conductor layers on the sidewalls of the isolation trench; The isolation trench is filled with insulating material; The insulating material is etched to obtain a through hole that penetrates the insulating material longitudinally; the sidewall of the through hole includes the sidewall of the ferroelectric layer and the sidewall of the insulating material; A conductor plug is formed by filling the through hole; the conductor plug contacts the protruding portion of the ferroelectric layer and is separated from the conductor layer by the insulating material.

7. The method according to claim 6, characterized in that, A storage layer and an isolation trench extending through the storage layer are formed on the substrate, including: Multiple ferroelectric layers and multiple conductor layers are alternately formed on the substrate; The ferroelectric layer and the conductor layer are etched to obtain a first longitudinal trench; The conductor layer is partially etched laterally using the first trench so that the ferroelectric layer has a protruding portion protruding from the conductor layer on the sidewall of the first trench, thereby obtaining an isolation trench that penetrates the storage layer.

8. The method according to claim 6, characterized in that, A storage layer and an isolation trench extending through the storage layer are formed on the substrate, including: Multiple ferroelectric layers and multiple sacrificial layers are alternately formed on the substrate; The ferroelectric layer and the sacrificial layer are etched to obtain a longitudinal second trench; The sacrificial layer is partially etched laterally using the second trench to obtain the first depression; Conductive material is formed in the second trench and the first recess; The ferroelectric layer and sacrificial layer between the second trench are etched to obtain the vertical third trench; The third trench is used to perform lateral etching on the sacrificial layer to remove the sacrificial layer and obtain the second depression; Conductive material is formed in the third trench and the second recess to form a conductor layer between the ferroelectric layers; The conductor material in the second trench and the third trench is removed, and the conductor layer is partially etched laterally using the second trench and the third trench, so that the ferroelectric layer has a protruding portion protruding from the conductor layer on the sidewall of the second trench and the third trench, thereby obtaining an isolation trench that penetrates the storage layer.

9. The method according to any one of claims 6-8, characterized in that, The storage layer further includes an insulating layer disposed on the side surface of the ferroelectric layer facing the conductor layer. After the conductor layer is partially etched laterally, the insulating layer protrudes from the conductor layer on the sidewall of the isolation trench.

10. The method according to claim 9, characterized in that, The insulating material or the insulating layer comprises at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, and aluminum oxide.

11. The method according to any one of claims 6-8, characterized in that, The ferroelectric layer includes at least one of the following materials: lithium niobate, blackened lithium niobate, doped lithium niobate, lithium tantalate, blackened lithium tantalate, doped lithium tantalate, bismuth ferrite, barium titanate, barium strontium titanate, and strontium titanate.

12. The method according to any one of claims 6-8, characterized in that, The material of the conductor layer or the conductor plug includes at least one of the following materials: titanium nitride, tungsten, nickel, platinum, titanium, tungsten nitride, ruthenium, ruthenium oxide, iridium, iridium oxide, tantalum nitride, cobalt, aluminum, copper, polycrystalline silicon, and metal silicides.

13. An electronic device comprising a circuit board and a storage device as described in any one of claims 1-5 connected to said circuit board.

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