A chip failure screening method and device

Abstract

This invention discloses a method and apparatus for screening chip failures. The method includes: applying a read voltage to a target chip at a preset temperature and obtaining the read current value of the target chip under the read voltage, wherein the read voltage is within the operating voltage range of the target chip; adjusting the default reference current value of the target chip to a preset reference current value, wherein the preset reference current value is greater than the default reference current value; comparing the read current value with the preset reference current value; when the read current value is not less than the preset reference current value, the target chip is identified as a high-quality chip; when the read current value is less than the preset reference current value, the target chip is identified as a non-high-quality chip. This invention effectively ensures product quality by screening chips with high-temperature anomalies under low-pressure, high-temperature testing conditions by increasing the reference current.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and apparatus for screening chip failures. Background Technology

[0002] With advancements in manufacturing processes and reductions in costs, chips are being used more and more widely, leading to increasingly stringent requirements for their operating environment, especially high-temperature environments. To ensure chips can operate in high-temperature environments, CP (wafer testing) involves actual high-temperature measurements to screen for chips exhibiting high-temperature anomalies. However, some chips can operate continuously at low voltage and high temperature for an extended period before exhibiting anomalies. To screen for these defective products, a high-temperature environment needs to be created, increasing testing costs and potentially resulting in the rejection of many chips. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a method and apparatus for screening flash memory failures.

[0004] Specifically, the technical solution of the present invention is as follows:

[0005] On one hand, the present invention provides a method for screening chip failures, comprising:

[0006] A read voltage is applied to the target chip at a preset temperature, and the read current value of the target chip under the read voltage is obtained, wherein the read voltage is within the operating voltage range of the target chip;

[0007] The default reference current value of the target chip is adjusted to a preset reference current value, wherein the preset reference current value is greater than the default reference current value;

[0008] Compare the readout current value with the preset reference current value;

[0009] When the readout current value is not less than the preset reference current value, the target chip is determined to be of superior quality;

[0010] When the readout current value is less than the preset reference current value, the target chip is determined to be a non-premium product.

[0011] In some implementations, after determining the target chip as non-premium when the readout current value is less than the preset reference current value, the following steps are taken:

[0012] The readout current of the non-premium product is compared with the default reference current value;

[0013] When the read current value exceeds the default reference current value, the non-superior product is determined to be a qualified product;

[0014] When the read current value does not exceed the default reference current value, the non-superior product is identified as a defective product.

[0015] In some implementations, it also includes:

[0016] The qualified or superior products are subjected to reliability testing, and the qualified or superior products that pass the reliability test are determined to be valid chips; the reliability test includes baking test and / or low temperature test.

[0017] In some embodiments, before applying a read voltage to the target chip at a preset temperature and obtaining the read current value of the target chip at the read voltage, the process includes:

[0018] Perform a room temperature test on the chip under test, and identify the chip under test that passes the room temperature test as the target chip.

[0019] On the other hand, the present invention provides a chip failure screening device, comprising:

[0020] An acquisition module is used to apply a read voltage to a target chip at a preset temperature and acquire the read current value of the target chip under the read voltage, wherein the read voltage is within the operating voltage range of the target chip;

[0021] An adjustment module is used to adjust the default reference current value of the target chip to a preset reference current value, wherein the preset reference current value is greater than the default reference current value;

[0022] The first comparison module is used to compare the read current value with the preset reference current value;

[0023] The first determining module is used to determine the target chip as a superior product when the read current value is not less than the preset reference current value;

[0024] The second determining module is used to determine the target chip as a non-premium product when the read current value is less than the preset reference current value.

[0025] In some implementations, it also includes:

[0026] The second comparison module is used to compare the readout current of the non-premium product with the default reference current value.

[0027] The third determining module is used to determine the non-superior product as a qualified product when the read current value exceeds the default reference current value;

[0028] The fourth determining module is used to determine the non-superior product as a defective product when the read current value does not exceed the default reference current value.

[0029] In some implementations, it also includes:

[0030] A reliability testing module is used to perform reliability testing on the qualified or superior products, and to determine the qualified or superior products that pass the reliability test as valid chips; the reliability test includes baking test and / or low temperature test.

[0031] In some implementations, it also includes:

[0032] The room temperature testing module is used to perform room temperature testing on the chip under test, and to identify the chip under test that passes the room temperature test as the target chip.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows: by increasing the default reference current of the chip, the test environment of low voltage, high temperature and long-term use is equivalent, thereby screening out chips that are prone to failure in this environment, ensuring the high temperature application of the chip and the quality of the product, and also effectively saving costs, while avoiding the mis-killing caused by high temperature environment. Attached Figure Description

[0034] The preferred embodiments will now be described in a clear and easy-to-understand manner, in conjunction with the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of the present invention.

[0035] Figure 1 This is a flowchart of an embodiment of the chip failure screening method of the present invention;

[0036] Figure 2 This is a schematic diagram of the chip reading "1" under different voltages;

[0037] Figure 3 This is a flowchart of another embodiment of the chip failure screening method of the present invention;

[0038] Figure 4 This is a schematic diagram of one embodiment of the chip failure screening device of the present invention.

[0039] Explanation of icon numbers:

[0040] Acquisition module 10, adjustment module 20, first comparison module 30, first determination module 40, second determination module 50. Detailed Implementation

[0041] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0042] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or sets.

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0044] To keep the drawings concise, each figure only schematically shows the parts relevant to the invention, and these do not represent the actual structure of the product. Furthermore, to facilitate understanding, in some figures, only one of components with the same structure or function is schematically depicted, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."

[0045] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0046] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0047] To ensure the proper functioning of chips in high-temperature environments, chip probing (CP) performs high-temperature testing. However, some chips can operate continuously at low voltage and high temperature for an extended period before exhibiting abnormalities. Since creating such high-temperature environments is extremely costly and can easily lead to the overkill of many chips, CP needs to provide an effective and mass-production-compliant screening solution for chips that fail due to low voltage and high temperature. Simultaneously, because low voltage and high temperature environments can affect chip readability, resulting in a poor customer experience, a low-cost and effective CP screening solution needs to be developed to minimize product failure rates, improve product quality, and control costs.

[0048] The present invention will be specifically described below using NorFlash chips as an example. However, it should be noted that the chip failure screening method and apparatus provided by the present invention can be applied not only to NorFlash chips but also to other chips.

[0049] One embodiment of the present invention is shown in the accompanying drawings. Figure 1 A method for screening chip failures, comprising:

[0050] S100 applies a read voltage to the target chip at a preset temperature and obtains the read current value of the target chip at the read voltage, with the read voltage being within the chip's operating voltage range.

[0051] Specifically, the preset temperature is typically 85℃, i.e., a high-temperature environment. In this high-temperature environment, a read voltage is applied to the target chip, and the corresponding read current value at that voltage is obtained. The read voltage is selected from the target chip's operating voltage range, typically 1.8V-3.6V; during testing, the read voltage is generally set to 1.8V.

[0052] NorFlash chips primarily represent stored data by storing "0" and "1". "0" and "1" are distinguished based on the reference current (small current represents '0', large current represents '1'). By reading the voltage value, the depth of '0' and '1' can be determined (i.e., the greater the distance from the reference current, the better the chip's performance in reading '0' or '1').

[0053] Refer to the attached diagram in the instruction manual for a schematic diagram of the chip reading "1" at different voltages. Figure 2 VTE is the threshold value, and a more negative VTE value is better. The farther VTE is from the coordinate axis, the deeper the data is written, the easier it is to retain the data, and the easier it is to read the data correctly. Compared with the reading voltage of 3.6V, at 1.8V, the distance between VTE and the coordinate axis becomes shorter, that is, closer to the x-axis. At this time, the data is more likely to be read incorrectly. In other words, the closer the data is to the x-axis, the more likely it is to be read incorrectly, and the farther it is from the x-axis, the easier it is to read correctly.

[0054] For example, assuming the default reference current of the target chip is 4mA, if a voltage of 1.8V is applied to the chip, the current value read at 1.8V is 5mA. This current value is close to the default reference current value, which may cause read failure. If a voltage of 3.6V is applied to the chip, the current value read at 3.6V is 8mA. The difference between 4mA and 3.6V is large, so it is considered easy to read correctly.

[0055] S101 adjusts the default reference current value of the target chip to a preset reference current value, which is greater than the default reference current value.

[0056] Specifically, when a chip performs a read operation, it typically compares the chip's default reference current with the read current to represent the stored data. When the read current is greater than the default reference current, it indicates that the stored data is "1", and when the read current of the storage cell is less than the default reference current, it indicates that the stored data is "0".

[0057] Generally, the default reference current is assumed to be 3mA, and the large current is usually 5-8mA, because the status is more obvious when it is greater than 5mA, and it is easier to read "1" correctly. If the current is read as 3.5mA, the data can also be read correctly, but it is easier to make mistakes than 5mA, because it is larger than the default reference current, but not enough to make a clear difference.

[0058] Therefore, adjusting the default reference current value will worsen the chip's ability to read "1" when the default reference current value increases, making it more prone to reading "1" failures. This can help screen out chips that may fail when used for a long time under low temperature and high pressure conditions.

[0059] S102 compares the read current value with the preset reference current value.

[0060] When the read current value is not less than the preset reference current value, S103 determines the target chip as a superior product.

[0061] When the read current value is less than the preset reference current value, S104 determines the target chip as a non-premium product.

[0062] In this embodiment, a certain voltage is applied to the target chip at a preset temperature, the current read from the chip at that voltage is obtained, and the default reference current value of the target chip is adjusted to simulate the chip's long-term use under high temperature and low voltage conditions, thereby enabling the selection of superior products.

[0063] In one embodiment, refer to the accompanying drawings. Figure 3 A method for screening chip failures, comprising:

[0064] S200 applies a read voltage to the target chip at a preset temperature and obtains the read current value of the target chip at the read voltage, with the read voltage located within the chip's operating voltage range.

[0065] S201 adjusts the default reference current value of the target chip to a preset reference current value, which is greater than the default reference current value.

[0066] Specifically, the reference current is divided into different levels, with a default reference current value corresponding to a default level. By adjusting the level, the reference current can be increased to reach the preset reference current value. For example, if the reference current value is 3mA and the preset reference current value is 4mA, assuming that each level increases the current value by 0.1mA, then to adjust from 3mA to 4mA, you would directly adjust 10 levels to increase the default reference current value to the preset reference current value. It should be noted that adjusting the reference current level here is only a temporary adjustment for screening purposes.

[0067] S202 compares the read current value with the preset reference current value to determine whether the read current value is less than the preset reference current value. If the determination is no, the target chip is determined to be a superior product and step S204 is executed; otherwise, the target chip is determined to be a non-superior product.

[0068] S203 compares the read current of the non-superior product with the default reference current value to determine whether the read current value is less than the default reference current value. If the determination is no, the non-superior product is determined to be a qualified product, and step S204 is executed; otherwise, the non-superior product is determined to be a defective product.

[0069] Specifically, based on the default reference current value, non-superior products are further screened. By comparing the read current of non-superior products with the default reference current, non-superior products are divided into qualified products and defective products.

[0070] S204 performs reliability testing and identifies chips that pass the reliability test as valid chips.

[0071] Specifically, after obtaining qualified and superior products, the chip needs to undergo further testing according to standard reliability testing procedures to conduct a more comprehensive reliability assessment and ensure there are no reliability issues before mass production and shipment. Reliability testing includes baking tests and / or low-temperature tests.

[0072] In this embodiment, the target chip is screened by increasing the default reference current of the chip to a preset reference current value and comparing the read current value with the preset reference current value, thereby filtering out chips with insufficient long-term reliability.

[0073] In one embodiment, a chip failure screening method includes:

[0074] S300 applies a read voltage to the target chip at a preset temperature and obtains the read current value of the target chip at the first voltage. The read voltage is within the operating voltage range of the chip.

[0075] When the read current value exceeds the default reference current value of the target chip, S301 adjusts the default reference current value to a preset reference current value, which is greater than the default reference current value.

[0076] To select valid chips, initial screening is performed based on the target chip's default reference current. By comparing the target chip's read current with the default reference current, a read current greater than the default reference current value indicates a high current and the chip has the capability to read "1".

[0077] Specifically, the reference current is constant when the chip leaves the factory. During testing, the reference current is temporarily increased only for that specific test item. After the test item is completed, it will return to the original reference current. The preset reference current value is usually set based on user feedback. For example, the default reference current value is 3mA. After a period of use, customers report that the chip is prone to reading "1" failures when the read current is 4mA. In this case, the preset reference current can be set to 4mA.

[0078] S302 compares the preset reference current value with the read current value to determine whether the preset reference current value is less than the read current value. If the determination is yes, the target chip is identified as a superior product; otherwise, the target is identified as a qualified product.

[0079] Specifically, because chips are prone to problems under low voltage and high temperature is not conducive to the turn-on of the select gate (SG), it is easy to cause large current to be difficult to pass, thus affecting the chip's performance in reading "1". This defect usually only appears after a period of use. In order to screen out chips that may have this defect before the product is delivered to the customer, the read current is examined under high temperature and low voltage test conditions.

[0080] For example, if the readout current should be 8mA, but due to incomplete chip activation, the actual readout current is 5mA, and assuming the default reference current is 3mA, the readout current is still higher than the default reference current. It can still read a "1" normally, but the chip actually has a defect. If screening is based solely on the default reference current, it will miss some chips. However, if the default reference current becomes 6mA while the readout current is 5mA, worsening the chip's ability to read "1", it will be easier to screen out potentially defective chips.

[0081] In this embodiment, the target chip is first initially screened using a default reference current value. Then, the default reference current value is increased to a preset reference current value for further screening, resulting in a chip with better reliability.

[0082] In one embodiment, based on any of the above embodiments, before applying a read voltage to the target chip at a preset temperature and obtaining the read current value of the target chip under the read voltage, the method includes: performing a room temperature test on the chip under test, and determining the chip under test that passes the room temperature test as the target chip.

[0083] One embodiment of the present invention is shown in the accompanying drawings. Figure 4 A chip failure screening device includes an acquisition module 10, an adjustment module 20, a first comparison module 30, a first determination module 40, and a second determination module 50, wherein:

[0084] The acquisition module 10 is used to apply a read voltage to the target chip at a preset temperature and acquire the read current value of the target chip at the read voltage, wherein the read voltage is within the operating voltage range of the chip.

[0085] The adjustment module 20 is used to adjust the default reference current value of the target chip to a preset reference current value, wherein the preset reference current value is greater than the default reference current value.

[0086] The first comparison module 30 is used to compare the read current value with the preset reference current value.

[0087] The first determining module 40 is used to determine the target chip as a superior product when the read current value is not less than the preset reference current value;

[0088] The second determining module 50 is used to determine the target chip as a non-premium product when the read current value is less than the preset reference current value.

[0089] In this embodiment, a certain voltage is applied to the target chip at a preset temperature, and the readout current of the target chip at this voltage is compared with a preset reference current to screen the target chips. By increasing the default reference current of the target chip to the preset reference current value, an equivalent low-voltage, high-temperature, long-term application environment is created, thereby screening out chips that may fail under this test environment.

[0090] In one embodiment, the product further includes: a second comparison module for comparing the read current of a non-superior product with a default reference current value; a third determination module for determining a non-superior product as a qualified product when the read current value exceeds the default reference current value; and a fourth determination module for determining a non-superior product as a defective product when the read current value does not exceed the default reference current value.

[0091] In one embodiment, the device further includes a room temperature testing module for performing room temperature testing on the chip under test, and identifying the chip under test that passes the room temperature test as the target chip.

[0092] In one embodiment, based on any of the above device embodiments, it further includes: a reliability testing module, used to perform reliability testing on the qualified product or the superior product, and to determine the qualified product or the superior product that passes the reliability test as a valid chip; the reliability test includes baking test and / or low temperature test.

[0093] It should be noted that the embodiments of the chip failure screening device provided by this invention and the embodiments of the chip failure screening method described above are all based on the same inventive concept and can achieve the same technical effects. Therefore, other specific details of the embodiments of the chip failure screening device can be found in the description of the embodiments of the chip failure screening method described above.

[0094] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0095] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between apparatuses or units may be electrical, mechanical, or other forms.

[0096] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0097] Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The integrated unit described above can be implemented in hardware or as a software functional unit.

[0098] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method of screening for chip failure, comprising: include: A read voltage is applied to the target chip in a high-temperature environment, and the read current value of the target chip under the read voltage is obtained, wherein the read voltage is within the operating voltage range of the target chip; The default reference current value of the target chip is adjusted to a preset reference current value to represent the situation where the target chip is used for a long time in a low-pressure and high-temperature test environment. The preset reference current value is greater than the default reference current value. Compare the readout current value with the preset reference current value; When the readout current value is not less than the preset reference current value, the target chip is determined to be of superior quality; When the readout current value is less than the preset reference current value, the target chip is determined to be a non-premium product. The readout current value of the non-premium product is compared with the default reference current value; When the read current value exceeds the default reference current value, the non-superior product is determined to be a qualified product; When the read current value does not exceed the default reference current value, the non-superior product is identified as a defective product.

2. The method of claim 1, wherein the step of determining the failure of the chip comprises the steps of: Also includes: ​ The qualified products and / or the superior products are subjected to reliability testing, and the qualified products and / or the superior products that pass the reliability testing are determined to be valid chips; the reliability testing includes baking test and / or low temperature test.

3. The method of claim 1, wherein the step of determining the failure of the chip comprises the steps of: Before applying a read voltage to the target chip in a high-temperature environment and obtaining the read current value of the target chip under the read voltage, the process includes: ​ Perform a room temperature test on the chip under test, and identify the chip under test that passes the room temperature test as the target chip.

4. A device for screening of chip failure, characterized by, include: An acquisition module is used to apply a read voltage to a target chip in a high-temperature environment and acquire the read current value of the target chip under the read voltage, wherein the read voltage is within the operating voltage range of the target chip; An adjustment module is used to adjust the default reference current value of the target chip to a preset reference current value, so as to be equivalent to the target chip being used for a long time in a low-voltage and high-temperature test environment. The preset reference current value is greater than the default reference current value. The first comparison module is used to compare the read current value with the preset reference current value; The first determining module is used to determine the target chip as a superior product when the read current value is not less than the preset reference current value; The second determining module is used to determine the target chip as a non-premium product when the read current value is less than the preset reference current value; The second comparison module is used to compare the readout current of the non-premium product with the default reference current value. The third determining module is used to determine the non-superior product as a qualified product when the read current value exceeds the default reference current value; The fourth determining module is used to determine the non-superior product as a defective product when the read current value does not exceed the default reference current value.

5. The chip failure screening apparatus according to claim 4, wherein Also includes: A reliability testing module is used to perform reliability testing on the qualified or superior products, and to determine the qualified and / or superior products that pass the reliability test as valid chips; the reliability test includes baking test and / or low temperature test.

6. The chip failure screening apparatus according to claim 4, wherein Also includes: The room temperature testing module is used to perform room temperature testing on the chip under test, and to identify the chip under test that passes the room temperature test as the target chip.

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