Flash block read count compression method and device, computer device and storage medium
By distinguishing high and low bits for flash memory block read counts with 24-bit granularity and transferring them to the NAND storage area when a threshold is reached, the problem of DRAM space waste is solved, and more efficient storage resource utilization is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2022-10-20
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, SSDs consume excessive DRAM space when recording the number of flash memory block reads, resulting in a waste of storage resources. Especially when DRAM capacity is limited, how to make reasonable use of DRAM space becomes an important issue.
The flash memory block read count is distinguished into high and low bits in DRAM with 24-bit granularity, and the high bit record is transferred to the NAND storage area when the threshold is reached, which reduces DRAM space occupation and saves NAND storage space.
By partitioning and storing flash memory block read counts, the DRAM space usage is reduced, NAND storage space is saved, and more efficient storage resource utilization is achieved.
Smart Images
Figure CN116027968B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of storage technology, and more specifically to a method, apparatus, computer device, and storage medium for compressing the number of reads of flash memory blocks. Background Technology
[0002] With the reduction in manufacturing costs and the improvement in product performance of SSDs (Solid State Drives), SSDs have been widely used in various applications. Currently, in the PC market, SSDs have gradually replaced traditional HDDs (Hard Disk Drives), providing users with a better experience in terms of reliability and performance.
[0003] Due to read interference, most existing technologies record the number of read operations for each flash memory block in DRAM during SSD operation. Since the number of flash memory block read operations can reach millions, the commonly used storage solution is to use 32 bits to store the read operation count for a single flash memory block. This method results in excessively large DRAM memory space, leading to wasted storage resources. In some consumer-grade SSD scenarios, due to hardware cost and power consumption considerations, the DRAM capacity in the SSD may be very small. When the DRAM capacity of an SSD is very limited, the rational use of DRAM space becomes particularly important. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method, apparatus, computer device and storage medium for compressing flash memory block read counts, which aims to reduce the DRAM space occupied by the number of cache flash memory block read counts, while saving NAND storage space.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] The first aspect is the method for compressing the number of flash memory block reads, including:
[0007] Receive read request;
[0008] Break the read request into multiple page-level read command nodes;
[0009] For a single page-level read command, increment the flash block read count by 1;
[0010] The number of flash memory block reads is divided into 24-bit granularity and stored in the first memory area, with high and low bits separated.
[0011] Determine whether the total number of flash block reads has reached the threshold for refreshing to the second storage area;
[0012] If the threshold for refreshing to the second storage area is reached, all flash block read counts recorded in the high-order bits of the 24-bit granularity area will be transferred from the first storage area to the second storage area.
[0013] The further technical solution is that the high-order bits in the 24-bit granularity area are the high 16 bits.
[0014] The further technical solution is that the lower 8 bits are in the 24-bit granularity area.
[0015] The further technical solution is as follows: after storing the flash memory block read counts in a 24-bit granularity and separating the high and low bits in the first storage area, it also includes:
[0016] Get the total number of reads for the flash memory block.
[0017] The further technical solution is as follows: the total number of reads of the flash memory block is obtained by left-shifting the high 16 bits of the flash memory block read count by 8 bits and adding it to the low 8 bits of the flash memory block read count.
[0018] The further technical solution is as follows: the first storage area is DRAM.
[0019] The further technical solution is that the second storage area is NAND.
[0020] Secondly, the flash memory block read count compression device includes a receiving unit, a splitting unit, a recording unit, a storage unit, a judging unit, and a moving unit;
[0021] The receiving unit is used to receive read requests;
[0022] The splitting unit is used to split a read request into multiple page-level read command nodes;
[0023] The recording unit is used to increment the flash block read count by 1 for a single page-level read command;
[0024] The storage unit is used to store the number of flash memory block reads in a 24-bit granularity, with high bits and low bits in the first storage area;
[0025] The judgment unit is used to determine whether the total number of reads of the flash memory block has reached the threshold for refreshing to the second storage area;
[0026] The transfer unit is used to transfer all flash memory block read counts of the high-order records in the 24-bit granularity area from the first storage area to the second storage area if the threshold for refreshing to the second storage area is reached.
[0027] Thirdly, a computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the flash memory block read count compression method as described above.
[0028] Fourthly, a computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the flash memory block read count compression method described above.
[0029] The beneficial effects of this invention compared with the prior art are: this invention compresses the number of reads of a flash memory block that is currently commonly stored using 32 bits to distinguish the high and low bits and store them in DRAM, which can reduce the DRAM space occupied by the number of reads of the cache flash memory block, and at the same time save the NAND storage space.
[0030] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of the present invention more obvious and understandable, preferred embodiments are described in detail below. Attached Figure Description
[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 A flowchart illustrating a flash memory block read count compression method provided in a specific embodiment of the present invention;
[0033] Figure 2 A schematic block diagram of a flash memory block read count compression device provided in a specific embodiment of the present invention;
[0034] Figure 3 A schematic block diagram of a computer device provided for a specific embodiment of the present invention;
[0035] Figure 4 This is a flowchart comparing the DRAM space occupied by the present invention and traditional storage solutions. Detailed Implementation
[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0037] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0038] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0039] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0040] This invention provides a method for compressing flash memory block read counts, primarily applied to solid-state drives (SSDs). Figure 1 As shown, the method includes the following steps: S10-S60.
[0041] S10, Receive read request.
[0042] After the host submits a read request to the SSD, the SSD receives the corresponding read request.
[0043] S20. Split the read request into multiple page-level read command nodes.
[0044] SSD read / write caching splits read requests into multiple page-level read command nodes.
[0045] S30. For a single page-level read command, increment the flash block read count by 1.
[0046] S40. The number of flash memory block reads is divided into 24-bit granularity and stored in the first storage area, with high and low bits separated.
[0047] Specifically, the high-order bits in the 24-bit granularity area are the high 16 bits. The low-order bits in the 24-bit granularity area are the low 8 bits.
[0048] In this embodiment, the first storage area is DRAM.
[0049] A single flash block read occupies 24 bits of space, and is stored in high and low bits. Compared to the commonly used 32-bit storage for a flash block read, this is compressed to 24 bits to distinguish high and low bits in DRAM, which can reduce the DRAM space occupied by the cache flash block read.
[0050] In one embodiment, the following steps are included after step S40:
[0051] S45, Get the total number of reads of the flash memory block.
[0052] Specifically, the total number of reads of the flash memory block is obtained by shifting the high 16 bits of the flash memory block read count 8 bits to the left and adding them to the low 8 bits.
[0053] S50. Determine whether the total number of reads of the flash memory block has reached the threshold for refreshing to the second storage area.
[0054] In this embodiment, the second storage area is NAND.
[0055] S60. If the threshold for refreshing to the second storage area is reached, all flash block read counts recorded in the high-order bits of the 24-bit granularity area are transferred from the first storage area to the second storage area.
[0056] The high 16 bits of the flash memory block read count are moved to NAND, while the low 8 bits only need to be recorded in DRAM. This reduces the DRAM space occupied by caching the flash memory block read count, and also saves NAND storage space.
[0057] When the SSD initializes and rebuilds the flash block read count table, only the high 16 bits of data recorded in the NAND need to be restored.
[0058] It should be noted that the choice of 24 bits for storage in this invention is based on the maximum number of reads of the flash memory block. The number of reads of the flash memory block can reach millions of times. Based on the maximum number of reads of the flash memory block, it can be deduced that a minimum of 24 bits of space is required to store one read. Therefore, it is not feasible to store one read with less than 24 bits of space. Of course, it is possible to store one read with more than 24 bits of space, but just like using 32 bits, it will occupy more space.
[0059] like Figure 4 As shown, assuming the SSD has n planes, and each plane has m blocks, using a traditional storage scheme, the total number of flash memory blocks is n*m. Each flash memory block requires 32 bits of DRAM space for read operations, resulting in a total DRAM space usage of 32nmbits. Using the present invention, the total number of flash memory blocks is n*m, and each flash memory block requires 24 bits of DRAM space for read operations, resulting in a total DRAM space usage of 24nmbits. By comparison, it can be concluded that the DRAM space occupied by the present invention after compression is 3 / 4 of that of the traditional scheme.
[0060] Figure 2 This is a schematic block diagram of a flash memory block read count compression device provided in an embodiment of the present invention; corresponding to the above-described flash memory block read count compression device, an embodiment of the present invention also provides a flash memory block read count compression device 100.
[0061] like Figure 2 As shown, the flash memory block read count compression device 100 includes a receiving unit 110, a splitting unit 120, a recording unit 130, a storage unit 140, a judging unit 150, and a moving unit 160.
[0062] The receiving unit 110 is used to receive read requests.
[0063] After the host submits a read request to the SSD, the SSD receives the corresponding read request.
[0064] Splitting unit 120 is used to split a read request into multiple page-level read command nodes.
[0065] SSD read / write caching splits read requests into multiple page-level read command nodes.
[0066] Recording unit 130 is used to increment the flash block read count by 1 for a single page-level read command.
[0067] Storage unit 140 is used to store the number of flash memory block reads in a 24-bit granularity, with high bits and low bits in the first storage area.
[0068] Specifically, the high-order bits in the 24-bit granularity area are the high 16 bits. The low-order bits in the 24-bit granularity area are the low 8 bits.
[0069] In this embodiment, the first storage area is DRAM.
[0070] A single flash block read occupies 24 bits of space, and is stored in high and low bits. Compared to the commonly used 32-bit storage for a flash block read, this is compressed to 24 bits to distinguish high and low bits in DRAM, which can reduce the DRAM space occupied by the cache flash block read.
[0071] In one embodiment, the flash memory block read count compression device 100 further includes an acquisition unit for acquiring the total number of reads of the flash memory block.
[0072] Specifically, the total number of reads of the flash memory block is obtained by shifting the high 16 bits of the flash memory block read count 8 bits to the left and adding them to the low 8 bits.
[0073] The judgment unit 150 is used to determine whether the total number of reads of the flash memory block has reached the threshold for refreshing to the second storage area.
[0074] In this embodiment, the second storage area is NAND.
[0075] The transfer unit 160 is used to transfer all flash block read counts of the high-order records in the 24-bit granularity area from the first storage area to the second storage area if the threshold for refreshing to the second storage area is reached.
[0076] The high 16 bits of the flash memory block read count are moved to NAND, while the low 8 bits only need to be recorded in DRAM. This reduces the DRAM space occupied by caching the flash memory block read count, and also saves NAND storage space.
[0077] When the SSD initializes and rebuilds the flash block read count table, only the high 16 bits of data recorded in the NAND need to be restored.
[0078] It should be noted that the choice of 24 bits for storage in this invention is based on the maximum number of reads of the flash memory block. The number of reads of the flash memory block can reach millions of times. Based on the maximum number of reads of the flash memory block, it can be deduced that a minimum of 24 bits of space is required to store one read. Therefore, it is not feasible to store one read with less than 24 bits of space. Of course, it is possible to store one read with more than 24 bits of space, but just like using 32 bits, it will occupy more space.
[0079] like Figure 4 As shown, assuming the SSD has n planes, and each plane has m blocks, using a traditional storage scheme, the total number of flash memory blocks is n*m. Each flash memory block requires 32 bits of DRAM space for read operations, resulting in a total DRAM space usage of 32nmbits. Using the present invention, the total number of flash memory blocks is n*m, and each flash memory block requires 24 bits of DRAM space for read operations, resulting in a total DRAM space usage of 24nmbits. By comparison, it can be concluded that the DRAM space occupied by the present invention after compression is 3 / 4 of that of the traditional scheme.
[0080] The aforementioned flash memory block read count compression device can be implemented as a computer program, which can, for example... Figure 3 It runs on the computer device shown.
[0081] Please see Figure 3 , Figure 3 This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device 500 can be a server, wherein the server can be a standalone server or a server cluster composed of multiple servers.
[0082] like Figure 3As shown, the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the flash memory block read count compression method steps as described above.
[0083] The computer device 700 can be a terminal or a server. The computer device 700 includes a processor 720, a memory, and a network interface 750 connected via a system bus 710, wherein the memory may include a non-volatile storage medium 730 and internal memory 740.
[0084] The non-volatile storage medium 730 can store an operating system 731 and a computer program 732. When the computer program 732 is executed, it enables the processor 720 to perform any flash memory block read count compression method.
[0085] The processor 720 provides computing and control capabilities to support the operation of the entire computer device 700.
[0086] The internal memory 740 provides an environment for the execution of the computer program 732 in the non-volatile storage medium 730. When the computer program 732 is executed by the processor 720, the processor 720 can execute any flash memory block read count compression method.
[0087] This network interface 750 is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 700 to which the present application is applied. The specific computer device 700 may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements. The processor 720 is used to run program code stored in memory to implement the following steps:
[0088] Flash memory block read count compression methods include:
[0089] Receive read request;
[0090] Break the read request into multiple page-level read command nodes;
[0091] For a single page-level read command, increment the flash block read count by 1;
[0092] The number of flash memory block reads is divided into 24-bit granularity and stored in the first memory area, with high and low bits separated.
[0093] Determine whether the total number of flash block reads has reached the threshold for refreshing to the second storage area;
[0094] If the threshold for refreshing to the second storage area is reached, all flash block read counts recorded in the high-order bits of the 24-bit granularity area will be transferred from the first storage area to the second storage area.
[0095] In one embodiment: the high-order bits in the 24-bit granularity region are the high 16 bits.
[0096] In one embodiment: the lower 8 bits are the lower bits in the 24-bit granularity area.
[0097] In one embodiment: after storing the flash memory block read counts in a 24-bit granularity, separating high and low bits, in the first storage area, the method further includes:
[0098] Get the total number of reads for the flash memory block.
[0099] In one embodiment: the total number of reads of the flash memory block is obtained by left-shifting the high 16 bits of the flash memory block read count by 8 bits and adding it to the low 8 bits of the flash memory block read count.
[0100] In one embodiment: the first storage area is DRAM.
[0101] In one embodiment: the second storage area is NAND.
[0102] It should be understood that in the embodiments of this application, the processor 720 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.
[0103] Those skilled in the art will understand that Figure 3 The structure of the computer device 700 shown does not constitute a limitation on the computer device 700, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0104] In another embodiment of the present invention, a computer-readable storage medium is provided. This computer-readable storage medium may be a non-volatile computer-readable storage medium. The computer-readable storage medium stores a computer program, wherein when executed by a processor, the computer program implements the flash memory block read count compression method disclosed in this embodiment of the present invention.
[0105] Those skilled in the art will readily understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention.
[0106] In the embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Units with the same function may be grouped into one unit. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, or it may be an electrical, mechanical, or other form of connection.
[0107] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of the present invention, depending on actual needs.
[0108] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0109] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks.
[0110] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A flash block read count compression method, characterized by, include: Receive read request; Break the read request into multiple page-level read command nodes; For a single page-level read command, increment the flash block read count by 1; The number of flash memory block reads is stored in the first storage area in a 24-bit granularity, with high and low bits. The high bit in the 24-bit granularity is the high 16 bits, and the low bit is the low 8 bits. Determine whether the total number of flash block reads has reached the threshold for refreshing to the second storage area; If the threshold for refreshing to the second storage area is reached, all flash block read counts recorded in the high 16 bits of the 24-bit granularity area are transferred from the first storage area to the second storage area, while the low 8 bits remain in the first storage area. The first storage area is DRAM, and the second storage area is NAND.
2. The flash block read count compression method of claim 1, wherein, After storing the flash memory block read counts in a 24-bit granularity, separating the high and low bits in the first storage area, the method further includes: Get the total number of reads for the flash memory block.
3. The flash block read count compression method of claim 2, wherein, The total number of reads of the flash memory block is obtained by left-shifting the high 16 bits of the flash memory block read count by 8 bits and adding it to the low 8 bits.
4. A flash block read count compression apparatus, which, when operating, performs the flash block read count compression method according to any one of claims 1 to 3, characterized in that, It includes a receiving unit, a splitting unit, a recording unit, a storage unit, a judgment unit, and a transfer unit; The receiving unit is used to receive read requests; The splitting unit is used to split a read request into multiple page-level read command nodes; The recording unit is used to increment the flash block read count by 1 for a single page-level read command; The storage unit is used to store the number of flash memory block reads in a 24-bit granularity, with high bits and low bits in the first storage area; The judgment unit is used to determine whether the total number of reads of the flash memory block has reached the threshold for refreshing to the second storage area; The transfer unit is used to transfer all flash memory block read counts of the high-order records in the 24-bit granularity area from the first storage area to the second storage area if the threshold for refreshing to the second storage area is reached.
5. A computer device, comprising: The device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor, when executing the computer program, implements the flash memory block read count compression method as described in any one of claims 1 to 3.
6. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor, the processor performs the flash memory block read count compression method as described in any one of claims 1 to 3.