A data processing method, apparatus and device

Abstract

The present disclosure relates to a data processing method, device and equipment, and relates to the field of computers. The method comprises: compiling first circuit data to obtain first intermediate data; for each loop invariant in the first intermediate data whose fan-out number is greater than a fan-out threshold, replacing a first operand in the first intermediate data based on a fan-out tree of the each loop invariant to obtain second intermediate data, wherein a node of the fan-out tree of any loop invariant is used to represent the any loop invariant, and the first operand represents an operand corresponding to the loop invariant in the loop data to which the loop invariant belongs; and generating second circuit data based on the second intermediate data. According to the technical solution of the present disclosure, the corresponding operand of the loop invariant in the loop is replaced based on the associated nodes of the constructed fan-out tree, the second intermediate data is obtained, the fan-out number of the loop invariant is reduced, and thus the problem of high fan-out can be solved.

Description

[0001] This disclosure is based on and claims priority to U.S. Provisional Patent Application No. 63 / 376,331, filed on September 20, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of computers, and more particularly to a data processing method, apparatus, and device. Background Technology

[0003] Field-Programmable Gate Arrays (FPGAs) are a further development of programmable devices such as programmable array logic and general-purpose array logic. They are a type of semi-custom circuit in the field of application-specific integrated circuits (ASICs). How to design FPGA circuits is a research direction.

[0004] Currently, High-Level Synthesis (HLS) compilers are commonly used for FPGA circuit design. HLS compilers employ techniques that use higher-level abstraction of behavior to describe the generated circuits. The concept of "high-level" represents a higher level of abstraction in the hardware description language. For example, it converts C-specification code written in C, C++, or System C into register-transfer level data and synthesizes it onto the FPGA to realize the FPGA circuit design.

[0005] The problem with the above technical solution is that when the HLS compiler processes data, that is, when it performs loop unrolling of the code, it causes the data to be broadcast, which leads to a high fan-out problem and affects the working performance of the designed FPGA circuit. Summary of the Invention

[0006] This disclosure provides a data processing method, apparatus, and device. By constructing a fan-out tree in an intermediate representation layer for each loop invariant whose fan-out count exceeds a fan-out threshold, and replacing the operands corresponding to each loop invariant in the loop with the associated nodes of the constructed fan-out tree, a second intermediate data is obtained. This reduces the fan-out count of the loop invariants, thereby solving the high fan-out problem. The technical solution of this disclosure is as follows:

[0007] According to one aspect of the embodiments of the present disclosure, a data processing method is provided, the method comprising:

[0008] The first circuit data is compiled to obtain the first intermediate data. The first circuit data is data describing the logical structure of the target circuit using a first programming language. The first intermediate data is data describing the logical structure of the target circuit using an intermediate code language.

[0009] For each cycle invariant in the first intermediate data whose fan-out number is greater than the fan-out threshold, based on the fan-out tree of each cycle invariant, the first operand in the first intermediate data is replaced to obtain the second intermediate data. The cycle invariant refers to a variable whose value does not change with the iteration of the cycle. The node of the fan-out tree of any cycle invariant is used to represent any cycle invariant. The first operand represents the operand corresponding to the cycle invariant in the cycle data to which it belongs.

[0010] Second circuit data is generated based on the second intermediate data. The second circuit data is data describing the logical structure of the target circuit using a second programming language.

[0011] According to another aspect of the embodiments of this disclosure, a data processing apparatus is provided, comprising:

[0012] The compilation unit is configured to compile the first circuit data to obtain the first intermediate data, wherein the first circuit data is data describing the logical structure of the target circuit using a first programming language, and the first intermediate data is data describing the logical structure of the target circuit using an intermediate code language.

[0013] The replacement unit is configured to replace the first operand in the first intermediate data with the first operand based on the fan-out tree of each cyclic invariant in the first intermediate data for each cyclic invariant whose fan-out number is greater than the fan-out threshold, to obtain the second intermediate data. The cyclic invariant is a variable whose value does not change with the iteration of the loop. The node of the fan-out tree of any cyclic invariant is used to represent any cyclic invariant. The first operand represents the operand corresponding to the cyclic invariant in the cyclic data to which it belongs.

[0014] The generation unit is configured to generate second circuit data based on the second intermediate data, wherein the second circuit data is data describing the logical structure of the target circuit using a second programming language.

[0015] In some embodiments, the replacement unit is further configured to, for any loop data in the first intermediate data, obtain the total number of loop iterations and the loop unrolling coefficient of the loop data, the loop unrolling coefficient being used to represent the number of copies of the loop body; and, if the ratio of the total number of loop iterations to the loop unrolling coefficient is greater than a target threshold, replace the first operand based on the fan-out tree of each loop invariant in the loop data.

[0016] In some embodiments, the replacement unit includes:

[0017] The identification subunit is configured to identify cyclic invariants in the cyclic data to obtain at least one cyclic invariant.

[0018] The extraction subunit is configured to extract the at least one cycle invariant from the inside of the cycle body in the cycle data to the outside of the cycle body;

[0019] An optimization subunit is configured to optimize the cyclic data;

[0020] The replacement subunit is configured to replace the first operand with a second operand for any loop invariant, the second operand representing the operand indicated by the associated node of the fan-out tree.

[0021] In some embodiments, the identification subunit is configured to determine latches in the loop data; for any variable in the latch, to recursively traverse the operands in multiple instructions of the loop body to obtain multiple variable recursion results for the variable; and in response to all of the multiple variable recursion results being true, to determine that the variable is a loop invariant.

[0022] In some embodiments, the identification subunit is configured to identify any variable in the loop data as a loop invariant if the variable is defined and assigned a value outside the loop body and the variable is used inside the loop body.

[0023] In some embodiments, the extraction subunit is configured to traverse the loop body of the loop data in a depth-first order to obtain a set of loop invariants, the set of loop invariants including at least one loop-invariant expression; for any expression in the set of loop invariants, the extraction cost of the expression is determined, the extraction cost representing the degree of influence of extracting the expression on the loop data; if the extraction cost is not less than a cost threshold, the expression is extracted as a loop invariant to the outside of the loop body.

[0024] In some embodiments, the optimization subunit is configured to perform any combination of first operations on the cyclic data in a preset order, the first operations including iteratively stripping the cyclic block, calculating the number of iterations, calculating the expansion coefficient, and performing iterative operations at the beginning or end; perform any combination of second operations on the cyclic data in a preset order, the second operations including copying basic blocks, remapping instructions, updating PHI nodes, and connecting jump instructions between basic blocks; and perform any combination of third operations on the cyclic data in a preset order, the third operations including updating the SE scalar evolution, updating the DT dominator tree, updating LI cycle information, performing LCSSA format protection, deleting dead instructions and simplifying instructions, and merging adjacent basic blocks.

[0025] In some embodiments, the replacement subunit is configured to, for any loop invariant, construct a fan-out tree for the loop invariant outside the loop body in the loop data; and inside the loop body in the loop data, replace the first operand corresponding to the loop invariant in the replacement operation instruction with the second operand.

[0026] In some embodiments, the replacement subunit is further configured to construct a fan-out tree for the loop invariant outside the loop body in the loop data based on a fan-out constraint coefficient, wherein the fan-out constraint coefficient is used to limit the number of associated nodes in the fan-out tree; or, based on a node fan-out value, construct a fan-out tree for the loop invariant outside the loop body in the loop data, wherein the node fan-out value is used to limit the number of layers in the fan-out tree.

[0027] According to another aspect of the embodiments of this disclosure, an electronic device is provided, the electronic device comprising:

[0028] processor;

[0029] Memory used to store the processor's executable instructions;

[0030] The processor is configured to execute the instruction to implement the aforementioned data processing method.

[0031] According to another aspect of the present disclosure, a computer-readable storage medium is provided that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the above-described data processing method.

[0032] According to another aspect of the present disclosure, a chip is provided, the chip including a processor and a memory, the processor being used to store processor-executable instructions in the memory, the processor being configured to execute the instructions to implement the above-described data processing method.

[0033] According to another aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described data processing method.

[0034] This disclosure provides a data processing method. By compiling first circuit data, first intermediate data is obtained. Since the first intermediate data may contain cyclic invariants that fan out, which may affect the design of the target circuit, a fan-out tree is constructed in the intermediate representation layer for each cyclic invariant whose fan-out number is greater than the fan-out threshold. Based on the associated nodes of the constructed fan-out tree, the operands corresponding to each cyclic invariant in the loop are replaced to obtain second intermediate data. This reduces the fan-out number of cyclic invariants, thereby solving the problem of high fan-out.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0037] Figure 1 This is a schematic diagram illustrating the implementation environment of a data processing method according to an exemplary embodiment.

[0038] Figure 2 This is a flowchart illustrating a data processing method according to an exemplary embodiment.

[0039] Figure 3 This is a flowchart illustrating another data processing method according to an exemplary embodiment.

[0040] Figure 4 This is a flowchart illustrating a method for determining loop invariants according to an exemplary embodiment.

[0041] Figure 5 This is a flowchart illustrating the extraction of loop invariants according to an exemplary embodiment.

[0042] Figure 6 This is a schematic diagram illustrating the partial and complete unfolding of a loop body according to an exemplary embodiment.

[0043] Figure 7 This is a schematic diagram illustrating three operations of a loop unrolling algorithm according to an exemplary embodiment.

[0044] Figure 8 This is a schematic diagram illustrating the head or tail residual iteration according to an exemplary embodiment.

[0045] Figure 9 This is a schematic diagram illustrating instruction remapping according to an exemplary embodiment.

[0046] Figure 10 This is a schematic diagram illustrating a jump instruction between connection basic blocks according to an exemplary embodiment.

[0047] Figure 11 This is a schematic diagram illustrating the circuitry before and after constructing a fan-out tree according to an exemplary embodiment.

[0048] Figure 12 This is a schematic diagram illustrating a comparison between first intermediate data and second intermediate data according to an exemplary embodiment.

[0049] Figure 13This is a flowchart illustrating the process of obtaining second circuit data according to an exemplary embodiment.

[0050] Figure 14 This is a block diagram illustrating a data processing apparatus according to an exemplary embodiment.

[0051] Figure 15 This is a block diagram illustrating another data processing apparatus according to an exemplary embodiment.

[0052] Figure 16 This is a block diagram illustrating an electronic device according to an exemplary embodiment.

[0053] Figure 17 This is a schematic diagram of the structure of a server according to an exemplary embodiment. Detailed Implementation

[0054] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0055] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0056] The following is an explanation of the terms used in this disclosure.

[0057] Field Programmable Gate Array (FPGA) is a product of further development based on programmable devices such as programmable array logic and general-purpose array logic. It is a semi-custom circuit in the field of application-specific integrated circuits.

[0058] The High-Level Synthesis (HLS) compiler can use C++ as input to generate register-transfer level (RTL) code. This compiler can accelerate the verification time of RTL code by increasing the abstraction level of FPGA hardware designs.

[0059] Intermediate code (IR) is data such as C specification code written in C, C++, or System C that is converted into machine code by the compiler.

[0060] Register Transfer Level (RTL) is a hierarchy that describes a circuit by describing the logic functions between registers.

[0061] A basic block (BB) is a sequence of statements that is executed sequentially in a program. It has only one entry point and one exit point. The entry point is the first statement in the block, and the exit point is the last statement. Execution of a basic block only enters from its entry point and exits from its exit point.

[0062] Figure 1 This is a schematic diagram illustrating an implementation environment for a data processing method according to an exemplary embodiment. See also... Figure 1 The implementation environment specifically includes: terminal 101 and server 102.

[0063] Terminal 101 can be at least one of the following devices: smartphone, smartwatch, desktop computer, laptop, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), and laptop computer. Applications for data processing can be installed and run on terminal 101. Terminal 101 can be connected to server 102 via a wireless network or wired network.

[0064] Terminal 101 can refer to one of a plurality of terminals; this embodiment uses terminal 101 as an example only. Those skilled in the art will understand that the number of terminals can be more or less. For example, there may be only a few terminals, or dozens or hundreds, or even more. This disclosure does not limit the number of terminals or the type of device.

[0065] Server 102 can be at least one of a single server, multiple servers, a cloud computing platform, and a virtualization center. Server 102 can be connected to terminal 101 and other terminals via a wireless network or a wired network. Optionally, the number of servers can be more or less, and this disclosure does not limit this. Of course, server 102 may also include other functional servers to provide more comprehensive and diversified services.

[0066] Figure 2 This is a flowchart illustrating a data processing method according to an exemplary embodiment, such as... Figure 2 As shown, this method is executed by the server and includes the following steps.

[0067] In step S201, the server compiles the first circuit data to obtain first intermediate data. The first circuit data is data describing the logical structure of the target circuit using a first programming language, and the first intermediate data is data describing the logical structure of the target circuit using an intermediate code language.

[0068] In this embodiment, the target circuit can be an FPGA circuit. When designing the FPGA circuit, the server can compile the input first circuit data using an HLS compiler. The first circuit data is described by a first programming language, and the first intermediate data is described by an intermediate code language. The first programming language can be C, C++, or System C standard code, and the intermediate code language can be IR code. This embodiment does not limit the types of the first programming language and the intermediate code language.

[0069] It should be noted that the HLS compiler backend can perform loop unrolling on the compiled first intermediate data. However, this loop unrolling can cause data broadcasting, resulting in excessive fan-out. This leads to excessive wire delay during the actual routing and placement of the FPGA circuit, thus affecting the FPGA circuit's performance. Therefore, this embodiment optimizes the first intermediate data located at the intermediate representation layer to improve the performance of the target circuit.

[0070] In step S202, for each cyclic invariant in the first intermediate data whose fan-out number is greater than the fan-out threshold, the server replaces the first operand in the first intermediate data based on the fan-out tree of each cyclic invariant to obtain the second intermediate data. Cyclic invariants are variables whose values ​​do not change with the iteration of the loop. The nodes of the fan-out tree of any cyclic invariant are used to represent any cyclic invariant. The first operand represents the operand corresponding to the cyclic invariant in its respective cyclic data.

[0071] In this embodiment, the server can identify each cyclic invariant whose value does not change with iteration in the first intermediate data. If the fan-out count of any cyclic invariant exceeds a fan-out threshold, the server can construct a fan-out tree for that cyclic invariant. The server then replaces the first operand (i.e., the operand corresponding to that cyclic invariant in the loop data) with the associated nodes of the fan-out tree, thereby reducing the fan-out count of the cyclic invariant to less than the fan-out threshold, thus obtaining the second intermediate data. The fan-out threshold is used to determine if there is an excessive fan-out problem, and the fan-out tree represents the calling relationship between fan-out nodes and their subordinate nodes. By constructing a fan-out tree for each cyclic invariant with excessive fan-out, the fan-out count of each associated node in the fan-out tree, i.e., the cyclic invariant, decreases and becomes less than the fan-out threshold, thereby solving the excessive fan-out problem and improving the performance of the target circuit.

[0072] In step S203, the server generates second circuit data based on the second intermediate data. The second circuit data is data describing the logical structure of the target circuit using a second programming language.

[0073] In this embodiment, the server solves the problem of excessive fan-out for loop invariants by constructing a fan-out tree for the loop invariants, thus obtaining optimized second intermediate data. The server then transmits this second intermediate data to the backend of the HLS compiler to generate second circuit data optimized from the first circuit data. This second circuit data can be described by a second programming language, which can be in RTL code format. By generating the optimized second circuit data, the target circuit obtained based on the second circuit data satisfies timing constraints, improving the performance of the target circuit.

[0074] This disclosure provides a data processing method. By compiling first circuit data, first intermediate data is obtained. Since the first intermediate data may contain cyclic invariants that fan out, which may affect the design of the target circuit, a fan-out tree is constructed in the intermediate representation layer for each cyclic invariant whose fan-out number is greater than the fan-out threshold. Based on the associated nodes of the constructed fan-out tree, the operands corresponding to each cyclic invariant in the loop are replaced to obtain second intermediate data. This reduces the fan-out number of cyclic invariants, thereby solving the problem of high fan-out.

[0075] In some embodiments, for each cycle invariant in the first intermediate data whose fan-out number is greater than a fan-out threshold, the first operand in the first intermediate data is replaced based on the fan-out tree of each cycle invariant to obtain the second intermediate data, including:

[0076] For any loop data in the first intermediate data, obtain the total number of loop iterations and the loop unrolling coefficient of the loop data. The loop unrolling coefficient is used to represent the number of copies of the loop body.

[0077] If the ratio of the total number of iterations to the loop unrolling coefficient is greater than the target threshold, the first operand is replaced based on the fan-out tree of each loop invariant in the loop data.

[0078] By obtaining the total number of iterations and the loop expansion coefficient, we can provide support for determining whether there is an excessive fan-out problem, and then optimize the loop data with excessive fan-out.

[0079] In some embodiments, replacing the first operand based on the fan-out tree of each loop invariant in the loop data includes:

[0080] Identify the cyclic invariants in the cyclic data to obtain at least one cyclic invariant.

[0081] Extract at least one loop invariant from the inside of the loop body to the outside of the loop body in the loop data;

[0082] Optimize loop data;

[0083] For any loop invariant, replace the first operand with the second operand, which represents the operand indicated by the associated node of the fan-out tree.

[0084] By constructing a fan-out tree for cyclic invariants with excessive fan-out, the fan-out number of each associated node in the fan-out tree, i.e., the cyclic invariant, decreases and becomes less than the fan-out threshold, thereby solving the problem of excessive fan-out and improving the performance of the target circuit.

[0085] In some embodiments, identifying cyclic invariants in cyclic data to obtain at least one cyclic invariant includes:

[0086] Identify the latches in the loop data;

[0087] For any variable in the latch, the operands in multiple instructions of the loop body are traversed recursively to obtain multiple variable recursion results;

[0088] If the recursive result of multiple variables is true, then the variable is determined to be a loop invariant.

[0089] By using a recursive approach for detection, loop invariants can be obtained more accurately.

[0090] In some embodiments, identifying cyclic invariants in cyclic data to obtain at least one cyclic invariant includes:

[0091] For any variable in the loop data, if the variable is defined and assigned a value outside the loop body, but is used inside the loop body, the variable is determined as a loop invariant.

[0092] By understanding where variables are defined, assigned values, and used, loop invariants can be determined more accurately.

[0093] In some embodiments, extracting at least one loop invariant from inside the loop body to outside the loop body in the loop data includes:

[0094] Traverse the loop body of the loop data in depth-first order to obtain a set of loop invariants, which includes at least one loop-invariant expression.

[0095] For any expression in the set of loop invariants, determine the extraction cost of the expression, which represents the degree of impact of extracting the expression on the loop data;

[0096] If the extraction cost is not less than the cost threshold, the expression is extracted as a loop invariant outside the loop body.

[0097] By extracting loop invariants or loop-invariant expressions, redundant calculations of these expressions are avoided, thus simplifying subsequent operations on loop invariants and eliminating redundant calculations.

[0098] In some embodiments, optimizing cyclic data includes:

[0099] Any combination of first operations performed on the loop data in a preset order. The first operations include iteratively stripping the loop block, calculating the number of loops, calculating the expansion coefficient, and performing iterative operations at the beginning or end.

[0100] Any combination of second operations is performed on the loop data in a preset order. The second operations include copying basic blocks, remapping instructions, updating PHI nodes, and connecting jump instructions between basic blocks.

[0101] Any combination of third operations is performed on the loop data in a preset order. The third operations include updating the SE scalar evolution, updating the DT dominator tree, updating the LI loop information, performing LCSSA format protection, deleting dead instructions and simplifying instructions, and merging adjacent basic blocks.

[0102] The optimization of loop data is achieved by performing three operations of the loop unrolling algorithm on the loop data.

[0103] In some embodiments, replacing the first operand with the second operand for any loop invariant includes:

[0104] For any loop invariant, construct a fan-out tree for the loop invariant outside the loop body in the loop data;

[0105] Inside the loop body of the loop data, replace the first operand corresponding to the loop invariant in the substitution operation instruction with the second operand.

[0106] By constructing a fan-out tree for loop invariants outside or inside the loop body, the number of fan-outs of the loop invariants is reduced, and the fan-out of each associated node in the resulting fan-out tree satisfies the fan-out threshold constraint.

[0107] In some embodiments, constructing a fan-out tree for loop invariants outside the loop body in the loop data includes:

[0108] Based on the fan-out constraint coefficient, a fan-out tree is constructed outside the loop body in the loop data for the loop invariants. The fan-out constraint coefficient is used to limit the number of associated nodes in the fan-out tree; or...

[0109] Based on node fanout values, a fanout tree is constructed outside the loop body in the loop data as loop invariants, and the node fanout values ​​are used to limit the number of levels of the fanout tree.

[0110] By constructing a fan-out tree based on the fan-out constraint coefficient or the fan-out value of a node for the loop invariant outside the loop body, the number of fan-outs of the loop invariant is reduced, and the fan-out of each associated node in the resulting fan-out tree satisfies the fan-out threshold constraint.

[0111] Figure 3 This is a flowchart illustrating another data processing method according to an exemplary embodiment, such as... Figure 3 As shown, this method is executed by the server and includes the following steps.

[0112] In step S301, the server compiles the first circuit data to obtain the first intermediate data. The first circuit data is data describing the logical structure of the target circuit using a first programming language, and the first intermediate data is data describing the logical structure of the target circuit using an intermediate code language.

[0113] In this embodiment of the disclosure, the server can compile the input first circuit data using an HLS compiler to obtain first intermediate data, i.e., IR code. Then, the server can optimize the first intermediate data through the following steps to improve the performance of the target circuit. The following description uses any cyclic data within the first intermediate data as an example.

[0114] In step S302, for any loop data in the first intermediate data, the server obtains the total number of loop iterations of the loop data and the loop expansion coefficient of the first intermediate data. The loop expansion coefficient is used to represent the number of copies of the loop body.

[0115] In this embodiment of the disclosure, the server can obtain the total number of iterations of the first intermediate data and the loop expansion coefficient of the first intermediate data. Optionally, the loop expansion coefficient of the first intermediate data can be directly assigned by the server, and this loop expansion coefficient is the expected number of iterations. By obtaining the total number of iterations and the loop expansion coefficient, support can be provided for subsequent determination of whether there is an excessive fan-out problem.

[0116] In step S303, when the ratio of the total number of iterations to the loop expansion coefficient is greater than the target threshold, the server identifies loop invariants in the loop data and obtains at least one loop invariant. A loop invariant is a variable whose value does not change with the iteration of the loop.

[0117] In this embodiment, the server compares the ratio of the total number of iterations to the loop unrolling coefficient with a target threshold to determine if the loop data has excessive fan-out. When the number of iterations exceeds the target threshold, such as when the total number of iterations is 1.5, 2, or 2.5 times the loop unrolling coefficient, the server determines that the loop data has excessive fan-out and needs optimization. When the number of iterations is not greater than the target threshold, the server determines that the loop data does not have excessive fan-out and can send the loop data to the HLS compiler backend for the default loop unrolling operation of the HLS compiler, generating unoptimized second circuit data. By determining the loop invariants and then processing the loop invariants that cause fan-out, the high fan-out problem is solved.

[0118] When loop data needs optimization, the server can identify loop invariants to obtain at least one loop invariant. These loop invariants can be categorized into three cases, and the server can identify them using the following three methods.

[0119] Method 1: For any variable in the loop data, if the variable is constant, it will not change after all iterations of the loop data. Therefore, the server can determine that the variable is a loop invariant.

[0120] For example, for any variable in the loop data, assuming that the variable is a constant A, then after any iteration of the loop data, the value of the variable is still a constant A, so the variable is a loop invariant.

[0121] Method Two: For any variable in the loop data, if the variable is defined and assigned a value outside the loop body, but used inside the loop body, then the variable will not change after passing through the loop body, and the server determines this variable as a loop invariant. Correspondingly, for any variable in the loop data, if the variable is defined and assigned a value outside the loop body, but used inside the loop body, the server determines this variable as a loop invariant. By controlling the location of variable definition, assignment, and usage, loop invariants can be determined more accurately.

[0122] For example, for any variable in the loop data, if the variable is defined and assigned a value before the start of any loop body in the loop data, and is used inside the loop body to determine other variables, then the value of the variable after the loop body ends is still the value assigned by the server outside the loop body, then the variable is a loop invariant; or, if the variable is defined before the start of any loop body in the loop data, is used inside the loop body, and is then assigned a value after the loop body ends, then the variable is determined to be a loop invariant.

[0123] Method 3: For any variable in the loop data, if there is only one path to assign a value to this variable within any loop body, and the instruction assigning this value is also a loop invariant within that loop body, then this variable is a loop invariant. The server can use a recursive multi-branch tree algorithm to determine loop invariants. Specifically, it determines a variable within a latch block in the loop data, then recursively traverses the operands of the instructions within the loop body. If the result of a logical AND operation on the multiple recursive results is true, then the variable is determined to be a loop invariant. Accordingly, the server determines the latches within the loop data. Then, for any variable in the latch, the server recursively traverses the operands of multiple instructions within the loop body, obtaining multiple recursive results for that variable. Finally, in response to multiple recursive results being true, the server determines the variable to be a loop invariant. Here, the latch is a basic block constituting any loop, and the recursive result of the variable includes true and false. True indicates recursion to instructions outside the loop, and false indicates recursion to the aforementioned variable.

[0124] For example, Figure 4 This is a flowchart illustrating a method for determining loop invariants according to an exemplary embodiment, such as... Figure 4As shown. Suppose there is a binary operand instruction in the first intermediate data. The server will recursively traverse the two operands included in the instruction. Recursively traversing operand 1 yields a result of False; recursively traversing operand 2 yields a result of True. Performing a logical AND operation on the recursive results of these two operands, the final recursive result is False. Therefore, the server determines that the variable is not a loop invariant.

[0125] In step S304, the server extracts at least one loop invariant from inside the loop body in the loop data to outside the loop body.

[0126] In this embodiment, since the value of a loop invariant does not change during loop iteration, there exists a corresponding expression unrelated to the loop within the loop. Therefore, for any loop invariant or expression, the server can extract the loop invariant from inside the loop body to outside the loop body based on its extraction cost. This extraction cost represents the degree of influence the extracted expression has on the loop data. Accordingly, for any loop, the server traverses the loop body in depth-first order to obtain a set of loop invariants. Then, for any expression in the set of loop invariants, the server determines its extraction cost. Finally, if the extraction cost is not less than a cost threshold, the server extracts the expression as a loop invariant to outside the loop body. This set of loop invariants includes loop-invariant expressions. By extracting loop invariants or loop-invariant expressions, redundant calculations of these expressions are avoided, thus simplifying subsequent operations on loop invariants.

[0127] For example, suppose S represents a loop statement within any loop body in the loop data, and v represents a variable within that loop body. The server marks the variable v within S as unextractable. For expressions exp in loop statement S that are not marked as unextractable, the server determines these expressions exp to be loop-invariant. Then, the server generates a new variable w, rewrites the expressions in S using variable w, and adds the previously determined loop-invariant expressions to the loop invariant set R. Then, for any expression exp in the loop invariant set R, the server calculates the extraction cost of the expression exp based on a cost function. Assuming the cost threshold K is 1, the server determines whether the expression can be extracted by comparing the extraction cost with the cost threshold. If the extraction cost is not less than the cost threshold K, and the server determines that extracting the expression exp has no side effects, i.e., it will not change other data, then the server can extract the expression exp from inside the loop body to outside the loop body. Optionally, the server can extract the expression to the preceding block of the loop. If the extraction cost is less than the cost threshold K, or the server determines that extracting the expression exp would change other data, then the server will not extract the expression exp and restore the expression to its form represented by the variable v. The value of this cost threshold is related to the target platform hardware, and this embodiment does not limit it.

[0128] For example, Figure 5 This is a flowchart illustrating the extraction of loop invariants according to an exemplary embodiment, such as... Figure 5 As shown. The instruction %var is a loop-invariant data loading instruction. Since the instruction %var is a loop invariant within the loop body, the server can extract the instruction outside the loop body, thus preventing redundant calculations due to loop iteration.

[0129] It should be noted that the above-described loop invariant extraction algorithm also considers the case of nested loops. For any variable in the first intermediate data, if the variable is determined to be a loop invariant in the innermost loop of the first intermediate data, the server can extract the variable if the extraction cost is not less than the cost threshold and the server determines that extracting the variable has no side effects. Then, the server will continue to determine whether the variable can be extracted in the outer loop. If the variable is determined to be a loop invariant in the outer loop, the server can extract the variable to the outside of that loop after determining that the extraction cost is not less than the cost threshold and the server determines that extracting the variable has no side effects. Then, the server continues to determine whether the variable is a loop invariant in the next loop, and extracts the variable if the extraction cost is not less than the cost threshold and the server determines that extracting the variable has no side effects. The server will determine whether the variable can be extracted in all loops of the first intermediate data until the variable is no longer a loop in the current loop, or the outermost loop has been determined, at which point the server will stop extracting the variable.

[0130] In step S305, the server optimizes the loop data.

[0131] In this embodiment, the server can optimize the loop data. Optionally, the server can first unroll the loop body in the loop data, and then optimize the loop data using a loop unrolling algorithm. The server's loop unrolling of the loop data can be divided into partial unrolling and full unrolling. If the loop unrolling coefficient of the loop data is less than the number of loop iterations, then the server can perform partial unrolling of the loop data; if there is no dependency between the consecutive iterations of the loop data, that is, each loop iteration does not affect the others, then the server can perform full unrolling of the loop data. By optimizing the loop data after unrolling, simplified loop data can be obtained, preparing for the subsequent construction of a fan-out tree for the loop invariants that generate fan-out.

[0132] In some embodiments, the loop unrolling algorithm includes three operations. Accordingly, the server performs any combination of the first operations on the loop data in a preset order. Then, the server performs any combination of the second operations on the loop data in a preset order. Finally, the server performs any combination of the third operations on the loop data in a preset order. The first operation includes iteratively stripping the loop block, calculating the loop count, calculating the unrolling coefficient, and performing iterative operations on the head or tail. The second operation includes copying the basic block, remapping instructions, updating PHI nodes, and connecting jump instructions between basic blocks. The third operation includes updating the SE scalar evolution, updating the DT dominator tree, updating the LI loop information, performing LCSSA format protection, deleting dead instructions and simplifying instructions, and merging adjacent basic blocks.

[0133] For example, Figure 6 This is a schematic diagram illustrating the partial and complete unfolding of a loop body according to an exemplary embodiment, as shown below. Figure 6 As shown. Figure 6 (a) in the diagram is a partial expansion diagram. When the expansion coefficient of the loop data is less than the number of loop iterations, the server can partially expand the loop body in the loop data. Figure 6 (b) in the diagram is a fully expanded diagram. When there is no dependency between successive iterations of the loop data, the server can fully expand the loop body in the loop data and execute all iterations simultaneously within a single clock cycle.

[0134] Figure 7 This is a schematic diagram illustrating three operations of a loop unrolling algorithm according to an exemplary embodiment, as shown below. Figure 7 As shown, optimization is performed on the loop data. The three operations of the loop unrolling algorithm are described in detail below.

[0135] The server performs any combination of first operations on the loop data according to a preset order. The first operations include iteratively stripping the loop body, calculating the loop count, calculating the expansion coefficient, and performing iterative operations at the beginning or end. First, the server iteratively strips the loop body of the loop data. Since the first few iterations or the last few iterations in the loop body may contain some special processing, the server can strip out these special iterations, making the original loop's regularity more obvious. Then, the server can calculate the loop count and expansion coefficient of the loop data. Then, when the loop count cannot divide the expansion coefficient evenly, the server can iteratively strip out the loop body that cannot be divided evenly and perform the remaining iterations at the beginning or end. It should be noted that other orders or arbitrary combinations of the first operations can also be used, and this embodiment does not limit this.

[0136] For example, Figure 8This is a schematic diagram illustrating the head or tail residual iteration according to an exemplary embodiment, such as... Figure 8 As shown. When the loop count of the loop data cannot be evenly divided by the loop expansion coefficient, the server can perform either a head-end or tail-end remainder iteration on the loop body that cannot be divided evenly, based on the integer part and the remainder part obtained after division. Specifically, the head-end remainder iteration executes the loop body of the integer part first, and then executes the loop body of the remainder part. The tail-end remainder iteration executes the loop body of the remainder part first, and then executes the loop body of the integer part.

[0137] The server performs any combination of second operations on the circular data in a preset order. These second operations include copying basic blocks, remapping instructions, updating PHI nodes, and connecting jump instructions between basic blocks. First, the server copies the basic blocks in the circular data. Since copying the basic blocks means copying all instructions in the circular data, but the operands in the copied instructions still use variables defined in the source code, the server needs to remap the operands in the circular data to ensure the validity and accuracy of variable definitions and usage paths. Optionally, the server can remap instructions by establishing a hash table data structure. After copying the basic blocks of the circular data, the server iterates through all instructions in the copied basic blocks, and for any instruction, replaces its operands based on the hash table. The hash table is established within the `CloneBasicBlock()` function, which is used to copy instructions while simultaneously creating a mapping between the source instructions and the newly copied instructions. Since the server copies the basic blocks of the loop data, the PHI node needs to be updated. Because a variable may come from different basic blocks, the PHI node can be used to select variables from different branches. Then, the server performs jump instruction operations between basic blocks connecting the loop data. Since the server can perform loop unrolling of the loop body based on either partial or full unrolling, it performs jump instruction operations between basic blocks that connect the loop data based on different unrolling scenarios. When the server partially unrolls the loop body, it iterates through all latches in the loop data. For any latch, the server modifies the jump instruction pointing to the loop head to point to the next unrolled basic block. When the server fully unrolls the loop body, for any basic block in the loop data, it modifies the jump instruction of that basic block to point to the next unrolled basic block, and modifies the jump instruction of the last iteration's basic block to point to the exit block. It should be noted that other orders or arbitrary combinations of these operations can also be used, and this embodiment does not limit this.

[0138] Figure 9 This is a schematic diagram illustrating instruction remapping according to an exemplary embodiment, such as... Figure 9 As shown. Figure 9 (a) in the text represents the original basic block. Figure 9 (b) in the diagram represents the copied basic block. Figure 9 The instructions included in (a) are all related to Figure 9 In (b) of the instruction set, the mapping is based on a hash table data structure. Therefore, after the CloneBasicBlock() function performs the basic block copy, it iterates through... Figure 9 (b) includes the instruction %5 = add nuw nsw i32%, 01, 1. When iterating to this instruction, the server determines that the operand %.01 in the instruction is not in the context of the previous instruction. Figure 9 (b) in the example is not defined in the copied basic block, but comes from... Figure 9 (a) in the example. Therefore, the server queries the hash table to determine the correspondence between %.01 and (a). Figure 9 In (b) of the instruction, %.01.100 is used. Then, the server replaces the operands, thus remapping the instruction.

[0139] Figure 10 This is a schematic diagram illustrating a jump instruction between basic connection blocks according to an exemplary embodiment, such as... Figure 10 As shown. Figure 10 (a) in the diagram is a schematic of the jump instructions between basic blocks when they are not expanded in the original form; Figure 10 (b) in the diagram is a schematic diagram of the jump instruction between basic blocks when partially expanded. The server modifies the jump instruction in the latch of the loop data, which originally pointed to the beginning of the loop, to point to the next basic block to be expanded. Figure 10 (c) in the diagram is a schematic diagram of the jump instructions between basic blocks when fully expanded. The server modifies the jump instructions of all basic blocks except the last basic block to point to the next expanded basic block, and the jump instruction of the last basic block points to the exit block.

[0140] The server performs any combination of third operations on the loop data in a preset order. These third operations include updating the SE scalar evolution, updating the DT dominator tree, updating the LI loop information, performing LCSSA format protection, deleting dead instructions and simplifying instructions, and merging adjacent basic blocks. First, the server updates the SE scalar evolution of the loop data after loop unrolling. Then, the server updates the DT dominator tree and LI loop information, and deletes dead instructions. Next, the server merges adjacent basic blocks. Optionally, the server can merge basic blocks without code, or it can merge basic blocks with bidirectional relationships, i.e., the unique successor of the previous basic block is the next basic block, and the unique predecessor of the next basic block is the previous basic block. Finally, the server simplifies the loop body in the loop data. Through these operations, the server can optimize the loop data. It should be noted that other orders or arbitrary combinations of the third operations can also be used, and this embodiment does not limit this.

[0141] In step S306, for any loop invariant, the server replaces the first operand in the first intermediate data based on the fan-out tree of the loop invariant to obtain the second intermediate data. The first operand represents the operand of the loop invariant in the expanded loop data.

[0142] In this embodiment, for any cyclic invariant whose fan-out count exceeds a fan-out threshold, the server can construct a fan-out tree for the cyclic invariant and then replace the first operand with a second operand to obtain second intermediate data. Here, the first operand represents the operand corresponding to the cyclic invariant in the cyclic data, and the second operand represents the operand indicated by the associated node of the constructed fan-out tree. By constructing a fan-out tree for the cyclic invariant that is fanning out, the fan-out count of the cyclic invariant can be made less than the fan-out threshold. Furthermore, by obtaining optimized second intermediate data, the target circuit obtained based on the second intermediate data satisfies timing constraints, thereby improving the performance of the target circuit.

[0143] In some embodiments, the server constructs a fan-out tree for loop invariants outside or inside the loop body. When constructing the fan-out tree for loop invariants inside the loop body, the server replaces the operands corresponding to the loop invariants in the loop with the operands indicated by the associated nodes of the constructed fan-out tree. Accordingly, for any loop invariant, the server constructs a fan-out tree for the loop invariant outside the loop body in the loop data. Then, inside the loop body in the loop data, the server replaces the first operand corresponding to the loop invariant in the operation instruction with a second operand. By constructing a fan-out tree for loop invariants outside or inside the loop body, the fan-out number of loop invariants is reduced, and the fan-out of each associated node of the resulting fan-out tree satisfies the fan-out threshold constraint.

[0144] In some embodiments, the server can construct a fan-out tree for loop invariants outside the loop body in the loop data based on a fan-out constraint coefficient or a node fan-out value. Accordingly, the server constructs a fan-out tree for loop invariants outside the loop body in the loop data based on a fan-out constraint coefficient, or the server constructs a fan-out tree for loop invariants outside the loop body in the loop data based on a node fan-out value. The fan-out constraint coefficient is used to limit the number of associated nodes in the fan-out tree, and the node fan-out value is used to limit the number of levels in the fan-out tree. By constructing a fan-out tree for loop invariants outside the loop body based on a fan-out constraint coefficient or a node fan-out value, the number of fan-outs of the loop invariants is reduced, ensuring that the fan-out of each node in the resulting fan-out tree satisfies the fan-out threshold constraint.

[0145] It should be noted that the fan-out value of this node is the fan-out value of each associated node in the preset fan-out tree. If the fan-out value of any associated node in the fan-out tree is greater than the node's fan-out value, then a node in the next level associated with that associated node is constructed. If the fan-out value of the associated node is still greater than the node's fan-out value, then a new node in the next level associated with that node is constructed, until the fan-out value of the associated node is less than the node's fan-out value. This allows us to obtain the number of nodes associated with that node and the number of levels in the fan-out tree. By limiting the number of associated nodes constructed based on the node's fan-out value, the number of levels in the fan-out tree is limited, ensuring that the fan-out of each associated node in the fan-out tree satisfies the fan-out threshold constraint.

[0146] For example, Figure 11 This is a schematic diagram illustrating the circuitry before and after constructing a fan-out tree according to an exemplary embodiment, such as... Figure 11 As shown. Figure 11 (a) in the diagram is a schematic diagram of the circuit before the fan-out tree is constructed. The number of fan-out nodes at the top is 4. Figure 11 (b) is a schematic diagram of the circuit before the fan-out tree is constructed. The fan-out tree is constructed on the topmost fan-out node, which reduces the number of fan-outs of that node and keeps the fan-out of each node within the fan-out threshold constraint. This will reduce the wire delay when the target circuit is actually laid out and routed.

[0147] For example, Figure 12 This is a schematic diagram illustrating a comparison between first intermediate data and second intermediate data according to an exemplary embodiment, such as... Figure 12 As shown. Figure 12 (a) in the figure represents the first intermediate data before optimization. The number of iterations is large, resulting in excessive fan-out, which affects the design of the target circuit. Figure 12In the first intermediate data, (b) represents the optimized second intermediate data. By optimizing the loop data in the first intermediate data, the server obtained several loops with a smaller number of iterations, which simplified the loop process, solved the problem of excessive fan-out, and improved the working performance of the target circuit.

[0148] In step S307, the server generates second circuit data based on the second intermediate data. The second circuit data is data describing the logical structure of the target circuit using a second programming language.

[0149] In this embodiment, the server constructs a fan-out tree for loop invariants inside or outside the loop body, reducing the fan-out number of loop invariants and thus obtaining second intermediate data with a fan-out number less than the fan-out threshold. The server then transmits this second intermediate data to the backend of the HLS compiler to generate second circuit data. This second circuit data can be described using RTL code, and the target circuit generated from the second circuit data satisfies timing constraints and has improved performance compared to the target circuit generated from the first circuit data.

[0150] For example, Figure 13 This is a flowchart illustrating the process of obtaining second circuit data according to an exemplary embodiment, such as... Figure 13 As shown, the process includes the following steps: 1301. The server compiles the first circuit data using the HLS compiler to obtain the first intermediate data. 1302. For any loop data in the first intermediate data, the server obtains the total number of iterations and the loop unrolling coefficient of the loop data. 1303. Based on the obtained total number of iterations and loop unrolling coefficient, the server determines whether the loop data has an excessive fan-out problem. If the loop data has an excessive fan-out problem, steps 1304 to 1307 are executed. 1304. The server obtains the loop invariants from the loop data. 1305. The server extracts the loop invariants from inside the loop body of the loop data to outside the loop body. 1306. The server optimizes the loop data. 1307. The server constructs a fan-out tree for the loop invariants that have fan-out, replaces the first operand with the second operand, and obtains the second intermediate data. If the loop data does not have an excessive fan-out problem, step 1308 is executed. 1308. The server performs a default loop unrolling operation on the loop data using the HLS compiler to generate the second circuit data. 1309. The server generates second circuit data based on the second intermediate data.

[0151] This disclosure provides a data processing method. By compiling first circuit data, first intermediate data is obtained. Since the first intermediate data may contain cyclic invariants that fan out, which may affect the design of the target circuit, a fan-out tree is constructed in the intermediate representation layer for each cyclic invariant whose fan-out number is greater than the fan-out threshold. Based on the associated nodes of the constructed fan-out tree, the operands corresponding to each cyclic invariant in the loop are replaced to obtain second intermediate data. This reduces the fan-out number of cyclic invariants, thereby solving the problem of high fan-out.

[0152] Figure 14 This is a block diagram illustrating a data processing apparatus according to an exemplary embodiment, see below. Figure 14 As shown, the device includes a compilation unit 1401, a replacement unit 1402, and a generation unit 1403.

[0153] The compilation unit 1401 is configured to compile the first circuit data to obtain the first intermediate data. The first circuit data is data describing the logic structure of the target circuit through the first programming language, and the first intermediate data is data describing the logic structure of the target circuit through the intermediate code language.

[0154] Replacement unit 1402 is configured to replace the first operand in the first intermediate data with the first operand based on the fan-out tree of each cyclic invariant in the first intermediate data for each cyclic invariant whose fan-out number is greater than the fan-out threshold, to obtain the second intermediate data. Cyclic invariant refers to a variable whose value does not change with the iteration of the loop. The node of the fan-out tree of any cyclic invariant is used to represent any cyclic invariant. The first operand represents the operand corresponding to the cyclic invariant in the cyclic data to which it belongs.

[0155] The generation unit 1403 is configured to generate second circuit data based on second intermediate data, wherein the second circuit data is data describing the logic structure of the target circuit using a second programming language.

[0156] In some embodiments, the replacement unit 1402 is configured to, for any loop data in the first intermediate data, obtain the total number of loop iterations and the loop unrolling coefficient of the loop data, the loop unrolling coefficient being used to represent the number of copies of the loop body; and, if the ratio of the total number of loop iterations to the loop unrolling coefficient is greater than a target threshold, replace the first operand based on the fan-out tree of each loop invariant in the loop data.

[0157] In some embodiments, Figure 15 This is a block diagram illustrating another data processing apparatus according to an exemplary embodiment, see [link to example diagram]. Figure 15 As shown, the replacement unit 1402 further includes:

[0158] The identification subunit 14021 is configured to identify cyclic invariants in cyclic data to obtain at least one cyclic invariant.

[0159] Extraction subunit 14022 is configured to extract at least one loop invariant from the inside of the loop body in the loop data to the outside of the loop body;

[0160] Optimization subunit 14023 is configured to perform loop expansion on the loop data;

[0161] Subunit 14024 is configured to replace the first operand with the second operand for any loop invariant, where the second operand represents the operand indicated by the associated node of the fan-out tree.

[0162] In some embodiments, the identification subunit 14021 is configured to determine latches in loop data; for any variable in the latch, the operands in multiple instructions of the loop body are traversed recursively to obtain multiple variable recursion results for the variable; in response to multiple variable recursion results being true, the variable is determined to be a loop invariant.

[0163] In some embodiments, the identification subunit 14021 is configured to identify any variable in the loop data as a loop invariant if the variable is defined and assigned outside the loop body and used inside the loop body.

[0164] In some embodiments, the extraction subunit 14022 is configured to traverse the loop body of the loop data in a depth-first order to obtain a set of loop invariants, the set of loop invariants including at least one loop-invariant expression; for any expression in the set of loop invariants, the extraction cost of the expression is determined, the extraction cost representing the degree of influence of the extracted expression on the loop data; if the extraction cost is not less than the cost threshold, the expression is extracted as a loop invariant to the outside of the loop body.

[0165] In some embodiments, the optimization subunit 14023 is configured to perform any combination of first operations on the loop data in a preset order, the first operations including iteratively stripping the loop block, calculating the number of loops, calculating the expansion coefficient, and performing iterative operations at the beginning or end; perform any combination of second operations on the loop data in a preset order, the second operations including copying the basic block, remapping instructions, updating PHI nodes, and connecting jump instructions between basic blocks; and perform any combination of third operations on the loop data in a preset order, the third operations including updating the SE scalar evolution, updating the DT dominator tree, updating the LI loop information, performing LCSSA format protection, deleting dead instructions and simplifying instructions, and merging adjacent basic blocks.

[0166] In some embodiments, the replacement subunit 14024 is configured to, for any loop invariant, construct a fan-out tree for the loop invariant outside the loop body in the loop data; and inside the loop body in the loop data, replace the first operand corresponding to the loop invariant in the replacement operation instruction with the second operand.

[0167] In some embodiments, the replacement subunit 14024 is further configured to construct a fan-out tree for loop invariants outside the loop body in the loop data based on fan-out constraint coefficients, wherein the fan-out constraint coefficients are used to limit the number of associated nodes in the fan-out tree; or, based on node fan-out values, to construct a fan-out tree for loop invariants outside the loop body in the loop data, wherein the node fan-out values ​​are used to limit the number of levels in the fan-out tree.

[0168] This disclosure provides a data processing apparatus that compiles first circuit data to obtain first intermediate data. Since the first intermediate data may contain cyclic invariants that fan out, which may affect the design of the target circuit, a fan-out tree is constructed in the intermediate representation layer for each cyclic invariant whose fan-out number is greater than the fan-out threshold. The operands corresponding to each cyclic invariant in the loop are replaced based on the associated nodes of the constructed fan-out tree to obtain second intermediate data. This reduces the fan-out number of cyclic invariants, thereby solving the problem of high fan-out.

[0169] Figure 16 This is a block diagram illustrating an electronic device 1600 according to an exemplary embodiment. Typically, the electronic device 1600 includes a processor 1601 and a memory 1602.

[0170] Processor 1601 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1601 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1601 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1601 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1601 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0171] The memory 1602 may include one or more computer-readable storage media, which may be non-transitory. The memory 1602 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1602 are used to store at least one program code, which is executed by the processor 1601 to implement the data processing method provided in the method embodiments of this disclosure.

[0172] In some embodiments, the electronic device 1600 may optionally include a peripheral device interface 1603 and at least one peripheral device. The processor 1601, memory 1602, and peripheral device interface 1603 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 1603 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of the following: radio frequency circuitry 1604, display screen 1605, camera assembly 1606, audio circuitry 1607, and power supply 1608.

[0173] Peripheral interface 1603 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 1601 and memory 1602. In some embodiments, processor 1601, memory 1602 and peripheral interface 1603 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 1601, memory 1602 and peripheral interface 1603 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0174] The radio frequency (RF) circuit 1604 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 1604 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 1604 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals back into electrical signals. Optionally, the RF circuit 1604 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The RF circuit 1604 can communicate with other electronic devices through at least one wireless communication protocol. This wireless communication protocol includes, but is not limited to: metropolitan area networks (MANs), various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks (WLANs), and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 1604 may also include circuitry related to NFC (Near Field Communication), which is not limited in this disclosure.

[0175] Display screen 1605 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 1605 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 1601 for processing. In this case, display screen 1605 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 1605, which serves as the front panel of electronic device 1600; in other embodiments, there may be at least two display screens, respectively disposed on different surfaces of electronic device 1600 or in a folded design; in still other embodiments, display screen 1605 may be a flexible display screen, disposed on a curved or folded surface of electronic device 1600. Furthermore, display screen 1605 may also be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. The display screen 1605 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0176] The camera assembly 1606 is used to acquire images or videos. Optionally, the camera assembly 1606 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is located on the front panel of the electronic device, and the rear-facing camera is located on the back of the electronic device. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 1606 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm-light flash and a cool-light flash, which can be used for light compensation at different color temperatures.

[0177] The audio circuit 1607 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, converting the sound waves into electrical signals that are input to the processor 1601 for processing, or input to the radio frequency circuit 1604 for voice communication. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each located in a different part of the electronic device 1600. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert electrical signals from the processor 1601 or the radio frequency circuit 1604 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 1607 may also include a headphone jack.

[0178] Power supply 1608 is used to power the various components in electronic device 1600. Power supply 1608 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 1608 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0179] Those skilled in the art will understand that Figure 16 The structure shown does not constitute a limitation on the electronic device 1600, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0180] When a computer device is configured as a server, Figure 17 This is a schematic diagram of a server structure according to an exemplary embodiment. The server 1700 can vary significantly due to different configurations or performance. It may include one or more Central Processing Units (CPUs) 1701 and one or more memories 1702. The memories 1702 store at least one computer program, which is loaded and executed by the processor 1701 to implement the data processing methods provided in the various method embodiments described above. Of course, the server may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server may also include other components for implementing device functions, which will not be elaborated here.

[0181] In an exemplary embodiment, a computer-readable storage medium including instructions is also provided, such as a memory 1602 including instructions, which can be executed by a processor 1601 of an electronic device 1600 to complete the above-described data processing method. Optionally, the computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0182] In an exemplary embodiment, a chip is also provided, the chip including a processor and a memory, the processor being used to store processor-executable instructions in the memory, the processor being configured to execute the instructions to implement the data processing method described above.

[0183] In an exemplary embodiment, a computer program product is also provided, including a computer program that, when executed by a processor, implements the above-described data processing method.

[0184] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0185] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A data processing method, characterized in that, The method includes: The first circuit data is compiled to obtain the first intermediate data. The first circuit data is data describing the logical structure of the target circuit using a first programming language. The first intermediate data is data describing the logical structure of the target circuit using an intermediate code language. For any loop data in the first intermediate data, obtain the total number of loop iterations and the loop unrolling coefficient of the loop data, where the loop unrolling coefficient is used to represent the number of copies of the loop body; If the ratio of the total number of iterations to the loop expansion coefficient is greater than the target threshold, identify the loop invariants in the loop data to obtain at least one loop invariant. The loop invariant refers to a variable whose value does not change with the iteration of the loop. Extract the at least one cycle invariant from the inside of the cycle body in the cycle data to the outside of the cycle body; Optimize the loop data; For each cyclic invariant whose fan-out number is greater than the fan-out threshold, a fan-out tree is constructed outside the loop body in the cyclic data for the cyclic invariant. Inside the loop body in the cyclic data, the first operand corresponding to the cyclic invariant in the replacement operation instruction is replaced with the second operand to obtain the second intermediate data. The nodes of the fan-out tree of any cyclic invariant are used to represent any cyclic invariant. The first operand represents the operand corresponding to the cyclic invariant in its respective cyclic data, and the second operand represents the operand indicated by the associated node of the fan-out tree. Second circuit data is generated based on the second intermediate data. The second circuit data is data describing the logical structure of the target circuit using a second programming language.

2. The data processing method according to claim 1, characterized in that, The process of identifying cyclic invariants in the cyclic data to obtain at least one cyclic invariant includes: Identify the latches in the cyclic data; For any variable in the latch, the operands in multiple instructions of the loop body are traversed recursively to obtain multiple variable recursion results for the variable. If all the recursive results of the multiple variables are true, the variables are determined to be loop invariants.

3. The data processing method according to claim 1, characterized in that, The process of identifying cyclic invariants in the cyclic data to obtain at least one cyclic invariant includes: For any variable in the loop data, if the variable is defined and assigned a value outside the loop body, and the variable is used inside the loop body, the variable is determined as a loop invariant.

4. The data processing method according to claim 1, characterized in that, The step of extracting the at least one loop invariant from inside the loop body of the loop data to outside the loop body includes: Traverse the loop body of the loop data in depth-first order to obtain a set of loop invariants, the set of loop invariants including at least one loop-invariant expression; For any expression in the set of loop invariants, determine the extraction cost of the expression, where the extraction cost represents the degree of influence of extracting the expression on the loop data; If the extraction cost is not less than the cost threshold, the expression is extracted as a loop invariant outside the loop body.

5. The data processing method according to claim 1, characterized in that, The optimization of the loop data includes: Any combination of first operations performed on the loop data in a preset order, wherein the first operation includes iteratively stripping the loop block, calculating the number of loops, calculating the expansion coefficient, and performing iterative operations at the beginning or end; Any combination of second operations is performed on the loop data in a preset order. The second operation includes copying basic blocks, remapping instructions, updating PHI nodes, and connecting jump instructions between basic blocks. Any combination of third operations is performed on the cyclic data in a preset order. The third operations include updating the SE scalar evolution, updating the DT dominator tree, updating the LI cycle information, performing LCSSA format protection, deleting death instructions and instruction simplification, and merging adjacent basic blocks.

6. The data processing method according to claim 1, characterized in that, The construction of a fan-out tree for the loop invariants outside the loop body in the loop data includes: Based on the fan-out constraint coefficient, a fan-out tree is constructed outside the loop body in the loop data for the loop invariants, and the fan-out constraint coefficient is used to limit the number of associated nodes in the fan-out tree; or... Based on the node fanout value, a fanout tree is constructed outside the loop body in the loop data for the loop invariant, and the node fanout value is used to limit the number of layers of the fanout tree.

7. A data processing apparatus, characterized in that, The device includes: The compilation unit is configured to compile the first circuit data to obtain the first intermediate data, wherein the first circuit data is data describing the logical structure of the target circuit using a first programming language, and the first intermediate data is data describing the logical structure of the target circuit using an intermediate code language. The replacement unit is configured to, for any loop data in the first intermediate data, obtain the total number of loop iterations and the loop unrolling coefficient of the loop data, wherein the loop unrolling coefficient is used to represent the number of copies of the loop body; if the ratio of the total number of loop iterations to the loop unrolling coefficient is greater than a target threshold, identify loop invariants in the loop data to obtain at least one loop invariant, wherein the loop invariant is a variable whose value does not change with the iteration of the loop; extract the at least one loop invariant from the inside of the loop body in the loop data to the outside of the loop body; optimize the loop data; for each loop invariant whose fan-out number is greater than a fan-out threshold, construct a fan-out tree for the loop invariant outside the loop body in the loop data, and inside the loop body in the loop data, replace the first operand corresponding to the loop invariant in the replacement operation instruction with a second operand to obtain second intermediate data, wherein the nodes of the fan-out tree of any loop invariant are used to represent the any loop invariant, the first operand represents the operand corresponding to the loop invariant in its respective loop data, and the second operand represents the operand indicated by the associated node of the fan-out tree; The generation unit is configured to generate second circuit data based on the second intermediate data, wherein the second circuit data is data describing the logical structure of the target circuit using a second programming language.

8. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the data processing method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, wherein when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the data processing method as described in any one of claims 1 to 6.

10. A chip, characterized in that, The chip includes a processor and a memory, the processor being used to store processor-executable instructions in the memory, the processor being configured to execute the instructions to implement the data processing method as described in any one of claims 1 to 6.

Images