Mapping method of solid state disk and solid state disk

Abstract

Disclosed are a mapping method of a solid state disk and the solid state disk. The solid state disk comprises a plurality of flash memory chips, respectively communicates with a flash memory controller in a controller through a plurality of channels, each channel corresponds to one to more chip select pins, and each chip select pin controls one to more physical dies. The mapping method comprises the following steps: obtaining a physical address of each physical die on the flash memory chip, wherein the physical address is represented by a channel number, a chip select pin number and a LUN number corresponding to the physical die; obtaining the number of physical dies, and establishing a logical address of the physical die according to the number; storing a mapping relationship between the logical address and the physical address as a first mapping table; establishing a second mapping table between a host and the solid state disk based on the logical address; and obtaining the physical address of the physical die according to the second mapping table and the first mapping table. According to the mapping method, the physical address of the physical die can be obtained according to the mapping relationship, the second mapping table is established only once, the firmware has good applicability, and the data access time is saved.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a mapping method for solid-state drives (SSDs) and a solid-state drive. Background Technology

[0002] Solid-state drives (SSDs) are hard drives made with solid-state electronic storage chips, mainly composed of a controller, storage media, and cache units. Currently, the most common SSDs use flash memory as the storage medium for data storage.

[0003] Figure 1 A schematic block diagram of a solid-state drive is shown, such as... Figure 1 The solid-state drive 100 includes a controller 120 and a storage medium 130. The storage medium includes multiple flash memory chips 131, which are packaged on a circuit board 140 of the solid-state drive 100. The controller 120 is connected to the host 101 via an interface 110 for external communication. The controller 120 includes a CPU 121, memory 122, and a flash memory controller 123. The CPU 121 is connected to the memory 122 and the flash memory controller 123. The flash memory controller 123 is connected to multiple flash memory chips 131 via multiple channels, and writes data into the flash memory chips 131 according to the control of the CPU 121. Channels are as follows: Figure 1 The channels are ordered sequentially as CH0, CH1, CH2, and CH3. Each channel's corresponding flash memory chip 131 contains one or more chip enable pins (CE). Each chip enable pin controls one or more DIEs. Therefore, a flash memory chip 131 includes multiple DIEs (Logical Units, the smallest concurrent operation unit in a flash memory chip that can independently execute commands and report command execution status, also known as LUNs).

[0004] In existing technology, the flash memory chips 131 packaged on the solid-state drive 100 are of the same type, and each flash memory chip 131 corresponds to one channel. The firmware of existing solid-state drives requires that the DIEs on the flash memory chips 131 be physically aligned during surface mounting (i.e., each DIE is located on the same CE on different CHs). If a DIE is mounted abnormally, the entire firmware will fail to function, resulting in rework. Therefore, current solid-state drives have poor applicability to PCB surface mounting, resulting in low drive quality. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a mapping method for solid-state drives and a solid-state drive, so as to solve the problems existing in the prior art.

[0006] According to one aspect of the present invention, a mapping method for a solid-state drive (SSD) is provided. The SSD includes a controller and a plurality of flash memory chips. The plurality of flash memory chips communicate with a flash memory controller within the controller through a plurality of channels. Each channel corresponds to one or more chip select pins in each flash memory chip. Each chip select pin controls one or more physical DIEs. The mapping method includes:

[0007] Obtain the physical address of each physical DIE on the flash memory chip. The physical address is characterized by the channel number, chip select pin number and LUN number corresponding to the physical DIE.

[0008] Obtain the number of physical DIEs and establish the logical address of each physical DIE accordingly;

[0009] Establish a mapping relationship between the logical address of the physical DIE and the physical address of the physical DIE, and store it as a first mapping table;

[0010] A second mapping table between the host and the solid-state drive is established based on the logical address of the physical DIE;

[0011] In response to the host's access request, the physical address of the physical DIE is obtained according to the second mapping table and the first mapping table.

[0012] Optionally, before the step of obtaining the physical address of each physical DIE on the flash memory chip, the method further includes:

[0013] The package type of the flash memory chip is selected based on the number of physical DIEs that need to be selected and the number of package slots on the solid-state drive that can be used to package the flash memory chip.

[0014] Optionally, the step of obtaining the physical address of each physical DIE on the flash memory chip includes:

[0015] Locate the physical DIE on the flash memory chip and read its corresponding channel number and chip select pin number;

[0016] Read the information of the flash memory chip and record the LUN number according to the number of DIEs contained in the flash memory chip.

[0017] Optionally, if each flash memory chip contains only one DIE, the LUN number is 0 by default; if each flash memory chip contains multiple DIEs, the LUN number corresponds to the actual LUN bit value where the physical DIE is located.

[0018] Optionally, the package type includes SDP, DDP, QDP, and ODP.

[0019] Optionally, the chip select pin numbers corresponding to the physical DIEs under different channel numbers are not exactly the same.

[0020] Optionally, multiple physical DIEs may not completely occupy each of the channels.

[0021] Optionally, when establishing the first mapping table, if multiple chip select pins under a certain channel correspond to physical DIEs, a mapping relationship is first established for each channel in sequence, and then a mapping relationship is established for the multiple physical DIEs under that channel.

[0022] Optionally, establishing a mapping relationship for each channel sequentially and then establishing a mapping relationship for multiple physical DIEs under that channel includes: first assigning a logical address to the physical DIE under the first chip select pin of each channel according to the channel number; and then assigning a logical address to multiple physical DIEs under the same channel according to the chip select pin number.

[0023] According to another aspect of the present invention, a solid-state drive (SSD) is provided for performing the above-described mapping method, wherein the SSD comprises:

[0024] A controller, connected to and communicating with a host, the controller including a flash memory controller; and

[0025] Multiple flash memory chips are connected to the flash memory controller via multiple channels. Each flash memory chip includes one or more physical DIEs. Each channel corresponds to one or more chip select pins in each flash memory chip, and each chip select pin controls one or more physical DIEs.

[0026] Among them, the chip select pin numbers corresponding to the physical DIEs on multiple flash memory chips are not exactly the same under different channels.

[0027] Optionally, the multiple flash memory chips packaged on the solid-state drive include one or more of SDP, DDP, QDP and ODP.

[0028] Optionally, in a subset of the flash memory chips, each chip select pin controls only one DIE, while in another subset, each chip select pin controls multiple DIEs.

[0029] The solid-state drive (SSD) mapping method and SSD provided by this invention establish a mapping relationship between the host and the SSD using the logical address of the physical die as a second mapping table, and establish a mapping relationship between the logical address and the physical address of the physical die as a first mapping table. This allows the physical address of the physical die to be obtained solely based on the mapping relationship, without needing to consider the physical distribution of the physical die on the flash memory chip, resulting in better firmware applicability. When accessing the flash memory chip is required, the physical address of the physical die can be read by sequentially referring to the second and first mapping tables, eliminating the need for multiple changes to the mapping relationship between the host and the flash memory chip, saving storage space and improving data reading efficiency. Furthermore, using the channel-chip select pin and LUN bit value to mark the physical address of the physical die allows for accurate location of each physical die on the flash memory chip, without considering the influence of different chip package types, improving the stability of data storage and the diversity of surface mount devices on the SSD.

[0030] Furthermore, packaging different types of flash memory chips on the same solid-state drive, especially DDP, QDP, etc., can save on packaging inventory, increase the number of DIEs available, expand storage space, and improve the fault tolerance rate of surface mount technology. If a surface mount error occurs in a DIE, it can be replaced by another DIE without multiple reworks, thus improving production line and work efficiency. Attached Figure Description

[0031] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0032] Figure 1 A schematic block diagram of a solid-state drive is shown.

[0033] Figure 2a and Figure 2b Two schematic block diagrams of flash memory chips in solid-state drives are shown respectively;

[0034] Figure 3 This diagram illustrates the overall distribution of channels and chip select signals on flash memory chips in a traditional solid-state drive.

[0035] Figure 4 A simplified schematic diagram of a circuit board for a solid-state drive according to an embodiment of the present invention is shown;

[0036] Figure 5 A flowchart illustrating a solid-state drive mapping method according to an embodiment of the present invention is shown;

[0037] Figure 6 It shows Figure 5 Flowchart of step S102;

[0038] Figure 7 A simplified schematic diagram showing the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a first embodiment of the present invention is shown.

[0039] Figure 8 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a second embodiment of the present invention is shown.

[0040] Figure 9 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a third embodiment of the present invention is shown.

[0041] Figure 10 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a fourth embodiment of the present invention is shown.

[0042] Figure 11 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a fifth embodiment of the present invention is shown.

[0043] Figure 12 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a sixth embodiment of the present invention is shown.

[0044] Figure 13 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a seventh embodiment of the present invention is shown. Detailed Implementation

[0045] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0046] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0047] Unless the context explicitly requires it, the terms "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than exclusive or exhaustive; that is, meaning "including but not limited to." In the description of this invention, it should be understood that terms such as "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0048] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0049] Figure 2a and Figure 2b Two schematic block diagrams of flash memory chips in solid-state drives are shown respectively.

[0050] like Figure 1 As shown, the solid-state drive 100 is packaged with multiple flash memory chips 131. Figure 2a Provide one example. For example... Figure 2a As shown, taking the flash memory chip 131 corresponding to channel CH0 as an example, channel CH0 corresponds to two chip select pins (CE0 and CE1). The packaged flash memory chip 131 contains two targets (Target 0 and Target 1). Typically, one target contains one or more LUNs, and these LUNs share a set of data signals. Each target is controlled by a CE (Chip Enable) pin, meaning that several LUNs on one target share one CE signal. Figure 2a In the given flash memory chip 131, one package contains two targets, each target contains only one LUN (LUN0), each target has an independent data interface, and each target is controlled by a chip select pin CE. Therefore, Figure 2a In the example, one CE corresponds to a single-LUN. A LUN, also known as a DIE, is the smallest independent unit in flash memory that can execute commands and report its own status, i.e., the smallest basic unit of communication.

[0051] Figure 2a The right side shows the internal structure of each LUN. Each DIE (LUN) contains several Planes (operation planes) (e.g., two, Plane0 and Plane1). Each Plane contains several Blocks (physical blocks). Each Block contains multiple Pages (physical pages). A Block is the smallest unit of an erase operation, and a Page is the smallest unit of a read / write operation.

[0052] like Figure 2b This is another example of the 131 flash memory chip. Figure 2b In this architecture, each package contains four targets, and each target contains four LUNs. Each target has an independent data interface, but the four LUNs within each target share a set of data interfaces, controlled by a single CE (Controller Edge). That is, one CE corresponds to a multi-LUN. In the following description, we will distinguish between single-LUN chips and multi-LUN chips. Figure 2a and Figure 2b Two types of flash memory chips, 131.

[0053] Figure 3 This diagram illustrates the overall distribution of channels and chip select signals on a flash memory chip in a traditional solid-state drive.

[0054] like Figure 3 As shown, the distribution of physical DIEs on a traditional solid-state drive is illustrated by taking a solid-state drive with four channels (CH0-CH3) and each channel CH corresponding to four chip select pins CE (CE0-CE3). Figure 3 In this configuration, each channel (CH) has two chip select pins (CE), and each CE has one physical die. Therefore, there are a total of eight physical dies on the hard drive, which exist as surface-mount components on the flash memory chips. Traditional solid-state drives (SSDs) firmware requires the PCB surface-mount components to conform to the physical location alignment of the flash memory (i.e., the physical dies on each chip are distributed on the same CE of each CH). Figure 3 Using flash memory chips of the same package type, and with the first two CEs of each channel being selected, and the first LUN under each selected CE being selected, the physical DIEs on each flash memory chip are aligned. While this method of surface mount assembly is convenient, has low requirements for the production line, and is easy to manage in terms of firmware, if a single surface mount chip malfunctions, the entire firmware will fail, requiring the replacement of the corresponding flash memory chip, resulting in low production efficiency. Furthermore, for solid-state drives of the same capacity, the CH / CE configuration of the flash memory chips is limited, leading to poor PCB surface mount applicability.

[0055] This invention improves the packaging method and physical DIE distribution method of solid-state drives (SSDs), and proposes a mapping method and a solid-state drive, which are described below with reference to the accompanying drawings.

[0056] Figure 4 A simplified schematic diagram of a solid-state drive circuit board according to an embodiment of the present invention is shown.

[0057] like Figure 4As shown, the solid-state drive 200 includes a controller 220 that communicates with a host (not shown) via an interface 210 to control data transmission and storage. The controller 220 internally includes a flash memory controller 223 for communicating with the flash memory chips. The circuit board 240 of the solid-state drive 200 has multiple package slots. Figure 4 The diagram shows two packaging slots, S1 and S2, where multiple flash memory chips of different or the same type can be packaged. Since there are only two slots, only two flash memory chips can be packaged. Each flash memory chip includes one or more physical DIEs, and each channel corresponds to one or more chip select pins in each flash memory chip. Each chip select pin controls one or more physical DIEs. The structure of the solid-state drive 200 in this embodiment is similar to... Figure 1 The solid-state drive 100 shown has a similar structure, and the similarities will not be described again.

[0058] Package type refers to the finished flash memory chip, including: SDP, DDP, QDP, and ODP. Currently, SDP, DDP, and QDP are commonly used. SDP (Single Die Package) means the flash memory chip has one CE (Chip Array) that can be connected to any channel; one SDP corresponds to one CH (Chip Array). DDP (Dual Die Package) means the flash memory chip has two CEs, which are connected to the same location in two channels. DDP is cross-channel. Figure 4 If there are two DDP packages in the empty slot, then one DDP corresponds to CH0 and CH2, and the other DDP corresponds to CH1 and CH3. QDP (Quad Die Package) refers to a flash memory chip with four CEs, which can connect to the chip's two channels. Each channel has two CEs. Figure 4 If there are two QDPs encapsulated in the middle, then the corresponding Figure 3 In the diagram, CH0 and CH1 connect to one QDP, and CH2 and CH3 connect to another QDP. ODP (Octuplus Die Package) refers to a flash memory chip with eight CEs, which can connect to two channels of the chip, with four CEs per channel, or connect to four channels, with two CEs per channel.

[0059] The solid-state drive 200 in this embodiment packages multiple flash memory chips, including one or more of SDP, DDP, QDP, and ODP, meaning it supports the mixed mounting of flash memory chips of different package types on the same PCB circuit board 240. For example, if the PCB supports mounting four packaged flash memory chips and requires selecting three physical dies, then it can mount three SDPs (occupying three empty slots) or one SDP and one DDP (occupying two empty slots), which is the mixed mounting of different package types. If the PCB only supports mounting two packaged flash memory chips, and three physical dies still need to be selected, then only one SDP and one DDP can be mounted.

[0060] The flash memory chip packaging on the solid-state drive 200 in this embodiment has a wide range of applicability. Specifically, when there are many physical dies that need to be selected, but few available slots, flash memory chips of different package types can be mixed and mounted (for example, if three physical dies need to be selected, but there are only two slots on the PCB for package mounting, then one DDP and one SDP can be mounted to meet the requirements). Additionally, when the SSD requires an odd number of N1 physical dies to be selected, but there are only an even number of N2 (N2 < N1) available slots on the PCB, a mixed mounting method of different package types can also be used. Therefore, the solid-state drive in this embodiment can support the fabrication of solid-state drives with fewer available slots on the circuit board. Furthermore, mixing flash memory chips of different package types can increase the number of selectable physical dies, thereby freeing up space for various firmware management functions.

[0061] Furthermore, when the solid-state drive 200 is packaged with the same type of flash memory chips, the chip select pin numbers corresponding to multiple physical dies under different channels are not completely the same, that is, they do not follow the physical alignment rules. For example, the physical die under CE1 is selected in CH0 and CH1, while CE0 is selected in CH2 and CH3. In this way, even if a chip has a problem, the physical die under other CEs of the same chip can be used to replace the faulty chip, reducing rework.

[0062] Furthermore, among the multiple flash memory chips packaged on the solid-state drive 200 in this embodiment, some flash memory chips control only one physical die per chip select pin, while others control multiple physical dies per chip select pin. Therefore, the solid-state drive 200 also supports the mixed mounting of single-LUN chips and multi-LUN chips.

[0063] In summary, the solid-state drive 200 of this invention improves upon traditional solid-state drives. For SSDs of the same capacity (with the same total number of physical dies), it allows for different LUN-CE-CH configurations and supports the mixed mounting of flash memory chips of different package types, thereby enhancing the applicability and increasing the capacity of the solid-state drive. When chip mounting anomalies occur, the position of the physical dies can be adjusted promptly, reducing rework, improving production efficiency, and increasing fault tolerance. Correspondingly, this invention also provides a solid-state drive mapping method, specifically in conjunction with the appendix... Figure 5-6 Please provide an explanation.

[0064] Figure 5 A flowchart illustrating a solid-state drive mapping method according to an embodiment of the present invention is shown.

[0065] In the solid-state drive (SSD) mapping method of this embodiment, after the SSD is powered on, a mapping relationship between the physical address and logical address of the physical DIE is first established. Then, when the firmware establishes the FTL (Flash Translation Layer, which maps the logical address of the host or user to the physical address of the flash memory) table, the mapping relationship is established using the logical address of the physical DIE. This ensures that the logical addresses are continuous, regardless of the actual location of the physical DIE. Before accessing the flash memory chip, the request needs to be converted to the actual channel and the physical address of the physical DIE. Therefore, with the mapping method of this embodiment, as long as the total number of physical DIEs on the SSD is consistent, the FTL does not need to be changed, while the location of the physical DIEs can be arbitrarily changed, resulting in strong chip adaptability.

[0066] Specifically, the solid-state drive mapping method in this embodiment includes the following steps:

[0067] In step S101, the package type of the flash memory chip is selected based on the number of physical DIEs that need to be selected and the number of package slots on the solid-state drive that can be used to package flash memory chips.

[0068] This step first determines how many physical dies need to be packaged on the SSD, and the types of flash memory chips that need to be packaged. Then, based on the required number of physical dies, and considering the available space on the SSD (see...),... Figure 4 The determination of the number and type of flash memory chips that can be packaged on a solid-state drive (SSD) has been previously discussed and will not be repeated here. Package types include SDP, DDP, QDP, and ODP. See [link to relevant documentation]. Figure 4 As described above, the solid-state drive in this embodiment can support the mixing of flash memory chips of different package types on the same circuit board.

[0069] In step S102, the physical address of each logical DIE on the flash memory chip is obtained. The physical address is characterized by the channel number, chip select pin number and LUN number corresponding to the physical DIE.

[0070] In this step, the physical location of the physical DIE (the actual location where the physical DIE exists on the flash memory chip) is obtained. We see which CH and which CE have the DIE and record them as a physical DIE. We also record the physical address of the physical DIE, which is the corresponding CH number, CE number and LUN number.

[0071] Figure 6 It shows Figure 5 The flowchart for step S102 is shown. Step S102 includes steps S1021-S1022. For example... Figure 6 As shown:

[0072] In step S1021, the physical DIEs on the flash memory chip are located, and their corresponding channel numbers and chip select pin numbers are read. In this step, N physical DIEs are first located, their physical locations are determined, and it is determined which CH and CE have a DIE. The CH and CE numbers corresponding to each physical DIE are recorded.

[0073] In step S1022, the information of the flash memory chip is read, and the LUN number is recorded according to the number of DIEs contained in the flash memory chip. In this step, if a physical DIE exists on a certain CH or CE, the information (ID) of the flash memory chip is read to determine whether the chip is a single-LUN chip or a multi-LUN chip. If each flash memory chip contains only one DIE (single-LUN), the LUN number defaults to 0; if each flash memory chip contains multiple physical DIEs (multi-LUN), the LUN number corresponds to the actual LUN bit value where the physical DIE is located (e.g., 0, 1, 2, 3, etc.). Thus, the physical location "LUN-CE-CH" is obtained.

[0074] Next, as Figure 5 In step S103, the number of physical DIEs is obtained, and the logical address of each physical DIE is established accordingly.

[0075] In this step, we first determine the actual number of physical DIEs selected on the solid-state drive, and then sort the multiple physical DIEs according to DIE0, DIE1, DIE2...DIEn. Then, the N physical DIEs correspond to DIE0 to DIE(N-1), which serve as the logical addresses of the N physical DIEs.

[0076] In step S104, a mapping relationship is established between the logical address of the physical DIE and the physical address of the physical DIE, and stored as a first mapping table.

[0077] In this step, a mapping relationship is constructed between the logical address (DIEn) of each physical DIE and its physical address (LUNy-CEm-CHx). That is, N physical addresses and N logical addresses are matched to establish a mapping relationship, which is stored as the first mapping table. For example, DIE0 corresponds to LUN0-CE0-CH0, DIE2 corresponds to LUN1-CE0-CH1, and so on. If the distribution of the same number (N) physical DIEs differs across different SSDs, the physical addresses of multiple physical DIEs on each SSD will vary. Therefore, the first mapping tables for different SSDs will be different, but the logical addresses can all be represented as DIE0-DIE(N-1).

[0078] In step S105, a second mapping table between the host and the solid-state drive is established based on the logical address of the physical DIE.

[0079] In this step, an FTL table, or second mapping table, is established between the host and the SSD. This second mapping table uses the logical address of the physical die as the physical address of the SSD's flash memory. The FTL is a mapping table maintained by the system that establishes a correspondence between the host's logical block addresses (LBAs) and the flash memory's physical block addresses (PBAs), such as an L2P table. As mentioned in the previous step, as long as the number of physical dies on the SSD is the same, the physical dies on different SSDs can have different distributions; that is, different physical dies have different physical addresses, but their corresponding logical addresses remain the same. Therefore, for the host, the flash memory's physical address (PBA) does not change when the second mapping table is established. Thus, only one second mapping table needs to be established to be applicable to multiple SSDs.

[0080] The second mapping table is the L2P table between the host and the solid-state drive (i.e., the mapping between the logical address of the host and the logical address of the physical DIE of the flash memory chip), while the first mapping table is the mapping table between the logical address and the physical address of the physical DIE inside the flash memory chip.

[0081] In step S106, in response to the host's access request, the physical address of the physical DIE is obtained according to the second mapping table and the first mapping table.

[0082] In this step, the solid-state drive (SSD) writes each piece of host logical data into the flash memory address space, correspondingly recording the mapping relationship between the logical address and physical address of each piece of data, thus completing the second mapping table. When the host needs to access the flash memory chip to read data, the SSD reads the data from the flash memory according to the second mapping table and then returns it to the user. Since a first mapping table is also established within the SSD in this embodiment, the physical address of the physical DIE also needs to be read according to the first mapping table. Therefore, when accessing the flash memory chip, the physical address of the physical DIE needs to be obtained sequentially according to the second mapping table and the first mapping table.

[0083] This step can also be seen as a method of accessing a solid-state drive, which mainly includes: obtaining the logical address of the physical DIE to be accessed from the access request; obtaining the physical address of the physical DIE to be accessed from the second mapping table; and determining and accessing the physical DIE to be accessed based on the physical address of the physical DIE to be accessed.

[0084] In this embodiment, using the mapping method described above, the firmware FTL establishment only considers the logical address of the physical DIE to be used, without considering the actual physical address of the physical DIE. This eliminates the need to repeatedly establish the FTL mapping table between the host and the flash memory chip, simplifying the process and reducing data caching. When accessing the flash memory chip, the physical address of the physical DIE can be obtained simply by referring to the second and first mapping tables, making the operation straightforward. Furthermore, as long as the total number of physical DIEs on the SSD remains consistent, the physical DIEs can be distributed in various ways on the SSD, such as on different CH and CE of the flash memory chip, thereby enhancing the firmware's applicability and providing multiple possible SSD design methods.

[0085] In summary, the solid-state drive (SSD) mapping method and SSD provided by this invention establish a second mapping table between the host and the SSD based on the logical address of the physical DIE, while establishing a first mapping table between the logical address and the physical address. This allows a fixed number of physical DIEs to have multiple physical distribution methods on the flash memory chip, improving firmware applicability. When accessing the flash memory chip, the physical address of the actual physical DIE can be read by sequentially referring to the second and first mapping tables, eliminating the need for multiple changes to the mapping relationship between the host and the flash memory chip, saving storage space and improving data reading efficiency. Furthermore, using the channel-chip select pin and LUN bit value to mark the physical address of the physical DIE allows for accurate location of each physical DIE on the flash memory chip, without considering the impact of different chip package types, thus improving the stability of data storage and the diversity of surface mount technology on the SSD. Different types of flash memory chips are packaged on the same solid-state drive, especially DDP, QDP and other types are packaged together with SDP. This can save on package inventory, increase the number of physical dies available, expand storage space, and increase the fault tolerance of surface mount technology. If a surface mount error occurs in a physical die, it can be replaced by another physical die without multiple reworks, thus improving production line and work efficiency.

[0086] The following is passed Figures 7-13 This invention introduces several embodiments of various distribution forms of physical DIEs on solid-state drives.

[0087] Figure 7 A simplified schematic diagram showing the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a first embodiment of the present invention is shown. Figure 8 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a second embodiment of the present invention is shown. Figure 9 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a third embodiment of the present invention is shown.

[0088] Figures 7-9 The embodiments are all illustrated using a single-LUN flash memory chip as an example. Figures 7-9 Each solid-state drive has four physical DIEs.

[0089] like Figure 7As shown, in the first embodiment, there are four channels, CH0-CH3. Each channel has one CE selected, and the CE at the same position (CE0) is selected. Each CE has only one LUN, so the LUN must be selected. The bit value of the LUN is defaulted to 0, that is, the corresponding LUN number is defaulted to 0. In this invention, according to step S1022, the LUN number is defaulted to 0. Therefore, in this embodiment, the mapping relationship between the logical address and physical address of the physical DIE is as follows: DIE 0 corresponds to LUN0-CE0-CH0, DIE 1 corresponds to LUN0-CE0-CH1, DIE 2 corresponds to LUN0-CE0-CH2, and DIE 3 corresponds to LUN0-CE0-CH3.

[0090] In this embodiment, the physical die of each flash memory chip is physically aligned. If there are four empty slots on the PCB, then it can be packaged with four SDPs, each SDP corresponding to one CH. If there are two empty slots on the PCB, two DDPs can be packaged, the first DDP corresponding to CH0 and CH2, and the second DDP corresponding to CH1 and CH3. See also Figure 8 In the second embodiment, physical DIEs are distributed on only two channels (CH0 and CH2), with two CEs (CE0 and CE1) selected on each channel. Each CE has only one LUN. Therefore, in this embodiment, the mapping relationship between the logical address and physical address of the physical DIE is as follows: DIE 0 corresponds to LUN0-CE0-CH0, DIE 1 corresponds to LUN0-CE0-CH2, DIE 2 corresponds to LUN0-CE1-CH0, and DIE 3 corresponds to LUN0-CE1-CH2. The package types that can be used in this embodiment are: if there is at least one empty package slot, then one QDP is packaged; if there are at least two empty package slots, then two DDPs are packaged.

[0091] See Figure 9 In the third embodiment, the chip select pin numbers corresponding to the physical DIEs under different channel numbers are not completely identical. That is, in this embodiment, the physical DIEs on each flash memory chip do not require physical alignment. Figure 7 Similar to the previous embodiment, this embodiment can use 4 SDP packages.

[0092] In this embodiment, the mapping relationship between the logical addresses and physical addresses of the four physical DIEs is as follows: DIE 0 corresponds to LUN0-CE0-CH0, DIE 1 corresponds to LUN0-CE2-CH1, DIE 2 corresponds to LUN0-CE2-CH2, and DIE 3 corresponds to LUN0-CE0-CH3.

[0093] Figure 10A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a fourth embodiment of the present invention is shown.

[0094] like Figure 10 As shown in the example, this embodiment uses a single-LUN flash memory chip as an example, where multiple physical dies do not completely occupy each channel. In this embodiment, there are many empty slots in the package, but the number of physical dies is relatively small. For example, four SDPs are packaged, but only three physical dies are actually needed. Therefore, not every channel has a physical die. Figure 10 In this embodiment, the mapping relationship between the logical addresses and physical addresses of the three physical DIEs is as follows: DIE 0 corresponds to -LUN0-CE0-CH0, DIE1 corresponds to LUN0-CE0-CH1, and DIE 2 corresponds to LUN0-CE0-CH3.

[0095] Figure 11 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a fifth embodiment of the present invention is shown. Figure 12 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a sixth embodiment of the present invention is shown.

[0096] Figures 11-12 The following example uses a single-LUN flash memory chip. The fifth and sixth embodiments further explain step S103 of the mapping method. In this invention, when establishing the first mapping table, if multiple chip select pins under a certain channel correspond to physical DIEs, a mapping relationship is first established sequentially for each channel, and then a mapping relationship is established for multiple physical DIEs under that channel. This mainly includes: first, allocating logical addresses to the physical DIEs under the first chip select pin of each channel according to the channel number; then, allocating logical addresses to multiple physical DIEs under the same channel according to the chip select pin number. That is, firstly, it is ensured that there is a mapping relationship on each CH, and then the process is iterated repeatedly until all DIEs have a mapping relationship.

[0097] like Figure 11As shown, the mapping relationship between the logical addresses and physical addresses of the four physical DIEs is as follows: DIE 0 corresponds to LUN0-CE0-CH0, DIE 1 corresponds to LUN0-CE0-CH1, DIE 2 corresponds to LUN0-CE0-CH3, and DIE 3 corresponds to LUN0-CE1-CH1. That is, the mapping relationship is first established for the first physical DIE on CH0, CH1, and CH3, and then the mapping relationship is established for the second physical DIE on these channels. In this way, CH0, CH1, and CH3 can be processed in parallel, and then CH1 is processed once more. Therefore, the following mapping relationship should be avoided: DIE 0 corresponds to LUN0-CE0-CH0, DIE 1 corresponds to LUN0-CE0-CH1, DIE 2 corresponds to LUN0-CE1-CH1, and DIE 3 corresponds to LUN0-CE0-CH3. Since CH1 is adjacent to two physical DIEs that need to be processed, such a mapping relationship will cause CH0 and CH1 to be processed in parallel while CH3 is idle. After CH1 and CE0 are processed, CH3 will be processed in parallel with CH1 again, which will waste resources and consume time.

[0098] like Figure 12 As shown, the mapping relationship between the logical addresses and physical addresses of the six physical DIEs in this embodiment is as follows: DIE 0 corresponds to LUN0-CE0-CH0, DIE 1 corresponds to LUN0-CE0-CH1, DIE 2 corresponds to LUN0-CE1-CH2, DIE 3 corresponds to LUN0-CE0-CH3, DIE 4 corresponds to LUN0-CE1-CH0, and DIE 5 corresponds to LUN0-CE2-CH2. The mapping relationship of DIE 0 to DIE 4 ensures that there is a mapping relationship on each CH. Therefore, CH0-CH3 are processed in parallel first, and the CHs corresponding to DIE 4-DIE 5 are processed in parallel. This results in higher data processing efficiency, faster and more stable establishment of the first mapping table, and a significant reduction in data processing time. This embodiment avoids the following mapping relationship: DIE 0 corresponds to LUN0-CE0-CH0, DIE 1 corresponds to LUN0-CE1-CH0, DIE 2 corresponds to LUN0-CE0-CH1, DIE 3 corresponds to LUN0-CE1-CH2, DIE 4 corresponds to LUN0-CE2-CH2, and DIE 5 corresponds to LUN0-CE0-CH3. Under this mapping relationship, DIE 0 is processed first, then DIE 1, DIE 2, and DIE 3 are processed in parallel, and then DIE 4 and DIE 5 are processed in parallel, which requires a long processing time and has low processing efficiency.

[0099] Therefore, prioritizing the establishment of mapping relationships for each channel with physical DIEs to enable parallel processing, and then processing the mapping relationships of multiple physical DIEs under a single channel, can improve data processing speed and increase processing efficiency.

[0100] Figure 13 A simplified schematic diagram of the overall distribution of channels and chip select pins on a flash memory chip in a solid-state drive according to a seventh embodiment of the present invention is shown.

[0101] like Figure 13 The diagram shows a mixed mounting of single-LUN and multi-LUN chips, illustrated using two single-LUN chips and two multi-LUN chips as an example. CH0-CE0 has two LUN strobes, CH1-CE0 has two LUN strobes, and CH2-CE0 and CH3-CE0 each have one LUN strobe. The mapping relationship between the logical address and physical address of the corresponding physical DIEs is as follows: DIE 0 corresponds to LUN0-CE0-CH0, DIE 1 corresponds to LUN1-CE0-CH0, DIE 2 corresponds to LUN0-CE0-CH1, DIE 3 corresponds to LUN1-CE0-CH1, DIE 4 corresponds to LUN0-CE0-CH2, and DIE 5 corresponds to LUN0-CE0-CH3. When a physical DIE is damaged, for example, if DIE 2 is a bad LUN, another physical DIE can be selected to replace DIE 2.

[0102] In summary, the solid-state drive and its mapping method of this invention, when the total number of physical dies on the solid-state drive is the same, do not require consideration of the physical location of the physical dies. Therefore, it can realize various distribution methods of physical dies for solid-state drives, resulting in better firmware applicability. This solid-state drive also supports single-LUN and multi-LUN mixed mounting on the same PCB, and even allows flash memory with only one LUN bit available in a multi-LUN chip and single-LUN flash memory to be mounted on the same PCB simultaneously, improving firmware applicability and solid-state drive production efficiency. It also supports mounting flash memory chips of different package types on the same PCB, balancing the needs for package space and the number of dies.

[0103] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A mapping method for a solid-state drive (SSD), wherein the SSD includes a controller and multiple flash memory chips, the multiple flash memory chips communicating with a flash memory controller within the controller via multiple channels, each channel corresponding to one or more chip select pins in each flash memory chip, and each chip select pin controlling one or more physical DIEs, wherein, The mapping method includes: Obtain the physical address of each physical DIE on the flash memory chip. The physical address is characterized by the channel number, chip select pin number and LUN number corresponding to the physical DIE. Obtain the number of physical DIEs and establish the logical address of each physical DIE accordingly; Establish a mapping relationship between the logical address of the physical DIE and the physical address of the physical DIE, and store it as a first mapping table; A second mapping table between the host and the solid-state drive is established based on the logical address of the physical DIE; In response to the host's access request, the physical address of the physical DIE is obtained according to the second mapping table and the first mapping table. The step of obtaining the physical address of each physical DIE on the flash memory chip includes: Locate the physical DIE on the flash memory chip and read its corresponding channel number and chip select pin number; Read the information of the flash memory chip, and record the LUN number according to the number of DIEs contained in the flash memory chip. If each flash memory chip contains only one DIE, the LUN number is 0 by default; if each flash memory chip contains multiple DIEs, the LUN number corresponds to the actual LUN bit value where the physical DIE is located.

2. The mapping method according to claim 1, wherein, Before the step of obtaining the physical address of each physical DIE on the flash memory chip, the following steps are also included: The package type of the flash memory chip is selected based on the number of physical DIEs that need to be selected and the number of package slots on the solid-state drive that can be used to package the flash memory chip.

3. The mapping method according to claim 2, wherein, The package types include SDP, DDP, QDP, and ODP.

4. The mapping method according to claim 1, wherein, The chip select pin numbers corresponding to the physical DIE under different channel numbers are not exactly the same.

5. The mapping method according to claim 1, wherein, The multiple physical DIEs do not completely occupy each of the channels.

6. The mapping method according to claim 1, wherein, When establishing the first mapping table, if multiple chip select pins under a certain channel correspond to physical DIEs, a mapping relationship is first established for each channel in sequence, and then a mapping relationship is established for multiple physical DIEs under that channel.

7. The mapping method according to claim 6, wherein, First, establish a mapping relationship for each channel sequentially. Then, establish a mapping relationship for multiple physical DIEs under the same channel. This includes: first, assigning logical addresses to the physical DIEs under the first chip select pin of each channel according to the channel number; and then assigning logical addresses to multiple physical DIEs under the same channel according to the chip select pin number.

8. A solid-state drive (SSD) for performing the mapping method according to any one of claims 1-7, wherein, The solid-state drive includes: A controller, connected to and communicating with a host, the controller including a flash memory controller; and Multiple flash memory chips are connected to the flash memory controller via multiple channels. Each flash memory chip includes one or more physical DIEs. Each channel corresponds to one or more chip select pins in each flash memory chip, and each chip select pin controls one or more physical DIEs. Among them, the chip select pin numbers corresponding to the physical DIEs on multiple flash memory chips are not exactly the same under different channels.

9. The solid-state drive according to claim 8, wherein, The multiple flash memory chips packaged on the solid-state drive include one or more of SDP, DDP, QDP and ODP.

10. The solid-state drive according to claim 8, wherein, Of the plurality of flash memory chips, in a portion of the flash memory chips each chip select pin controls only one DIE, while in the other portion of the flash memory chips each chip select pin controls multiple DIEs.

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