Signal output control circuit and lin transceiver

Abstract

The application provides a signal output control circuit and a LIN transceiver, wherein the output end of the circuit is connected with a LIN bus, and the circuit comprises an input signal control module, a stable voltage output module, a driving module and a power module; wherein the first input end of the input signal control module is connected with an external chip, the output end of the input signal control module is connected with the first end of the driving module, and the power module is connected with the second input end of the input signal control module, the second end of the driving module and the LIN bus respectively. In this way, the stable voltage output module is arranged between the input signal control module and the driving module, so that the stable voltage output module provides stable voltage for the driving module when the output voltage of the input signal control module is zero, thereby reducing the conversion rate of the LIN bus between the recessive state and the dominant state, making the waveform of the LIN bus signal be able to be output according to the preset slope, and further reducing the electromagnetic radiation.

Description

Technical Field

[0001] This invention relates to the field of LIN bus technology, and in particular to a signal output control circuit and a LIN transceiver. Background Technology

[0002] LIN is an abbreviation for Local Interconnect Network, which can be used in various fields such as automobiles. The LIN bus is a low-cost serial communication network defined for automotive distributed electronic systems. It complements other automotive multiplexing networks such as Controller Area Network (CAN) and is suitable for applications that do not have high requirements for network bandwidth, performance, or fault tolerance.

[0003] In existing LIN bus signal output circuits, when the inverting input signal sent to the inverting input terminal of the operational amplifier is high and close to the power supply voltage signal at the non-inverting input terminal, the operational amplifier cannot function properly because the input signal exceeds its specified common-mode input voltage range. Its output signal becomes distorted, and therefore it cannot drive the MOSFET to pull down the LIN bus. At this time, the LIN bus is in a recessive state, and its voltage is at a high potential close to the power supply voltage. As the inverting input signal gradually decreases, the common-mode input voltage of the operational amplifier also decreases until it falls within the normal operating range. At this point, the voltage on the LIN bus is rapidly pulled down, causing the LIN bus to quickly switch from a recessive state to a dominant state. The LIN bus voltage is also rapidly pulled down from a high potential close to the power supply voltage to a lower inverting input signal potential. Because the LIN bus voltage changes too quickly, its output waveform has a steep slope, contains many high-frequency signals, and thus generates high electromagnetic radiation. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a signal output control circuit and a LIN transceiver, thereby reducing the transition rate of the LIN bus between the recessive and dominant states, enabling the slope of the LIN bus signal waveform to be output according to a preset slope, thereby reducing electromagnetic radiation.

[0005] In a first aspect, embodiments of the present invention provide a signal output control circuit. The output terminal of the circuit is connected to a LIN bus. The circuit includes: an input signal control module, a stable voltage output module, a drive module, and a power supply module. The first input terminal of the input signal control module is connected to an external chip, and the output terminal of the input signal control module is connected to the first terminal of the drive module. The power supply module is connected to the second input terminal of the input signal control module, the second terminal of the drive module, and the LIN bus. The power supply module provides a power supply voltage signal. The input signal control module receives a digital signal sent by the external chip and outputs a drive voltage to the stable voltage output module and the drive module. The stable voltage output module acquires the digital signal from the external chip and the drive voltage output by the input signal control module, and outputs a stable voltage to the drive module. The drive module outputs a LIN bus signal with a preset slope.

[0006] Furthermore, the input signal control module includes: a first operational amplifier and a slope control unit; the positive input terminal of the first operational amplifier is connected to the LIN bus and the power supply module, the inverting input terminal of the first operational amplifier is connected to the output terminal of the slope control unit, and the output terminal of the first operational amplifier is connected to the stable voltage output module and the drive module respectively; the input terminal of the slope control unit is connected to an external chip for receiving digital signals sent by the external chip; the slope control unit converts the digital signals into voltage signals with a preset slope, the preset slope voltage signals having rising and falling edges; and sends the preset slope voltage signals to the first operational amplifier; the first operational amplifier generates a drive voltage based on the LIN bus voltage and the preset slope voltage signals, and sends the drive voltage to the drive module.

[0007] Furthermore, the stable voltage output module includes a voltage replication unit and a pre-charge unit connected to each other; wherein, the input terminal of the voltage replication unit is connected to the first operational amplifier; the output terminal of the pre-charge unit is connected to the input terminal of the drive module; the voltage replication unit is used to acquire and store the drive voltage output by the first operational amplifier under normal operating conditions; the pre-charge unit is used to acquire the drive voltage stored in the voltage replication unit, and when the first operational amplifier fails to operate normally, output the stored drive voltage to the drive module to drive the drive module.

[0008] Furthermore, the voltage replication unit includes a first switch, a second switch, a sampling capacitor, a holding capacitor, and a buffer; wherein the first switch, the second switch, and the buffer are connected in series in sequence; one end of the sampling capacitor is connected to the first switch and the second switch; one end of the holding capacitor is connected to the second switch and the buffer; the other ends of the sampling capacitor and the other ends of the holding capacitor are both grounded; the buffer is used to output a stable voltage to the pre-charge unit; the first switch and the second switch alternately close and close to acquire and store the driving voltage.

[0009] Furthermore, the capacitance value of the sampling capacitor is greater than the capacitance value of the holding capacitor.

[0010] Furthermore, the pre-charge unit includes: a second operational amplifier, a third switch, a resistor, and a current source; the negative input terminal of the second operational amplifier is connected to the output terminal of the buffer, and the output terminal of the second operational amplifier is connected to the positive input terminal of the second operational amplifier, the driver module, and the driver module respectively; one end of the resistor is connected to the connection line between the second operational amplifier and the driver module and one end of the third switch respectively, and the other end of the resistor is grounded; the other end of the third switch is connected to the output terminal of the current source; the third switch is used to be closed when the first operational amplifier fails to work properly, so as to output a stable voltage to the driver module.

[0011] Furthermore, the driving module includes a MOSFET; wherein the gate of the MOSFET is connected to the output terminal of the first operational amplifier and the stable voltage output module respectively; the drain of the MOSFET is connected to the LIN bus and the power supply module respectively; the source of the MOSFET is grounded; the MOSFET is used to drive the LIN bus according to the driving voltage or the stable voltage, so that when the LIN bus switches between the hidden state and the dominant state, it outputs a LIN bus signal with a preset slope waveform.

[0012] Furthermore, the power module includes a connected input power supply and a terminating resistor.

[0013] Secondly, embodiments of the present invention provide a LIN transceiver, including a transceiver body and a signal output control circuit as described above; the signal output control circuit is disposed within the transceiver body.

[0014] Furthermore, it also includes a communication module; the communication module is located inside the transceiver body; the communication module is used for communication connection with external chips.

[0015] This invention provides a signal output control circuit and a LIN transceiver. The output of the circuit is connected to a LIN bus. The circuit includes an input signal control module, a stable voltage output module, a driver module, and a power supply module. The first input terminal of the input signal control module is connected to an external chip, and the output terminal of the input signal control module is connected to the first terminal of the driver module. The power supply module is connected to the second input terminal of the input signal control module, the second terminal of the driver module, and the LIN bus. The power supply module provides a power supply voltage signal. The input signal control module receives digital signals sent by the external chip and outputs a driver voltage to the stable voltage output module and the driver module. The stable voltage output module acquires the digital signals from the external chip and the driver voltage output by the input signal control module, and outputs a stable voltage to the driver module. The driver module outputs a LIN bus signal with a preset slope. In this method, by setting a stable voltage output module between the input signal control module and the driver module, the stable voltage output module provides a stable voltage to the driver module when the output voltage of the input signal control module is zero. This reduces the transition rate of the LIN bus between recessive and dominant states, allowing the LIN bus signal waveform to be output according to a preset slope, thereby reducing electromagnetic radiation.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the signal output control circuit provided in Embodiment 1 of the present invention;

[0020] Figure 2 This is a schematic diagram of another signal output control circuit provided in Embodiment 1 of the present invention;

[0021] Figure 3 This is a schematic diagram of a stable voltage output module provided in Embodiment 1 of the present invention;

[0022] Figure 4 This is a digital signal timing diagram and its corresponding switching signal timing diagram provided in Embodiment 1 of the present invention;

[0023] Figure 5 This is a schematic diagram of a LIN transceiver provided in Embodiment 2 of the present invention.

[0024] Icons: 1-Input signal control module; 2-Stable voltage output module; 3-Drive module; 4-Power supply module; 5-External chip; 6-LIN bus; 7-LIN transceiver; 8-Signal output control circuit; 9-Communication module; 11-Slope control unit; 21-Voltage replication unit; 22-Pre-charge unit; 41-Input power supply; 42-Termination resistor. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] LIN transceivers are widely used in industrial control and automotive applications. In LIN communication, the LIN bus rail-to-rail output requires the transceiver to transmit communication waveforms across varying power supply voltages, load resistances, and load capacitances. In many LIN transceiver designs, a slope control unit is used to control the slope of the bus waveform to comply with the electromagnetic radiation limitations for LIN bus outputs specified in IEC 62228-2 2016, "EMC evaluation of integrated circuit transceivers - LIN transceivers".

[0027] The LIN bus is divided into a recessive state and a dominant state. The output stage circuit switches the LIN bus between the recessive and dominant states, and the driver transistor is driven by a slope-controlled amplifier to achieve a fixed rising and falling edge output.

[0028] However, in actual circuits, due to the rail-to-rail input range of the amplifier, when the input signal is close to the high level of the power supply, the amplifier cannot be in amplification mode and cannot effectively clamp the LIN bus with the output signal of the slope control. At this time, it is difficult for the amplifier to pull down the LIN bus. When the common mode of the amplifier input drops to a range sufficient for the amplifier to establish, the LIN bus will quickly drop to the clamping voltage output by the slope control unit. During this period, the LIN bus cannot respond according to the original slope.

[0029] To facilitate understanding of this embodiment, the embodiments of the present invention will be described in detail below.

[0030] Example 1:

[0031] Figure 1 This is a schematic diagram of the signal output control circuit provided in Embodiment 1 of the present invention.

[0032] Figure 2 This is a schematic diagram of another signal output control circuit provided in Embodiment 1 of the present invention.

[0033] Reference Figure 1 The signal output control output terminal is connected to the LIN bus 6. The circuit includes: input signal control module 1, stable voltage output module 2, drive module 3 and power supply module 4; wherein, the first input terminal of the input signal control module 1 is connected to the external chip 5, and the output terminal of the input signal control module 1 is connected to the first terminal of the drive module 3; the power supply module 4 is connected to the second input terminal of the input signal control module 1, the second terminal of the drive module 3 and the LIN bus 6 respectively.

[0034] In existing technologies, the operating voltage range of the LIN bus is 5.5V to 40V. Depending on the application environment, the LIN bus operates at different voltage levels. The voltage waveform output by the LIN bus is a smooth square wave / trapezoidal wave. The electromagnetic radiation value of the LIN bus output must comply with the electromagnetic radiation limits for LIN bus output specified in IEC 62228-2 2016 "EMC evaluation of integrated circuit transceivers - LIN transceivers".

[0035] Here, refer to Figure 2 The power module 4 includes a connected input power supply 41 and a terminating resistor 42.

[0036] Among them, the voltage VBAT of the input power supply 41 and the terminating resistor 42 (R) slave The size of R can be set according to application requirements. slave ≥500Ω, R slave The resistor is typically 30kΩ, and the LIN master node is usually connected to an external 1kΩ pull-up resistor.

[0037] The power module is used to provide power voltage signals.

[0038] Here, the LIN bus is divided into recessive and dominant states based on its voltage potential. The recessive state is when the LIN bus voltage is close to the high level of VBAT, and the dominant state is when the LIN bus voltage is close to the low level of ground.

[0039] Input signal control module 1 is used to receive digital signals sent by external chips and output drive voltage to stable voltage output module 2 and drive module 3.

[0040] In one embodiment, reference is made to Figure 2The input signal control module 1 includes: a first operational amplifier AMP0 and a slope control unit 11.

[0041] The positive input terminal of the first operational amplifier AMP0 is connected to the LIN bus and the power supply module to receive the LIN bus voltage; the inverting input terminal of the first operational amplifier 11 is connected to the output terminal of the slope control unit 11 to receive the voltage signal with a preset slope; the output terminal of the first operational amplifier 11 is connected to the stable voltage output module 2 and the drive module 3.

[0042] The slope control unit 11 is used to receive digital signals sent by an external chip, convert the digital signal Vin into a voltage signal with a preset slope, the voltage signal with the preset slope having a rising edge and a falling edge, the rising edge having a preset rising edge slope, and the falling edge having a preset falling edge slope; and send the voltage signal with the preset slope to the first operational amplifier AMP0; when the digital signal Vin changes from a high level to a low level, correspondingly, the voltage signal with the preset slope output by the slope control unit 11 decreases from the preset voltage signal to zero, wherein the slope at which the preset voltage signal decreases to zero is the preset falling edge slope, and the preset voltage signal is equal to the power supply voltage signal.

[0043] Here, the voltage signal with the preset slope is pre-set according to the actual situation. Specifically, the rising edge slope, falling edge slope, and / or preset voltage signal can be set according to actual needs. When the external chip sends a digital signal V... in The slope control unit 11 outputs a voltage signal with a preset slope and a preset rising edge to the rail.

[0044] The first operational amplifier AMP0 is used to amplify and compare a voltage signal with a preset slope and a LIN bus voltage. When both the preset slope voltage signal and the LIN bus voltage are at a high potential, the input voltage of the first operational amplifier AMP0 exceeds its specified common-mode input voltage. At this time, the first operational amplifier AMP0 cannot work normally, and the output drive voltage is a distorted signal. As the preset slope voltage signal gradually decreases from the power supply voltage to zero, the input voltage of the first operational amplifier AMP0 also gradually decreases to the normal operating range of the common-mode input voltage. At this time, the first operational amplifier AMP0 works normally and outputs a normal drive voltage, which is an undistorted signal.

[0045] The stable voltage output module 2 is used to acquire the digital signal Vin from the external chip and the drive voltage output by the input signal control module 1, and output a stable voltage to the drive module 3.

[0046] The driver module is used to output LIN bus signals with waveforms having a preset slope.

[0047] In one embodiment, reference is made to Figure 2 The driving module includes a MOSFET M0; the gate of the MOSFET is connected to the output terminal of the first operational amplifier and the output terminal of the stable voltage output module 2, respectively; the drain of the MOSFET is connected to the LIN bus and the power supply module, respectively; the source of the MOSFET is grounded. Preferably, the drain of the MOSFET is connected to the power supply module through a first diode D1, the anode of the first diode D1 is electrically connected to the power supply module, and the cathode of the first diode D1 is connected to the LIN bus; and / or, the drain of the MOSFET is connected to the LIN bus through a second diode D2, and the cathode of the second diode D2 is connected to the drain of the MOSFET (not shown in the figure). The first diode D1 is used to prevent reverse current from flowing into the power supply module when the LIN bus voltage is too high, and the second diode D2 is used to prevent negative voltage from the LIN bus from entering the chip.

[0048] The MOSFET is used to drive the LIN bus according to the drive voltage or the stable voltage, so that when the LIN bus switches between the recessive and dominant states, it outputs a LIN bus signal with a preset slope. Ideally, the waveform of the LIN bus signal perfectly matches the waveform of the voltage signal with the preset slope output by the slope control unit 11.

[0049] As described above, in the prior art, when the first operational amplifier AMP0 fails to function properly, its output drive voltage is a distorted signal. This distorted signal cannot drive the MOS transistor in the drive module. The LIN bus voltage is pulled up by the power supply voltage and held at a high potential, unable to follow the output of the slope control unit 11. At this time, the voltage signal waveform output by the slope control unit 11 is a falling edge waveform (its falling edge has a preset falling edge slope), while the LIN bus waveform remains at a high potential without change. As the voltage signal output by the slope control unit 11 continuously decreases, the input voltage of the first operational amplifier AMP0 returns to the normal operating voltage range. The first operational amplifier AMP0 functions normally and outputs an undistorted drive voltage. Under the action of the undistorted drive voltage, the MOS transistor is momentarily turned on, instantly pulling the LIN bus voltage down. Due to the clamping effect of the first operational amplifier AMP0, the LIN bus voltage is now close to the voltage output by the slope control unit 11. Because the LIN bus voltage drops from a high potential to a low potential in a very short time, it will generate a high-frequency electromagnetic interference signal in the circuit, interfering with the operation of other devices in the circuit / chip and reducing the communication effect of the circuit.

[0050] To address the aforementioned technical issues, the stable voltage output module 2 acquires and stores the drive voltage (i.e., the undistorted drive voltage) output by the first operational amplifier AMP0 under normal operating conditions. When the first operational amplifier AMP0 fails to operate normally (i.e., when the drive voltage is distorted), the stored voltage is output to the drive module 3 to drive the MOSFET. After the MOSFET is driven by the stored voltage, it conducts, and the LIN bus voltage is pulled down to a certain extent, no longer remaining at a high potential. At this point, the LIN bus voltage drop is significantly reduced compared to existing technologies, thus greatly reducing the generated electromagnetic interference signals.

[0051] In one embodiment, reference is made to Figure 3 The stable voltage output module 2 includes a voltage replication unit 21 and a pre-charge unit 22 connected to each other; wherein, the input terminal of the voltage replication unit 21 is connected to the first operational amplifier AMP0; and the output terminal of the pre-charge unit 22 is connected to the input terminal of the drive module 3.

[0052] The voltage replication unit 21 is used to acquire and store the drive voltage (i.e., the undistorted drive voltage) output by the first operational amplifier AMP0 under normal operating conditions.

[0053] The pre-charge unit 22 is used to acquire the driving voltage stored in the voltage replication unit. When the first operational amplifier AMP0 fails to work properly (i.e., when the driving voltage is distorted), the stored driving voltage is output to the driving module 3 to drive the driving module.

[0054] Here, when the first operational amplifier AMP0 fails to work properly, the pre-charge unit 22 outputs the stored drive voltage to the drive module 3 to drive the MOS transistor in the drive module.

[0055] In one specific embodiment, reference is made to Figure 3 The voltage replication unit 21 includes a first switch SW1, a second switch SW2, a sampling capacitor C0, a holding capacitor C1, and a buffer BUFFER; wherein the first switch SW1, the second switch SW2, and the buffer BUFFER are connected in series in sequence; one end of the sampling capacitor C0 is connected to the first switch SW1 and the second switch SW2; one end of the holding capacitor C1 is connected to the second switch SW2 and the buffer BUFFER; the other ends of the sampling capacitor C0 and the other ends of the holding capacitor C1 are both grounded.

[0056] A buffer is used to output a stable voltage Vgate to the precharge unit 22.

[0057] The first and second switches alternately close and close to acquire and store the drive voltage.

[0058] Specifically, the voltage replication unit 21 works as follows: When the first operational amplifier AMP0 is working normally, the first switch SW1 remains closed, and the sampling capacitor C0 acquires the driving voltage (at this time, the driving voltage is not distorted), that is, the sampling capacitor C0 is charged, completing the acquisition and storage of the driving voltage. The voltage on the sampling capacitor C0 is the sampling voltage V. C0 When the voltage output by the slope control unit 11 is 0, the first switch SW1 is turned off, disconnecting the sampling capacitor C0 from the first operational amplifier AMP0. The second switch SW2 is closed. Since the sampling capacitor C0 and the holding capacitor C1 are connected, charge moves from the sampling capacitor C0 to the holding capacitor C1, and the sampling voltage V... C0 The sampling capacitor C0 and the holding capacitor C1 are redistributed. After a period of time, the holding capacitor C1 is allocated a stable holding voltage V. C1 Triggered by the rising edge of the digital signal Vin, the second switch SW2 is turned off, disconnecting the connection between the holding capacitor C1 and the sampling capacitor C0, thus maintaining the voltage V. C1 After being regulated by the buffer, a stable voltage Vgate is obtained and output to the pre-charge unit 22. Preferably, after the first switch SW1 is turned off, there is a delay before the second switch SW2 is closed.

[0059] Here, in order to replicate (store) the driving voltage as accurately as possible (without distortion), the capacitance value of the sampling capacitor C0 is greater than the capacitance value of the holding capacitor C1.

[0060] The initial voltage across the holding capacitor C1 can be set to approximately 0.4V. The first switch SW1 and the second switch SW2 can be implemented in different ways, such as using NMOS transistors, PMOS transistors, or complementary CMOS switches. The sampling capacitor C0 and the holding capacitor C1 can be replaced by other semiconductor devices, such as MOM capacitors, MIM capacitors, or MOS capacitors. The second switch SW2 and the holding capacitor C1 can be positioned between the buffer and the sampling capacitor C0, or between the buffer and the pre-charge unit 22. Depending on the specific connection structure of the circuit described above, the buffer can be adaptively adjusted to respond to the sampling voltage V. C0 Voltage stabilization is performed.

[0061] In one embodiment, reference is made to Figure 3The pre-charge unit 22 includes: a second operational amplifier AMP1, a third switch SW3, a resistor Rg, and a current source Ib. The negative input terminal of the second operational amplifier AMP1 is connected to the output terminal of the buffer BUFFER, and the output terminal of the second operational amplifier AMP1 is connected to the positive input terminal of the second operational amplifier AMP1, the driver module 3, and the driver module 3. One end of the resistor Rg is connected to one end of the second operational amplifier AMP1, the driver module 3, and the third switch SW3, and the other end of the resistor Rg is grounded. The other end of the third switch SW3 is connected to the output terminal of the current source Ib.

[0062] Specifically, the output of the second operational amplifier AMP1 is connected to the MOS transistor.

[0063] Here, the current source Ib is output from the internal low-voltage power supply VCC, and the resistor Rg is the gain resistor, the value of which can be set according to the actual situation.

[0064] The working principle of the pre-charge unit 22 is as follows: When triggered by the rising edge of the digital signal Vin, the third switch SW3 is closed, and a stable voltage Vgate is output to the drive module 3 to drive the MOS transistor; after a delay period of obtaining the falling edge of the digital signal Vin, the third switch SW3 is turned off, and the stable voltage Vgate is no longer output to the drive module 3.

[0065] In one embodiment, such as Figure 4 Digital signals are periodic pulse signals.

[0066] In the first signal cycle, the digital signal Vin drops from high to low. The slope control unit 11 outputs a voltage signal with a preset slope (a trapezoidal wave signal with a preset falling edge slope) from high to low. The voltage signal output by the slope control unit 11 begins to decrease at time t0. Since both the LIN bus voltage and the voltage signal output by the slope control unit 11 are at a high potential, the first operational amplifier AMP0 cannot function properly and outputs a distorted drive voltage. At this time, the MOS transistor in the drive module 3 cannot be driven, causing the LIN bus voltage to fail to decrease with the voltage output by the slope control unit 11, and the LIN bus voltage remains at a high potential. After a period of time, at time t1, the voltage output by the slope control unit 11 decreases to a range where the first operational amplifier AMP0 can function normally. At this time, the first operational amplifier AMP0 outputs an undistorted drive voltage, and the MOS transistor is driven, causing the LIN bus voltage to be momentarily pulled down to the voltage output by the slope control unit 11. After the MOS transistor is driven normally, the LIN bus voltage decreases with the voltage output by the slope control unit 11.

[0067] Until the output of the slope control unit 11 drops to 0 (at which point the digital signal Vin is also at a low level), the first switch SW1 switches from closed to off (previously, the first switch SW1 was always in the closed state, and the sampling capacitor C0 was connected to the first operational amplifier AMP0 to acquire and store the driving voltage to obtain the sampling voltage V). C0 After a brief delay (during which the digital signal Vin and the signal output by the slope control unit 11 are still at a low level), at time t2, the second switch SW2 switches from off to closed, and the sampled voltage V... C0 The sampling capacitor C0 and the holding capacitor C1 are redistributed. After a period of time, the holding capacitor C1 is allocated a stable holding voltage V. C1 .

[0068] When the second signal cycle begins, the digital signal Vin changes from low to high (i.e., rising edge). At this time, the slope control unit 11 outputs a voltage signal with a preset slope (a trapezoidal wave signal with a preset rising edge slope) that rises from low to high. Triggered by the rising edge of the digital signal Vin, the second switch SW2 is turned off, disconnecting the connection between the holding capacitor C1 and the sampling capacitor C0, and maintaining the voltage V. C1 After being regulated by a buffer, a stable voltage Vgate is obtained. After a short delay, the first switch SW1 and the third switch SW3 close. The third switch SW3 closes to output the stable voltage Vgate to the driver module 3 to drive the MOS transistor, and the first switch SW1 closes to acquire and store the drive voltage output by the first operational amplifier AMP0. The first switch SW1 and the third switch SW3 can be closed simultaneously (not shown in the figure) or not simultaneously.

[0069] As the MOSFET turns on under the drive of the stable voltage Vgate, the LIN bus voltage begins to drop, and to some extent follows the voltage changes of the slope control unit 11. At this time, the stable voltage Vgate has not yet reached the voltage value V that can fully drive the MOSFET. M Therefore, the MOSFET is not operating in its full state. When the MOSFET is in its full state, the LIN bus voltage waveform perfectly matches and follows the voltage waveform with the preset slope output by the slope control unit 11, and the LIN bus output is a complete and smooth trapezoidal wave.

[0070] After the falling edge of the digital signal Vin is acquired, the third switch SW3 is turned off after a delay, and the stable voltage Vgate is no longer output to the drive module 3. At this time, the voltage signal output by the slope control unit 11 (a trapezoidal wave signal with a preset falling edge slope) continues to decrease until the first operational amplifier AMP0 is working normally (at this time, the drive voltage is not distorted). The MOS transistor works in full under the action of the drive voltage, and the LIN bus voltage decreases along with the voltage output by the slope control unit 11.

[0071] After n signal cycles, since the sampling capacitor C0 samples the driving voltage in each signal cycle and performs voltage redistribution between the sampling capacitor C0 and the holding capacitor C1, the holding voltage V on the holding capacitor C1 is thus reduced. c1 The voltage will gradually approach the driving voltage of MOSFET M0 under the current operating conditions, causing MOSFET M0 to gradually approach its fully operating state. This allows the LIN bus voltage output waveform to fit and follow the waveform output by the slope control unit 11. Here, n is related to the capacitance ratio between C1 and C0.

[0072] This invention provides a signal output control circuit. By setting a stable voltage output module between the input signal control module and the drive module, the stable voltage output module provides a stable voltage to the drive module when the output signal of the input signal control module is distorted. This reduces the switching rate of the LIN bus between the recessive and dominant states, improves the waveform continuity of the LIN bus signal output, and further reduces electromagnetic radiation.

[0073] Example 2:

[0074] Figure 5 This is a schematic diagram of a LIN transceiver provided in Embodiment 2 of the present invention.

[0075] Reference Figure 5 The LIN transceiver 7 includes a transceiver body and the aforementioned signal output control circuit 8; the signal output control circuit 8 is located within the transceiver body.

[0076] It also includes a communication module 9; the communication module 9 is located inside the transceiver body; the communication module 9 is used for communication connection with external chips.

[0077] This invention provides a LIN transceiver. The output of the circuit is connected to a LIN bus. The circuit includes an input signal control module, a stable voltage output module, a driver module, and a power supply module. The first input terminal of the input signal control module is connected to an external chip, and the output terminal of the input signal control module is connected to the first terminal of the driver module. The power supply module is connected to the second input terminal of the input signal control module, the second terminal of the driver module, and the LIN bus. The power supply module provides a power supply voltage signal. The input signal control module receives digital signals sent by the external chip and outputs a drive voltage to the stable voltage output module and the driver module. The stable voltage output module acquires the digital signals from the external chip and the drive voltage output by the input signal control module, and outputs a stable voltage to the driver module. The driver module outputs a LIN bus signal with a preset slope. This method achieves continuous and complete waveform output from the LIN bus under different power supply voltages and load applications using very few components, thereby resulting in lower output electromagnetic radiation.

[0078] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and apparatus described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0079] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0080] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0081] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0082] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A signal output control circuit, characterized in that, The output terminal of the circuit is connected to the LIN bus. The circuit includes: an input signal control module, a stable voltage output module, a driver module, and a power supply module. The first input terminal of the input signal control module is connected to an external chip, and the output terminal of the input signal control module is connected to the first terminal of the driver module. The power supply module is connected to the second input terminal of the input signal control module, the second terminal of the driver module, and the LIN bus. The power module is used to provide a power voltage signal; The input signal control module is used to receive digital signals sent by the external chip and output driving voltage to the stable voltage output module and the driving module; The stable voltage output module is used to acquire the digital signal and the driving voltage output by the input signal control module, and output a stable voltage to the driving module. The driving module is used to output a LIN bus signal with a waveform having a preset slope; The input signal control module includes: a first operational amplifier and a slope control unit; The positive input terminal of the first operational amplifier is connected to the LIN bus and the power supply module, the inverting input terminal of the first operational amplifier is connected to the output terminal of the slope control unit, and the output terminal of the first operational amplifier is connected to the stable voltage output module and the drive module respectively. The input terminal of the slope control unit is connected to the external chip and is used to receive digital signals sent by the external chip. The slope control unit converts the digital signal into a voltage signal with the preset slope and sends the voltage signal with the preset slope to the first operational amplifier; wherein the voltage signal with the preset slope is equal to the power supply voltage signal; The first operational amplifier is used to generate the driving voltage based on the LIN bus voltage and the voltage signal with the preset slope, and send the driving voltage to the driving module; The stable voltage output module includes a voltage replication unit and a pre-charge unit connected to each other; wherein, the input terminal of the voltage replication unit is connected to the first operational amplifier; and the output terminal of the pre-charge unit is connected to the input terminal of the drive module. The voltage replication unit is used to acquire and store the driving voltage output by the first operational amplifier under normal operating conditions; The pre-charge unit is used to acquire the driving voltage stored in the voltage replication unit, and when the first operational amplifier cannot work properly, output the stored driving voltage to the driving module to drive the driving module.

2. The circuit according to claim 1, characterized in that, The voltage replication unit includes a first switch, a second switch, a sampling capacitor, a holding capacitor, and a buffer; wherein the first switch, the second switch, and the buffer are connected in series in sequence; one end of the sampling capacitor is connected to the first switch and the second switch; one end of the holding capacitor is connected to the second switch and the buffer; the other ends of the sampling capacitor and the other ends of the holding capacitor are both grounded; The buffer is used to output the stable voltage to the pre-charge unit; The first switch and the second switch are alternately closed and closed to acquire and store the driving voltage.

3. The circuit according to claim 2, characterized in that, The capacitance value of the sampling capacitor is greater than the capacitance value of the holding capacitor.

4. The circuit according to claim 3, characterized in that, The pre-charge unit includes: a second operational amplifier, a third switch, a resistor, and a current source; The negative input terminal of the second operational amplifier is connected to the output terminal of the buffer, and the output terminal of the second operational amplifier is connected to the positive input terminal of the second operational amplifier, the driving module, and the driving module, respectively; one end of the resistor is connected to the connection line between the second operational amplifier and the driving module and one end of the third switch, respectively, and the other end of the resistor is grounded; the other end of the third switch is connected to the output terminal of the current source. The third switch is used to be in a closed state when the first operational amplifier fails to work properly, so as to output the stable voltage to the drive module.

5. The circuit according to claim 4, characterized in that, The driving module includes a MOS transistor; wherein the gate of the MOS transistor is connected to the output terminal of the first operational amplifier and the stable voltage output module respectively; the drain of the MOS transistor is connected to the LIN bus and the power supply module respectively; and the source of the MOS transistor is grounded. The MOS transistor is used to drive the LIN bus according to the driving voltage or the stable voltage, so that when the LIN bus switches between a recessive state and a dominant state, it outputs a LIN bus signal with a waveform having the preset slope.

6. The circuit according to claim 5, characterized in that, The power module includes a connected input power supply and a terminating resistor.

7. A LIN transceiver, characterized in that, It includes a transceiver body and a signal output control circuit as described in any one of claims 1-6; the signal output control circuit is disposed within the transceiver body.

8. The LIN transceiver according to claim 7, characterized in that, It also includes a communication module; the communication module is disposed within the transceiver body; the communication module is used for communication connection with an external chip.

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