A programmable general logic interface circuit
Patent Information
- Application Number
- CN202310057963.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-19
- Publication Date
- 2026-10-27
- Estimated Expiration
- 2043-01-19
AI Technical Summary
GPIO的优点是接口可以设置的很灵活，但缺点是需要软件进行大量地编程，浪费开发时间而且无法实现通讯的高效率
[0014]与现有技术相比，本发明所达到的有益效果是：本发明提供了一种可编程通用逻辑接口电路，它通过用户的CPU程序修改本接口中的寄存器配置实现各类常用芯片的接口时序要求，一方面它既可以解决如SPI等特定协议、固定管脚类接口不灵活的问题，如芯片需要和SRAM芯片通讯，它需要有时钟、读、写、地址和数据等信号，如果用SPI、I2C和UART类接口是无法实现和SRAM芯片通讯的；另一方面它还可以解决GPIO这类接口软件开发工作量大、通讯效率低的问题。本发明提供的可编程通用逻辑接口实现了芯片接口的灵活性和高效率的平衡，增加了芯片的市场适用范围。
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Figure CN116028417B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of programmable general logic interface circuit technology, specifically to a programmable general logic interface circuit. Background Technology
[0002] Communication between control chips such as MCUs and other chips typically uses two types of interfaces. One type uses mature hardware interfaces with specific protocols, such as UART (Universal Asynchronous Receiver / Transmitter), which uses two pins (TX and RX) for communication; SPI (Synchronous Serial Peripheral Interface), which uses SCK, MISO, MOSI, and NSS; and I2C (Important Serial Bus), a simple, bidirectional two-wire synchronous serial bus developed by Philips, using two pins (SCL and SDA). These interfaces typically use fewer pins, but both sides must adhere to specific protocol requirements for handshaking, lacking flexibility. The other type uses more mature hardware interfaces, such as General Purpose Input / Output (GPIO). These interfaces are usually configured by software or programs through registers, such as setting them as inputs or outputs, and output pin levels can be high or low. Multiple GPIOs can often be programmed to achieve more complex handshaking communication. The advantage of GPIO is its flexible interface configuration, but the disadvantage is the need for extensive software programming, wasting development time and failing to achieve high communication efficiency. How to implement a logic interface that is both flexible in programming and highly automated in hardware, and improve the compatibility of chip interfaces, is a very important problem that needs to be solved in current applications. Summary of the Invention
[0003] The purpose of this invention is to provide a programmable universal logic interface circuit to solve the problems mentioned in the background art.
[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a programmable general logic interface circuit includes four independent programmable logic units, a register control logic unit, an address generation circuit, a read / write data register, a CPU bus, and an internal control logic unit;
[0005] The programmable logic unit is used to receive signals and generate status signals and control signals according to the internal control logic functions; the register control logic unit is used to configure internal signals and read status signals; the address generation circuit is used to generate a 9-bit output address; the read / write data register is used to generate write data and receive read data; the CPU bus is used to cooperate in completing the timing generation of different read / write registers; the internal control logic unit realizes the correct generation of control signals, addresses and data.
[0006] According to the above technical solution, the four programmable logic units include PLU1, PLU2, PLU3, and PLU4; PLU1, PLU2, PLU3, and PLU4 respectively receive EXT_CLK, Ext_rdy_pin1, Ext_rdy_pin2, Ext_rdy_pin3, Ext_rdy_pin4 signals and Int_ctrl_1, Int_ctrl_2, Int_ctrl_3, Int_ctrl_4 signals, and after receiving the signals, they generate status signals Plu1_sts, Plu2_sts, Plu3_sts, Plu4_sts and control signals Ext_ctrl_pin1, Ext_ctrl_pin2, Ext_ctrl_pin3, Ext_ctrl_pin4 according to the internal control logic function of the PLU.
[0007] According to the above technical solution, the programmable logic units (PLU1, PLU2, PLU3, and PLU4) are four functionally related but independent modules, which can be added or removed as needed in the system. Each PLU internally comprises MUXA, MUXB, MUXC, MUX2-204, MUX2-205, register input signals, a logic function table (LFT), a synchronizer, MUX2-209, a two-input AND gate, and an inverter. MUXA has two input signals, Ext_rdy_pin1 and Int_ctrl_1, which are selected by the PCFG and output as the MuxA signal. MUXB has two input signals, logic level 0 and FSM, which are selected by the PCFG and output as the MuxB signal. MUXC has two input signals. The input signals are FSM and FSM, respectively. After selection by PCFG, the output signal is MuxC. MUX2 selects the external clock EXTCLK and the system clock SYSCLK, and outputs the CKIN signal. The CKIN signal is sent to MUX2, and its signal after passing through the inverter is also sent to another input terminal of MUX2. Finally, after selection by PCFG, the output signal is CKOUT. The register input signals and the logic function table LFT will realize 256 combinational logic functions such as AND, OR, and NOT according to MuxA, MuxB, and MuxC. The synchronizer completes the synchronization of the output logic of the logic function table LFT or the reset and set functions of the synchronizer itself. MUX2 completes the selection of whether the output logic of the logic function table LFT is synchronous output or direct output. The two-input AND gate completes the output enable or disable of the signal.
[0008] According to the above technical solution, the logic function table (LFT) circuit is configured and modified through the register input signal PCFG. The LFT is an eight-input multiplexer, and the bits of PCFG are mapped to the eight multiplexer inputs. The output of the LFT is selected by combining the three signals MuxA, MuxB, and MuxC. The LFT can be used to implement any combinational logic function with three inputs. For example, to implement the combinational logic MuxA and MuxB, for any combination where MuxA and MuxB are 1, the output of the LFT should be 1; while for all other combinations, the output of the LFT should be 0, and PCFG is configured as 11000000.
[0009] According to the above technical solution, the register control logic unit is used to configure the PCFG signal required by the internal control logic unit and PLU internal control, configure the CFG signal required by the address generation circuit, and read the status signal plu_sts of PLU1 to PLU4 according to the read and write timing requirements of the CPU bus.
[0010] According to the above technical solution, the CPU bus is used to generate different timing sequences for reading and writing registers in conjunction with the different CPUs used by PGLI external applications. The present invention uses the AMBA bus used in conjunction with ARM CPU.
[0011] According to the above technical solution, the address generation circuit is used to generate a 9-bit output address: First, the generated address is initialized according to the configuration signal CFG[8:0] output by the register control logic unit to determine the default output address. Then, the register continues to configure bits CFG[10:9]. If these two bits are 00, the subsequent address changes by 1 each time; if they are 01, the subsequent address changes by 2 each time; if they are 10, the subsequent address changes by 4 each time; if they are 11, the subsequent address changes by 8 each time. Simultaneously, the register configures bits CFG[12:11]. If these two bits are 00, the output address is in a high-impedance state; if they are 01, the output address does not change; if they are 10, the output address increments; if they are 11, the output address decrements. The increment or decrement is set by CFG[10:9]; each address change and hold time is controlled by the FSM[2:0] signal output by the internal control logic unit; when FSM[2:0] is 000 (represented by S0 in this invention), the output address is in a high-impedance state; when FSM[2:0] is 001, 010, 011, 100, 101, 110 (represented by S1 to S6 respectively), the output address will increment, decrement, or remain unchanged based on the default address by +1 / +2 / +4 / +8; when FSM[2:0] is 111 (represented by S7 in this invention), the output address is in a high-impedance state by default; through the configuration output by the register control logic unit and the FSM[2:0] signal output by the internal control logic unit, the address generation circuit can flexibly generate various 9-bit addresses.
[0012] According to the above technical solution, the internal control logic unit is used to control the PCFG[31:16] signal output by the register control logic unit. The internal logic control unit circuit will control the input signal, output signal, address signal, and data signal under eight states (S0~S7) according to the configuration of PCFG[31:16]. S0 is the IDLE state, also called the initial state, S2~S6 are intermediate states, and S7 is the stop state. In the S0 state, PCFG
[31] is configured as 1 (write operation), PCFG
[30] is configured as 1 (16-bit data width), PCFG
[29] is configured as 0 (the next external state is high impedance state), PCFG
[28] is configured as 1 (update data in the next state), PCFG[31:16] is configured as 1, PCFG[31:16] is configured as 1, PCFG[31:16] is configured as 0, PCFG
[29] is configured as 0 (the next external state is high impedance state), PCFG
[28] is configured as 1 (update data in the next state), PCFG[31:16] is configured as 1, ... FG
[27] is 1 (PLU1 enabled), PCFG
[23] is 1 (next state jump based on Ext_rdy_pin signal), PCFG[22:18] is 00000 (each state lasts for 1 clock cycle), PCFG
[17] is 0 (Ext_rdy_pin synchronizes with EXTCLK signal), PCFG
[16] is 1 (EXTCLK is output); PCFG[15:8] is 00010000 (LFT_OUT equals MuxA), PCFG[7] is set to 0 (Ext_rdy_pin selected), PCFG[6:5] is 00, PCFG[4] is 0 (SYSCLK selected), PCFG[3] is 0. PCFG[2] is 0 (synchronizer not reset), PCFG[1] is 0 (LFT_OUT direct output selected), PCFG[0] is 1 (Ext_ctrl_pin1 output enabled), CFG[12:11] is 10 (next address increment), CFG[10:9] is 00 (add one mode), CFG[8:0] is A (initial address), DAT[15:0] is D0 (initial data); According to the above configuration, in S0 state, when the Ext_rdy_pin pin input is high, regardless of whether Int_ctrl_1 is 0 or 1, the MuxA output is high, and LFT_OUT equals MuxA. When the signal is high, the output value of Ext_ctrl_pin1 is also high; at the same time, in the S0 state, WDAT[15:0] is in a high-impedance state by default, and ADDR[8:0] is in a high-impedance state by default; since PCFG
[23] is 1, when Ext_rdy_pin1 is high and continues for one EXTCLK clock cycle, it will automatically jump to the S2 state; S1 is the start state, and according to the above PCFG[31:0] signal, CFG[12:0] and DAT[15:0] configuration, the output value of Ext_ctrl_pin1 will be 0 as Ext_rdy_pin1 changes, and the WDAT data will become the initial setting value D0 of DAT[15:0];By analogy, the final states of the input and output pins, as well as the final values of the address and data, can be obtained in states S2 to S7.
[0013] According to the above technical solution, the read / write data register is used to generate write data and receive read data; when PCFG
[31] is 0, it indicates a read operation, and the module needs to perform a register read operation; when PCFG
[31] is 1, it indicates a write operation, and the module needs to perform a write address generation operation; when PCFG
[30] is 0, it indicates 8-bit data; when PCFG
[30] is 1, it indicates 16-bit data; when PCFG
[31] is 0 and PCFG
[29] is 0, it indicates no read operation; when PCFG
[31] is 0 and PCFG
[29] is 1, it indicates that a read operation is started, external data is sampled, and the sampled data is placed into the data register; when PCFG
[31] is 1 and PCFG
[29] is 0, it indicates no write data, and the external write data bus WDAT[15:0] is not started. [] is in a high-impedance state; when PCFG
[31] is 1 and PCFG
[29] is 1, the write data configured by the register control logic unit is sent to the external write data bus WDAT[15:0]; when PCFG
[28] is 0, it indicates that the next state data is held; when PCFG
[28] is 1, it indicates that the next state data is updated, and the specific update value is determined by PCFG
[29] ; the FSM[2:0] signal (S0~S7) output by the internal control logic unit controls each data change; when it is S0, the write data WDAT is usually in a high-impedance state; when it is S7, the write data WDAT is in a high-impedance state by default; through the configuration output by the register control logic unit and the FSM[2:0] signal output by the internal control logic unit, the read and write register circuit can flexibly read or generate data of different widths.
[0014] Compared with existing technologies, the beneficial effects achieved by this invention are as follows: This invention provides a programmable universal logic interface circuit, which, through user CPU program modification of register configurations in this interface, fulfills the timing requirements of various commonly used chips. On the one hand, it solves the inflexibility problem of specific protocol and fixed-pin interfaces such as SPI. For example, if a chip needs to communicate with an SRAM chip, it requires clock, read, write, address, and data signals, which cannot be achieved using SPI, I2C, and UART interfaces. On the other hand, it also solves the problems of high software development workload and low communication efficiency of interfaces such as GPIO. The programmable universal logic interface provided by this invention achieves a balance between flexibility and high efficiency in chip interfaces, increasing the market applicability of the chips. Attached Figure Description
[0015] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:
[0016] Figure 1 This is a circuit diagram of a Programmable General-Purpose Logic Interface (PGLI);
[0017] Figure 2 This is a circuit diagram of a programmable logic unit (PLU1);
[0018] Figure 3 It is a schematic diagram of a certain waveform generated by the internal logic control unit circuit;
[0019] Figure 4 It is a logical function table;
[0020] Figure 5 It is the register table PCFG
[25] -PCFG
[31] of the register control unit;
[0021] Figure 6 It is the register table PCFG
[24] -PCFG
[17] of the register control unit;
[0022] Figure 7 It is the register table PCFG[0]-PCFG
[16] of the register control unit;
[0023] Figure 8 These are the register tables CFG[0]-CFG
[12] , DATA[0]-DATA
[15] , and plu_sts of the register control unit;
[0024] In the diagram, 101, PLU1; 102, PLU2; 103, PLU3; 104, PLU4; 105, Register control logic unit; 106, CPU bus; 107, Address generation circuit; 108, Read / write data register; 109, Internal control logic unit; 201, MUXA; 202, MUXB; 203, MUXB; 206, Register input signal PCFG[15:8]; 207, LFT module; 208, Synchronizer; 210, AND gate; 211, Inverter. Detailed Implementation
[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0026] Please see Figures 1-8 The present invention provides a technical solution: a programmable general logic interface circuit includes four independent programmable logic units, a register control logic unit, an address generation circuit, a read / write data register, a CPU bus, and an internal control logic unit;
[0027] The programmable logic unit is used to receive signals and generate status signals and control signals according to the internal control logic functions; the register control logic unit is used to configure internal signals and read status signals; the address generation circuit is used to generate a 9-bit output address; the read / write data register is used to generate write data and receive read data; the CPU bus is used to cooperate in completing the timing generation of different read / write registers; the internal control logic unit realizes the correct generation of control signals, addresses and data.
[0028] According to the above technical solution, the four programmable logic units include PLU1, PLU2, PLU3, and PLU4; PLU1, PLU2, PLU3, and PLU4 respectively receive EXT_CLK, Ext_rdy_pin1, Ext_rdy_pin2, Ext_rdy_pin3, Ext_rdy_pin4 signals and Int_ctrl_1, Int_ctrl_2, Int_ctrl_3, Int_ctrl_4 signals, and after receiving the signals, they generate status signals Plu1_sts, Plu2_sts, Plu3_sts, Plu4_sts and control signals Ext_ctrl_pin1, Ext_ctrl_pin2, Ext_ctrl_pin3, Ext_ctrl_pin4 according to the internal control logic function of the PLU.
[0029] According to the above technical solution, the programmable logic units (PLU1, PLU2, PLU3, and PLU4) are four functionally related but independent modules, which can be added or removed as needed in the system. Each PLU internally comprises MUXA, MUXB, MUXC, MUX2-204, MUX2-205, register input signals, a logic function table (LFT), a synchronizer, MUX2-209, a two-input AND gate, and an inverter. MUXA has two input signals, Ext_rdy_pin1 and Int_ctrl_1, which are selected by the PCFG and output as the MuxA signal. MUXB has two input signals, logic level 0 and FSM, which are selected by the PCFG and output as the MuxB signal. MUXC has two input signals. The input signals are FSM and FSM, respectively. After selection by PCFG, the output signal is MuxC. MUX2 selects the external clock EXTCLK and the system clock SYSCLK, and outputs the CKIN signal. The CKIN signal is sent to MUX2, and its signal after passing through the inverter is also sent to another input terminal of MUX2. Finally, after selection by PCFG, the output signal is CKOUT. The register input signals and the logic function table LFT will realize 256 combinational logic functions such as AND, OR, and NOT according to MuxA, MuxB, and MuxC. The synchronizer completes the synchronization of the output logic of the logic function table LFT or the reset and set functions of the synchronizer itself. MUX2 completes the selection of whether the output logic of the logic function table LFT is synchronous output or direct output. The two-input AND gate completes the output enable or disable of the signal.
[0030] According to the above technical solution, the logic function table (LFT) circuit is configured and modified through the register input signal PCFG. The LFT is an eight-input multiplexer, and the bits of PCFG are mapped to the eight multiplexer inputs. The output of the LFT is selected by combining the three signals MuxA, MuxB, and MuxC. The LFT can be used to implement any combinational logic function with three inputs. For example, to implement the combinational logic MuxA and MuxB, for any combination where MuxA and MuxB are 1, the output of the LFT should be 1; while for all other combinations, the output of the LFT should be 0, and PCFG is configured as 11000000.
[0031] According to the above technical solution, the register control logic unit is used to configure the PCFG signal required by the internal control logic unit and PLU internal control, configure the CFG signal required by the address generation circuit, and read the status signal plu_sts of PLU1 to PLU4 according to the read and write timing requirements of the CPU bus.
[0032] According to the above technical solution, the CPU bus is used to generate different timing sequences for reading and writing registers in conjunction with the different CPUs used by PGLI external applications. The present invention uses the AMBA bus used in conjunction with ARM CPU.
[0033] According to the above technical solution, the address generation circuit is used to generate a 9-bit output address: First, the generated address is initialized according to the configuration signal CFG[8:0] output by the register control logic unit to determine the default output address. Then, the register continues to configure bits CFG[10:9]. If these two bits are 00, the subsequent address changes by 1 each time; if they are 01, the subsequent address changes by 2 each time; if they are 10, the subsequent address changes by 4 each time; if they are 11, the subsequent address changes by 8 each time. Simultaneously, the register configures bits CFG[12:11]. If these two bits are 00, the output address is in a high-impedance state; if they are 01, the output address does not change; if they are 10, the output address increments; if they are 11, the output address decrements. The increment or decrement is set by CFG[10:9]; each address change and hold time is controlled by the FSM[2:0] signal output by the internal control logic unit; when FSM[2:0] is 000 (represented by S0 in this invention), the output address is in a high-impedance state; when FSM[2:0] is 001, 010, 011, 100, 101, 110 (represented by S1 to S6 respectively), the output address will increment, decrement, or remain unchanged based on the default address by +1 / +2 / +4 / +8; when FSM[2:0] is 111 (represented by S7 in this invention), the output address is in a high-impedance state by default; through the configuration output by the register control logic unit and the FSM[2:0] signal output by the internal control logic unit, the address generation circuit can flexibly generate various 9-bit addresses.
[0034] According to the above technical solution, the internal control logic unit is used to control the PCFG[31:16] signal output by the register control logic unit. The internal logic control unit circuit will control the input signal, output signal, address signal, and data signal under eight states (S0~S7) according to the configuration of PCFG[31:16]. S0 is the IDLE state, also called the initial state, S2~S6 are intermediate states, and S7 is the stop state. In the S0 state, PCFG
[31] is configured as 1 (write operation), PCFG
[30] is configured as 1 (16-bit data width), PCFG
[29] is configured as 0 (the next external state is high impedance state), PCFG
[28] is configured as 1 (update data in the next state), PCFG[31:16] is configured as 1, PCFG[31:16] is configured as 1, PCFG[31:16] is configured as 0, PCFG
[29] is configured as 0 (the next external state is high impedance state), PCFG
[28] is configured as 1 (update data in the next state), PCFG[31:16] is configured as 1, ... FG
[27] is 1 (PLU1 enabled), PCFG
[23] is 1 (next state jump based on Ext_rdy_pin signal), PCFG[22:18] is 00000 (each state lasts for 1 clock cycle), PCFG
[17] is 0 (Ext_rdy_pin synchronizes with EXTCLK signal), PCFG
[16] is 1 (EXTCLK is output); PCFG[15:8] is 00010000 (LFT_OUT equals MuxA), PCFG[7] is set to 0 (Ext_rdy_pin selected), PCFG[6:5] is 00, PCFG[4] is 0 (SYSCLK selected), PCFG[3] is 0. PCFG[2] is 0 (synchronizer not reset), PCFG[1] is 0 (LFT_OUT direct output selected), PCFG[0] is 1 (Ext_ctrl_pin1 output enabled), CFG[12:11] is 10 (next address increment), CFG[10:9] is 00 (add one mode), CFG[8:0] is A (initial address), DAT[15:0] is D0 (initial data); According to the above configuration, in S0 state, when the Ext_rdy_pin pin input is high, regardless of whether Int_ctrl_1 is 0 or 1, the MuxA output is high, and LFT_OUT equals MuxA. When the signal is high, the output value of Ext_ctrl_pin1 is also high; at the same time, in the S0 state, WDAT[15:0] is in a high-impedance state by default, and ADDR[8:0] is in a high-impedance state by default; since PCFG
[23] is 1, when Ext_rdy_pin1 is high and continues for one EXTCLK clock cycle, it will automatically jump to the S2 state; S1 is the start state, and according to the above PCFG[31:0] signal, CFG[12:0] and DAT[15:0] configuration, the output value of Ext_ctrl_pin1 will be 0 as Ext_rdy_pin1 changes, and the WDAT data will become the initial setting value D0 of DAT[15:0];By analogy, the final states of the input and output pins, as well as the final values of the address and data, can be obtained in states S2 to S7.
[0035] According to the above technical solution, the read / write data register is used to generate write data and receive read data: when PCFG
[31] is 0, it indicates a read operation, and the module needs to perform a register read operation; when PCFG
[31] is 1, it indicates a write operation, and the module needs to perform a write address generation operation; when PCFG
[30] is 0, it indicates 8-bit data; when PCFG
[30] is 1, it indicates 16-bit data; when PCFG
[31] is 0 and PCFG
[29] is 0, it indicates no read operation; when PCFG
[31] is 0 and PCFG
[29] is 1, it indicates that a read operation has been started, external data has been sampled, and the sampled data has been placed into the data register; when PCFG
[31] is 1 and PCFG
[29] is 0, it indicates that no data has been written, and the external write data bus WDAT[15:0] is not started. [] is in a high-impedance state; when PCFG
[31] is 1 and PCFG
[29] is 1, the write data configured by the register control logic unit is sent to the external write data bus WDAT[15:0]; when PCFG
[28] is 0, it indicates that the next state data is held; when PCFG
[28] is 1, it indicates that the next state data is updated, and the specific update value is determined by PCFG
[29] ; the FSM[2:0] signal (S0~S7) output by the internal control logic unit controls each data change; when it is S0, the write data WDAT is usually in a high-impedance state; when it is S7, the write data WDAT is in a high-impedance state by default; through the configuration output by the register control logic unit and the FSM[2:0] signal output by the internal control logic unit, the read and write register circuit can flexibly read or generate data of different widths.
[0036] In an embodiment of the present invention, Figure 1 After receiving the EXT_CLK, SYSCLK, PCFG[15:0], FSM[2:0], Ext_rdy_pin1 signals and the Int_ctrl_1 signal, PLU1 presses... Figure 2 The PLU1 internal control logic generates the status signal Plu1_sts and the control signal Ext_ctrl_pin1;
[0037] The register control logic unit 105 completes the output of SYSCLK, PCFG[31:0], CFG[2:0], and DATA[15:0] signals, as well as the reading of status signal plu_sts and data DATA[15:0] according to the read / write timing requirements of the CPU bus 106;
[0038] CPU bus 106, depending on the CPU used by the PGLI external application, generates different timing sequences for reading and writing registers. This invention uses the AMBA bus used with ARM CPU.
[0039] The address generation circuit 107 completes the output of ADDR[8:0] based on the configuration signal CFG[2:0] output by the register control logic unit 105 and the FSM[2:0] signal output by the internal control logic unit 109;
[0040] The read / write data register 108 generates write data WDAT[15:0] based on the FSM[2:0] signal output by the internal control logic unit 109 and the DATA[15:0] signal output by the register control logic unit 105; at the same time, the external CPU can read the external read data RDAT[15:0] stored in the read / write data register 108 through the CPU bus 106 and the register control logic unit 105.
[0041] The internal control logic unit 109 obtains the PCFG[31:16] output by the register control logic unit 105 and the Plu1_sts, Plu2_sts, Plu3_sts and Plu4_sts signals generated by PLU1, PLU2, PLU3 and PLU4, and outputs the FSM[2:0], Int_ctrl_1, Int_ctrl_2, Int_ctrl_3 and Int_ctrl_4 signals to complete the control of the programmable logic units PLU1101, PLU2102, PLU3103, PLU4104, address generation circuit 107 and read / write data register 108, so as to realize the correct generation of control signals, addresses and data.
[0042] Figure 2 In the middle: the external input signal Ext_rdy_pin1 and the internal input signal Int_ctrl_1 and the register output signal PCFG[7] are sent to MUXA201, and the output signal MuxA is generated according to the selection of the FSM[2:0] signal generated by the internal control logic unit; the logic level 0 and the FSM[0] signal generated by the internal control logic unit are sent to MUXB202, and the output signal MuxB is generated according to the selection of the register output signal PCFG[6]; the FSM[2:1] signal generated by the internal control logic unit is sent to MUXB203, and the output signal MuxC is generated according to the selection of the register output signal PCFG[5].
[0043] The external pin clock signal EXTCLK and the internal clock signal SYSCLK are respectively sent to the MUX2204 module. After being selected by PCFG[4], the CKIN signal is input to the input terminal of the MUX2205 module. At the same time, the CKIN signal is sent to another input terminal of the MUX2205 module after passing through the inverter 211. After being selected by PCFG[3], the CKOUT signal is input to the synchronizer 208. The register input signals PCFG[15:8]206 and MuxA, MuxB, and Mux The C signals are all input to the LFT module 207, which generates the output signal LFT_OUT, and sends them to the synchronizer 208 and MUX2209 respectively. The synchronizer 208 receives the control of the CKOUT, PCFG[2] and LFT_OUT signals respectively, and outputs the LFT_DFF signal to the MUX2209. After PCFG[2] selects, the signal output by the MUX2209 is sent to the AND gate 210. The AND gate 210 generates the final output signal Ext_ctrl_pin1 under the control of the PCFG[1] signal.
[0044] Figure 3 The internal logic control unit circuit generates eight states S0 to S7, external pin input signal Ext_rdy_pin1, internal output control signal Int_ctrl_1, external control signal Ext_ctrl_pin1, address output signal ADDR[7:0], and write data signal WDAT[15:0].
[0045] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0046] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A programmable universal logic interface circuit, characterized in that: The programmable general logic interface circuit includes four independent programmable logic units, a register control logic unit, an address generation circuit, a read / write data register, a CPU bus, and an internal control logic unit. The programmable logic unit (PLU) receives signals and generates status signals and control signals according to its internal control logic functions. The register control logic unit configures internal signals and reads status signals. The address generation circuit generates a 9-bit output address. The read / write data register generates write data and receives read data. The CPU bus coordinates the timing of different read / write register operations. The internal control logic unit ensures the correct generation of control signals, addresses, and data. The four independent programmable logic units include PLU1, PLU2, PLU3, and PLU4. PLU1, PLU2, PLU3, and PLU4 receive EXT_CLK, Ext_rdy_pin1, Ext_rdy_pin2, Ext_rdy_pin3, and Ext_rdy_pin4 signals, as well as Int_ctrl_1, Int_ctrl_2, Int_ctrl_3, and Int_ctrl_4 signals, respectively. After receiving the signals, PLU1, PLU2, PLU3, and PLU4 generate status signals Plu1_sts, Plu2_sts, Plu3_sts, and Plu4_sts, and control signals Ext_ctrl_pin1, Ext_ctrl_pin2, Ext_ctrl_pin3, and Ext_ctrl_pin4, respectively, according to the internal control logic function of the PLU. The programmable logic units (PLU1, PLU2, PLU3, and PLU4) are four functionally related but independent modules. Each PLU consists of MUXA, MUXB, MUXC, MUX2-204, MUX2-205, register input signals, a logic function table (LFT), a synchronizer, MUX2-209, a two-input AND gate, and an inverter. The register input signals and the LFT implement AND, OR, and NOT combinational logic functions based on MuxA, MuxB, and MuxC. The synchronizer synchronizes the output logic of the LFT or performs its own reset and set functions. MUX2 selects whether the LFT output logic is synchronous or directly output. The two-input AND gate performs a logical AND operation between the Plu1_sts signal and the PCFG, outputting the Ext_ctrl_pin1 signal.
2. The programmable universal logic interface circuit according to claim 1, characterized in that: The logic function table (LFT) circuit is configured and modified through the register input signal PCFG. The LFT is an eight-input multiplexer, and the bits of PCFG are mapped to the eight multiplexer inputs. The output of the LFT is selected by combining the three signals MuxA, MuxB, and MuxC.
3. The programmable universal logic interface circuit according to claim 2, characterized in that: The register control logic unit is used to configure the PCFG signals required for the internal control logic unit and PLU internal control, configure the CFG signals required for the address generation circuit, and read the status signals of Plu1_sts, Plu2_sts, Plu3_sts, and Plu4_sts according to the read / write timing requirements of the CPU bus.
4. The programmable universal logic interface circuit according to claim 1, characterized in that: The CPU bus is used to cooperate with PGLI external applications, using different CPUs to generate different read and write register timings.
5. A programmable universal logic interface circuit according to claim 1, characterized in that: The address generation circuit is used to generate a 9-bit output address: the generated address is initialized according to the configuration signal CFG output by the register control logic unit to determine the default output address, and the CFG bit is further configured through the register. The address change and holding time are controlled by the FSM signal output by the internal control logic unit. Through the configuration output by the register control logic unit and the FSM signal output by the internal control logic unit, the address generation circuit can generate different 9-bit addresses.
6. The programmable universal logic interface circuit according to claim 1, characterized in that: The internal control logic unit is used to control the programmable logic units PLU1, PLU2, PLU3, PLU4, address generation circuit, and read / write data register according to the PCFG output by the register control logic unit, so as to realize the correct generation of control signals, addresses and data.
7. A programmable universal logic interface circuit according to claim 6, characterized in that: The internal control logic unit circuit is used to control the PCFG signal output by the control logic unit through the register. The internal logic control unit circuit will control the input signal, output signal, address signal, and data signal under eight states S0, S1, S2, S3, S4, S5, S6, and S7 according to the PCFG configuration. S0 is the initial state, S1 is the start state, S2, S3, S4, S5, and S6 are intermediate states, and S7 is the stop state.